Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26567

1

T1

19

T2

195

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22811

1

T1

19

T2

195

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3756

1

T5

2

T12

2

T40

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20254

1

T1

19

T2

195

T3

1

auto[1]

6313

1

T4

1

T7

3

T8

16

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22492

1

T1

19

T2

195

T3

1

auto[1]

4075

1

T5

1

T48

1

T49

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	31	1			T177	1		T121	11		T20	7
values[0]	41	1			T4	1		T55	6		T181	1
values[1]	657	1			T92	27		T225	11		T109	28
values[2]	731	1			T40	16		T92	15		T76	18
values[3]	722	1			T12	1		T108	7		T51	19
values[4]	626	1			T165	1		T66	29		T225	8
values[5]	2822	1			T7	3		T8	16		T9	19
values[6]	753	1			T5	2		T165	1		T92	1
values[7]	686	1			T49	25		T43	1		T165	1
values[8]	728	1			T76	19		T57	1		T226	1
values[9]	1359	1			T3	1		T12	1		T49	3
minimum	17411	1			T1	19		T2	195		T5	31

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	908	1			T4	1		T92	42		T225	11
values[1]	673	1			T12	1		T40	16		T108	7
values[2]	684	1			T165	1		T225	8		T106	15
values[3]	2949	1			T7	3		T8	16		T9	19
values[4]	650	1			T49	5		T225	1		T57	1
values[5]	706	1			T5	2		T40	10		T165	2
values[6]	769	1			T49	25		T43	1		T57	1
values[7]	706	1			T76	19		T58	15		T226	1
values[8]	701	1			T49	3		T36	17		T43	1
values[9]	410	1			T3	1		T12	1		T106	12
minimum	17411	1			T1	19		T2	195		T5	31

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22415

1

T1

19

T2

195

T3

1

auto[1]

4152

1

T8

15

T9

17

T10

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T4	1		T92	12		T225	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T76	13		T46	7		T170	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T40	8		T108	7		T109	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T12	1		T40	8		T284	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T61	3		T274	1		T162	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T165	1		T225	1		T106	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1540	1			T7	3		T8	16		T9	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T106	12		T63	13		T47	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T49	1		T225	1		T57	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T164	13		T244	1		T171	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T165	1		T51	1		T164	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T5	1		T40	10		T165	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T49	12		T43	1		T57	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T244	13		T243	15		T173	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T183	1		T217	13		T179	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T76	10		T58	9		T226	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T49	3		T36	5		T43	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T108	7		T58	11		T30	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T3	1		T27	1		T173	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T12	1		T106	12		T109	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17269	1			T1	19		T2	195		T5	31
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T92	30		T225	10		T109	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T76	5		T46	2		T203	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T109	12		T51	1		T172	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T187	10		T232	6		T131	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T61	3		T274	14		T174	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T225	7		T51	3		T295	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1004	1			T50	8		T59	14		T38	30
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T47	2		T248	10		T124	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T49	4		T169	12		T204	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T164	9		T171	20		T289	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T51	9		T164	11		T183	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T5	1		T76	5		T51	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T49	13		T166	3		T206	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T244	6		T243	12		T218	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T183	12		T217	12		T179	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T76	9		T58	6		T51	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T36	12		T288	4		T15	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T58	9		T217	9		T187	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T27	17		T274	9		T252	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T109	10		T27	2		T179	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T48	1		T33	1		T92	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T177	1		T20	6		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T121	6		T321	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T4	1		T55	4		T175	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T181	1		T256	10		T322	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T92	11		T225	1		T109	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T46	7		T170	1		T203	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T40	8		T92	1		T109	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T40	8		T76	13		T284	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T108	7		T32	2		T186	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T12	1		T51	16		T164	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T66	16		T169	7		T283	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T165	1		T225	1		T106	27
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1493	1			T7	3		T8	16		T9	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T40	10		T63	13		T47	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T51	1		T169	15		T32	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T5	1		T165	1		T92	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T49	12		T43	1		T165	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T76	2		T244	13		T245	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T57	1		T217	13		T179	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T76	10		T226	1		T283	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	350	1			T3	1		T49	3		T36	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	403	1			T12	1		T106	12		T108	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17269	1			T1	19		T2	195		T5	31
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T20	1		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T121	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T55	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T256	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T92	16		T225	10		T109	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T46	2		T203	10		T60	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T92	14		T109	12		T51	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T76	5		T187	10		T232	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T186	2		T61	3		T64	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T51	3		T251	13		T295	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T66	13		T169	11		T218	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T225	7		T124	9		T62	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1028	1			T49	4		T50	8		T59	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T47	2		T164	9		T248	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T51	9		T169	12		T179	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T5	1		T51	13		T171	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T49	13		T164	11		T166	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T76	5		T244	6		T245	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T217	12		T179	6		T203	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T76	9		T187	17		T175	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T36	12		T288	4		T27	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T109	10		T58	15		T51	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T48	1		T33	1		T92	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T4	1		T92	32		T225	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T76	6		T46	7		T170	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T40	1		T108	1		T109	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T12	1		T40	1		T284	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T61	5		T274	15		T162	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T165	1		T225	8		T106	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1343	1			T7	3		T8	1		T9	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T106	1		T63	1		T47	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T49	5		T225	1		T57	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T164	10		T244	1		T171	21
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T165	1		T51	10		T164	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T5	2		T40	1		T165	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T49	14		T43	1		T57	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T244	7		T243	13		T173	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T183	13		T217	13		T179	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T76	10		T58	7		T226	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T49	1		T36	13		T43	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T108	1		T58	10		T30	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T3	1		T27	18		T173	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T12	1		T106	1		T109	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17411	1			T1	19		T2	195		T5	31
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T92	10		T109	14		T55	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T76	12		T46	2		T203	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T40	7		T108	6		T109	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T40	7		T30	6		T187	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T61	1		T174	14		T268	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T106	14		T51	13		T164	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1201	1			T8	15		T9	17		T10	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T106	11		T63	12		T47	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T169	14		T258	16		T267	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T164	12		T171	13		T289	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T164	16		T179	6		T188	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T40	9		T76	1		T163	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T49	11		T166	4		T206	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T244	12		T243	14		T218	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T217	12		T179	9		T188	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T76	9		T58	8		T51	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T49	2		T36	4		T163	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T108	6		T58	10		T30	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T173	13		T252	11		T298	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T106	11		T109	9		T179	14

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T177	1		T20	6		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T121	6		T321	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T4	1		T55	3		T175	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T181	1		T256	8		T322	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T92	17		T225	11		T109	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T46	7		T170	1		T203	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T40	1		T92	15		T109	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T40	1		T76	6		T284	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T108	1		T32	2		T186	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T12	1		T51	6		T164	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T66	14		T169	12		T283	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T165	1		T225	8		T106	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1360	1			T7	3		T8	1		T9	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T40	1		T63	1		T47	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T51	10		T169	13		T32	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T5	2		T165	1		T92	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T49	14		T43	1		T165	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T76	6		T244	7		T245	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T57	1		T217	13		T179	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T76	10		T226	1		T283	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	392	1			T3	1		T49	1		T36	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	363	1			T12	1		T106	1		T108	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17411	1			T1	19		T2	195		T5	31
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T20	1		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T121	5		T321	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T55	3		T175	7		T323	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T256	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T92	10		T109	14		T169	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T46	2		T203	2		T60	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T40	7		T109	15		T51	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T40	7		T76	12		T187	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T108	6		T186	4		T61	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T51	13		T164	2		T30	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T66	15		T169	6		T205	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T106	25		T171	7		T124	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1161	1			T8	15		T9	17		T10	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T40	9		T63	12		T47	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T169	14		T179	6		T188	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T163	6		T171	13		T258	31
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T49	11		T164	16		T166	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T76	1		T244	12		T245	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T217	12		T179	9		T203	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T76	9		T187	10		T260	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T49	2		T36	4		T163	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	336	1			T106	11		T108	6		T109	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22415

1

T1

19

T2

195

T3

1

auto[1]

auto[0]

4152

1

T8

15

T9

17

T10

13