Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26567

1

T1

19

T2

195

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22669

1

T1

19

T2

195

T4

1

auto[ADC_CTRL_FILTER_COND_OUT]

3898

1

T3

1

T5

2

T12

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20340

1

T1

19

T2

195

T3

1

auto[1]

6227

1

T7

3

T8

16

T9

19

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22492

1

T1

19

T2

195

T3

1

auto[1]

4075

1

T5

1

T48

1

T49

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	261	1			T165	1		T106	12		T27	18
values[0]	57	1			T312	14		T313	15		T314	10
values[1]	760	1			T12	1		T165	1		T225	8
values[2]	719	1			T49	5		T40	8		T109	28
values[3]	592	1			T49	3		T165	1		T55	6
values[4]	589	1			T43	2		T106	15		T169	27
values[5]	909	1			T49	25		T108	14		T109	20
values[6]	624	1			T3	1		T40	8		T92	1
values[7]	667	1			T4	1		T40	10		T66	29
values[8]	663	1			T39	23		T106	12		T109	28
values[9]	3315	1			T5	2		T7	3		T8	16
minimum	17411	1			T1	19		T2	195		T5	31

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	742	1			T165	1		T225	8		T57	1
values[1]	752	1			T49	8		T40	8		T109	28
values[2]	477	1			T43	1		T165	1		T55	6
values[3]	728	1			T43	1		T106	15		T170	1
values[4]	831	1			T49	25		T40	8		T108	14
values[5]	632	1			T3	1		T92	1		T76	44
values[6]	2855	1			T4	1		T7	3		T8	16
values[7]	723	1			T12	1		T92	15		T45	5
values[8]	973	1			T36	17		T92	27		T106	12
values[9]	178	1			T5	2		T165	1		T57	1
minimum	17676	1			T1	19		T2	195		T5	31

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22415

1

T1

19

T2

195

T3

1

auto[1]

4152

1

T8

15

T9

17

T10

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T165	1		T57	1		T51	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T225	1		T46	7		T243	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T49	1		T51	2		T245	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T49	3		T40	8		T109	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T43	1		T165	1		T58	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T55	4		T169	22		T167	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T43	1		T32	2		T203	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T106	15		T170	1		T203	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T40	8		T108	7		T109	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T49	12		T108	7		T51	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T92	1		T76	10		T63	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T3	1		T76	15		T163	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1471	1			T4	1		T7	3		T8	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T66	16		T225	1		T106	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T45	3		T284	1		T170	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T12	1		T92	1		T57	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T36	5		T92	11		T106	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T58	11		T226	1		T47	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T165	1		T298	12		T240	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T5	1		T57	1		T318	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17301	1			T1	19		T2	195		T5	31
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T324	16		T312	1		T290	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T51	3		T166	7		T248	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T225	7		T46	2		T243	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T49	4		T51	1		T245	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T109	12		T51	9		T24	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T58	6		T251	4		T252	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T55	2		T169	23		T167	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T203	16		T300	10		T218	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T203	18		T316	4		T174	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T109	10		T243	1		T217	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T49	13		T51	8		T164	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T76	9		T166	3		T317	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T76	10		T187	17		T60	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1030	1			T50	8		T59	14		T38	30
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T66	13		T225	10		T164	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T45	2		T179	6		T64	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T92	14		T244	6		T187	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T36	12		T92	16		T187	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T58	9		T47	2		T27	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T298	13		T240	13		T325	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T5	1		T318	2		T222	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T48	1		T33	1		T92	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T324	17		T312	13		T290	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T165	1		T106	12		T124	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T27	1		T188	3		T60	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T312	1		T313	8		T314	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T12	1		T165	1		T57	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T225	1		T243	15		T172	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T49	1		T166	8		T245	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T40	8		T109	16		T46	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T165	1		T58	9		T51	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T49	3		T55	4		T169	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T43	2		T32	2		T203	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T106	15		T169	15		T170	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T108	7		T109	10		T243	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T49	12		T108	7		T164	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T40	8		T92	1		T76	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T3	1		T76	13		T51	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T4	1		T40	10		T225	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T66	16		T225	1		T76	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T39	23		T109	15		T284	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T106	12		T164	13		T244	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1633	1			T7	3		T8	16		T9	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T5	1		T12	1		T92	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17269	1			T1	19		T2	195		T5	31
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T124	9		T189	20		T310	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T27	17		T188	6		T60	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T312	13		T313	7		T314	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T51	3		T248	10		T179	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T225	7		T243	12		T252	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T49	4		T166	7		T245	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T109	12		T46	2		T51	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T58	6		T51	1		T62	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T55	2		T169	11		T217	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T203	16		T300	10		T222	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T169	12		T167	14		T203	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T109	10		T243	1		T217	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T49	13		T164	11		T203	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T76	9		T166	3		T15	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T76	5		T51	8		T187	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T51	13		T206	8		T288	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T66	13		T225	10		T76	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T109	13		T64	14		T270	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T164	9		T244	6		T187	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1154	1			T50	8		T59	14		T36	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T5	1		T92	14		T58	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T48	1		T33	1		T92	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T165	1		T57	1		T51	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T225	8		T46	7		T243	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T49	5		T51	2		T245	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T49	1		T40	1		T109	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T43	1		T165	1		T58	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T55	3		T169	25		T167	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T43	1		T32	2		T203	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T106	1		T170	1		T203	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T40	1		T108	1		T109	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T49	14		T108	1		T51	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T92	1		T76	10		T63	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T3	1		T76	12		T163	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1370	1			T4	1		T7	3		T8	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T66	14		T225	11		T106	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T45	5		T284	1		T170	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T12	1		T92	15		T57	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T36	13		T92	17		T106	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T58	10		T226	1		T47	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T165	1		T298	15		T240	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T5	2		T57	1		T318	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17439	1			T1	19		T2	195		T5	31
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T324	18		T312	14		T290	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T51	13		T166	7		T258	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T46	2		T243	14		T260	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T51	1		T245	7		T30	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T49	2		T40	7		T109	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T58	8		T252	1		T249	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T55	3		T169	20		T167	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T203	12		T173	13		T300	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T106	14		T203	14		T316	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T40	7		T108	6		T109	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T49	11		T108	6		T51	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T76	9		T63	12		T166	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T76	13		T163	6		T187	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1131	1			T8	15		T9	17		T10	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T66	15		T106	11		T163	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T171	7		T258	16		T179	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T244	12		T187	7		T259	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T36	4		T92	10		T106	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T58	10		T47	1		T30	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T298	10		T240	5		T200	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T318	1		T319	15		T250	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T326	13		T311	12		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T324	15		T290	5		T327	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T165	1		T106	1		T124	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T27	18		T188	7		T60	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T312	14		T313	11		T314	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T12	1		T165	1		T57	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T225	8		T243	13		T172	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T49	5		T166	8		T245	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T40	1		T109	13		T46	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T165	1		T58	7		T51	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T49	1		T55	3		T169	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T43	2		T32	2		T203	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T106	1		T169	13		T170	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T108	1		T109	11		T243	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T49	14		T108	1		T164	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T40	1		T92	1		T76	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T3	1		T76	6		T51	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T4	1		T40	1		T225	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T66	14		T225	11		T76	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T39	1		T109	14		T284	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T106	1		T164	10		T244	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1517	1			T7	3		T8	1		T9	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T5	2		T12	1		T92	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17411	1			T1	19		T2	195		T5	31
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T106	11		T124	13		T328	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T188	2		T60	3		T267	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T313	4		T314	1		T239	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T51	13		T258	12		T248	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T243	14		T252	11		T175	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T166	7		T245	7		T30	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T40	7		T109	15		T46	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T58	8		T51	1		T62	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T49	2		T55	3		T169	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T203	12		T173	13		T300	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T106	14		T169	14		T167	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T108	6		T109	9		T217	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T49	11		T108	6		T164	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T40	7		T76	9		T166	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T76	12		T51	9		T187	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T40	9		T63	12		T206	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T66	15		T76	1		T163	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T39	22		T109	14		T171	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T106	11		T164	12		T244	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1270	1			T8	15		T9	17		T10	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T58	10		T47	1		T30	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22415

1

T1

19

T2

195

T3

1

auto[1]

auto[0]

4152

1

T8

15

T9

17

T10

13