Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26567

1

T1

19

T2

195

T3

1

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22910

1

T1

19

T2

195

T4

1

auto[ADC_CTRL_FILTER_COND_OUT]

3657

1

T3

1

T5

2

T12

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20693

1

T1

19

T2

195

T3

1

auto[1]

5874

1

T5

2

T7

3

T8

16

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22492

1

T1

19

T2

195

T3

1

auto[1]

4075

1

T5

1

T48

1

T49

17

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	230	1			T92	16		T76	19		T30	7
values[0]	24	1			T253	12		T280	10		T329	1
values[1]	888	1			T3	1		T49	5		T225	8
values[2]	433	1			T165	1		T108	7		T109	28
values[3]	632	1			T40	8		T165	1		T225	11
values[4]	2902	1			T7	3		T8	16		T9	19
values[5]	696	1			T4	1		T40	18		T106	27
values[6]	748	1			T108	7		T47	5		T164	28
values[7]	669	1			T12	1		T36	17		T43	1
values[8]	803	1			T43	1		T225	1		T45	5
values[9]	1131	1			T5	2		T49	25		T66	29
minimum	17411	1			T1	19		T2	195		T5	31

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	669	1			T3	1		T49	5		T225	8
values[1]	581	1			T40	8		T165	1		T109	28
values[2]	599	1			T39	23		T165	1		T225	11
values[3]	2910	1			T4	1		T7	3		T8	16
values[4]	714	1			T40	10		T106	15		T76	18
values[5]	746	1			T36	17		T108	7		T47	5
values[6]	674	1			T12	1		T43	1		T165	1
values[7]	798	1			T5	2		T43	1		T225	1
values[8]	1006	1			T49	25		T66	29		T92	43
values[9]	156	1			T252	6		T292	1		T190	24
minimum	17714	1			T1	19		T2	195		T5	31

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22415

1

T1

19

T2

195

T3

1

auto[1]

4152

1

T8

15

T9

17

T10

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T49	1		T108	7		T109	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T3	1		T225	1		T109	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T109	15		T164	3		T32	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T40	8		T165	1		T51	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T225	1		T57	1		T58	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T39	23		T165	1		T63	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1524	1			T4	1		T7	3		T8	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T12	1		T106	12		T24	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T40	10		T217	10		T172	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T106	15		T76	13		T226	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T36	5		T178	1		T27	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T108	7		T47	3		T259	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T12	1		T51	1		T170	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T43	1		T165	1		T57	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T225	1		T55	4		T46	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T5	1		T43	1		T45	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T49	12		T66	16		T92	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T92	12		T76	10		T58	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T252	2		T190	11		T304	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T292	1		T192	17		T330	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17339	1			T1	19		T2	195		T5	31
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T106	12		T288	1		T171	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T49	4		T109	12		T164	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T225	7		T109	10		T251	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T109	13		T188	14		T207	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T51	3		T243	1		T331	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T225	10		T58	9		T166	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T51	8		T27	2		T187	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1048	1			T50	8		T59	14		T38	30
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T24	7		T183	12		T186	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T217	8		T186	2		T218	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T76	5		T164	11		T244	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T36	12		T27	17		T186	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T47	2		T203	28		T232	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T51	9		T183	11		T179	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T187	17		T188	7		T172	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T55	2		T46	2		T217	21
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T5	1		T45	2		T169	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T49	13		T66	13		T76	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T92	30		T76	9		T58	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T252	4		T190	13		T332	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T192	14		T333	1		T200	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T48	1		T33	1		T92	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T288	4		T171	20		T300	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T92	1		T30	7		T187	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T92	1		T76	10		T204	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T253	1		T280	8		T329	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T49	1		T109	16		T164	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T3	1		T225	1		T106	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T108	7		T109	15		T173	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T165	1		T284	1		T267	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T225	1		T57	1		T164	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T40	8		T165	1		T51	26
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1516	1			T7	3		T8	16		T9	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T12	1		T39	23		T63	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T4	1		T40	18		T206	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T106	27		T76	13		T226	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T178	1		T27	1		T258	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T108	7		T47	3		T164	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T12	1		T36	5		T170	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T43	1		T165	1		T30	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T225	1		T55	4		T46	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T43	1		T45	3		T57	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T49	12		T66	16		T76	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	446	1			T5	1		T92	11		T58	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17269	1			T1	19		T2	195		T5	31
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T187	6		T253	10		T252	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T92	14		T76	9		T204	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T253	11		T280	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T49	4		T109	12		T164	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T225	7		T109	10		T288	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T109	13		T181	16		T133	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T267	3		T252	10		T16	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T225	10		T166	3		T245	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T51	11		T27	2		T243	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1044	1			T50	8		T59	14		T38	30
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T24	7		T187	10		T186	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T206	8		T217	8		T64	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T76	5		T183	12		T297	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T27	17		T186	11		T218	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T47	2		T164	11		T244	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T36	12		T183	11		T179	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T188	7		T172	8		T60	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T55	2		T46	2		T51	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T45	2		T187	17		T172	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T49	13		T66	13		T76	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	345	1			T5	1		T92	16		T58	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T48	1		T33	1		T92	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T49	5		T108	1		T109	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T3	1		T225	8		T109	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T109	14		T164	1		T32	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T40	1		T165	1		T51	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T225	11		T57	1		T58	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T39	1		T165	1		T63	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1392	1			T4	1		T7	3		T8	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T12	1		T106	1		T24	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T40	1		T217	9		T172	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T106	1		T76	6		T226	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T36	13		T178	1		T27	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T108	1		T47	4		T259	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T12	1		T51	10		T170	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T43	1		T165	1		T57	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T225	1		T55	3		T46	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T5	2		T43	1		T45	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T49	14		T66	14		T92	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	345	1			T92	32		T76	10		T58	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T252	5		T190	14		T304	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T292	1		T192	15		T330	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17477	1			T1	19		T2	195		T5	31
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T106	1		T288	5		T171	21
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T108	6		T109	15		T164	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T109	9		T171	7		T184	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T109	14		T164	2		T188	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T40	7		T51	13		T267	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T58	10		T166	4		T245	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T39	22		T63	12		T51	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1180	1			T8	15		T9	17		T10	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T106	11		T24	7		T186	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T40	9		T217	9		T186	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T106	14		T76	12		T164	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T36	4		T258	16		T186	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T108	6		T47	1		T259	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T179	6		T218	7		T208	33
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T30	9		T258	31		T187	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T55	3		T46	2		T217	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T169	12		T261	9		T260	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T49	11		T66	15		T76	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T92	10		T76	9		T58	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T252	1		T190	10		T304	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T192	16		T330	11		T334	23
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T335	13		T336	17		T330	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T106	11		T171	13		T300	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T92	1		T30	1		T187	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T92	15		T76	10		T204	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T253	12		T280	8		T329	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T49	5		T109	13		T164	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T3	1		T225	8		T106	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T108	1		T109	14		T173	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T165	1		T284	1		T267	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T225	11		T57	1		T164	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T40	1		T165	1		T51	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1383	1			T7	3		T8	1		T9	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T12	1		T39	1		T63	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T4	1		T40	2		T206	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T106	2		T76	6		T226	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T178	1		T27	18		T258	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T108	1		T47	4		T164	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T12	1		T36	13		T170	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T43	1		T165	1		T30	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T225	1		T55	3		T46	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T43	1		T45	5		T57	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T49	14		T66	14		T76	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	415	1			T5	2		T92	17		T58	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17411	1			T1	19		T2	195		T5	31
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T30	6		T187	7		T173	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T76	9		T124	24		T330	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T280	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T109	15		T164	12		T169	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T106	11		T109	9		T171	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T108	6		T109	14		T173	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T267	3		T252	11		T250	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T164	2		T166	4		T245	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T40	7		T51	22		T179	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1177	1			T8	15		T9	17		T10	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T39	22		T63	12		T24	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T40	16		T206	8		T217	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T106	25		T76	12		T184	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T258	16		T186	11		T218	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T108	6		T47	1		T164	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T36	4		T179	6		T218	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T30	9		T258	19		T188	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T55	3		T46	2		T217	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T258	12		T187	10		T261	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T49	11		T66	15		T76	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	376	1			T92	10		T58	8		T163	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22415

1

T1

19

T2

195

T3

1

auto[1]

auto[0]

4152

1

T8

15

T9

17

T10

13