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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.73 99.07 96.67 100.00 100.00 98.83 98.33 91.19


Total test records in report: 919
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T805 /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.3690098851 Jun 10 07:17:30 PM PDT 24 Jun 10 07:37:39 PM PDT 24 502805161147 ps
T806 /workspace/coverage/default/39.adc_ctrl_filters_polled.2393726707 Jun 10 07:22:20 PM PDT 24 Jun 10 07:35:40 PM PDT 24 324273094333 ps
T332 /workspace/coverage/default/36.adc_ctrl_clock_gating.2058013419 Jun 10 07:21:50 PM PDT 24 Jun 10 07:27:12 PM PDT 24 516543601011 ps
T807 /workspace/coverage/default/2.adc_ctrl_clock_gating.3692551267 Jun 10 07:16:29 PM PDT 24 Jun 10 07:18:19 PM PDT 24 195094823633 ps
T808 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.3597969131 Jun 10 06:43:57 PM PDT 24 Jun 10 06:43:59 PM PDT 24 403384916 ps
T809 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.3818792404 Jun 10 06:44:52 PM PDT 24 Jun 10 06:44:53 PM PDT 24 348256523 ps
T810 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.230299950 Jun 10 06:44:38 PM PDT 24 Jun 10 06:44:40 PM PDT 24 358179585 ps
T74 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1375424432 Jun 10 06:44:26 PM PDT 24 Jun 10 06:44:34 PM PDT 24 2617742790 ps
T77 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.317564231 Jun 10 06:44:26 PM PDT 24 Jun 10 06:44:34 PM PDT 24 8295223921 ps
T155 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.1334439722 Jun 10 06:44:11 PM PDT 24 Jun 10 06:44:12 PM PDT 24 684956415 ps
T75 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.2717526606 Jun 10 06:43:57 PM PDT 24 Jun 10 06:44:00 PM PDT 24 2381770254 ps
T78 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2854828222 Jun 10 06:44:04 PM PDT 24 Jun 10 06:44:17 PM PDT 24 8288677797 ps
T79 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1436158551 Jun 10 06:44:26 PM PDT 24 Jun 10 06:44:35 PM PDT 24 8528019431 ps
T87 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.932671751 Jun 10 06:43:57 PM PDT 24 Jun 10 06:43:59 PM PDT 24 513358486 ps
T96 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1457737541 Jun 10 06:43:49 PM PDT 24 Jun 10 06:43:53 PM PDT 24 458234641 ps
T98 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.4159882270 Jun 10 06:44:01 PM PDT 24 Jun 10 06:44:03 PM PDT 24 524345681 ps
T811 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.1766662390 Jun 10 06:44:28 PM PDT 24 Jun 10 06:44:29 PM PDT 24 367173304 ps
T99 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.1031058336 Jun 10 06:44:02 PM PDT 24 Jun 10 06:44:04 PM PDT 24 327102836 ps
T812 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.1074909565 Jun 10 06:44:46 PM PDT 24 Jun 10 06:44:48 PM PDT 24 412787911 ps
T71 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3405846913 Jun 10 06:44:12 PM PDT 24 Jun 10 06:44:18 PM PDT 24 4773474963 ps
T813 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1739873068 Jun 10 06:44:25 PM PDT 24 Jun 10 06:44:26 PM PDT 24 330805598 ps
T72 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.489941621 Jun 10 06:43:58 PM PDT 24 Jun 10 06:45:48 PM PDT 24 52533885588 ps
T73 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2880928209 Jun 10 06:44:14 PM PDT 24 Jun 10 06:44:17 PM PDT 24 2281830671 ps
T156 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.3887445786 Jun 10 06:43:56 PM PDT 24 Jun 10 06:43:58 PM PDT 24 353417168 ps
T95 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.250092576 Jun 10 06:44:27 PM PDT 24 Jun 10 06:44:29 PM PDT 24 355945554 ps
T157 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.3594457235 Jun 10 06:44:06 PM PDT 24 Jun 10 06:44:11 PM PDT 24 2152004842 ps
T88 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3836425251 Jun 10 06:44:23 PM PDT 24 Jun 10 06:44:25 PM PDT 24 416610674 ps
T89 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.3227606725 Jun 10 06:44:14 PM PDT 24 Jun 10 06:44:17 PM PDT 24 1071385387 ps
T137 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.4070948567 Jun 10 06:44:03 PM PDT 24 Jun 10 06:44:07 PM PDT 24 1197500828 ps
T82 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.784560079 Jun 10 06:43:57 PM PDT 24 Jun 10 06:44:20 PM PDT 24 8053301495 ps
T161 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.1441275714 Jun 10 06:44:01 PM PDT 24 Jun 10 06:44:03 PM PDT 24 861380909 ps
T814 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.3549574029 Jun 10 06:44:34 PM PDT 24 Jun 10 06:44:36 PM PDT 24 485020264 ps
T815 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3331785545 Jun 10 06:43:55 PM PDT 24 Jun 10 06:43:56 PM PDT 24 304656147 ps
T158 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3949968708 Jun 10 06:44:34 PM PDT 24 Jun 10 06:44:35 PM PDT 24 524319272 ps
T83 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.227510746 Jun 10 06:43:57 PM PDT 24 Jun 10 06:44:01 PM PDT 24 4600005274 ps
T102 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.2770707950 Jun 10 06:44:23 PM PDT 24 Jun 10 06:44:24 PM PDT 24 623377049 ps
T159 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.787768802 Jun 10 06:44:14 PM PDT 24 Jun 10 06:44:16 PM PDT 24 466157650 ps
T90 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2579418853 Jun 10 06:44:26 PM PDT 24 Jun 10 06:44:38 PM PDT 24 4122560122 ps
T138 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3511122153 Jun 10 06:44:28 PM PDT 24 Jun 10 06:44:29 PM PDT 24 323987549 ps
T160 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.3796148606 Jun 10 06:43:55 PM PDT 24 Jun 10 06:44:14 PM PDT 24 4689168643 ps
T816 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.341393727 Jun 10 06:44:27 PM PDT 24 Jun 10 06:44:31 PM PDT 24 4854481571 ps
T91 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2482035055 Jun 10 06:44:26 PM PDT 24 Jun 10 06:44:28 PM PDT 24 524818323 ps
T817 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2092590394 Jun 10 06:44:36 PM PDT 24 Jun 10 06:44:39 PM PDT 24 2676858097 ps
T818 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3185418923 Jun 10 06:44:47 PM PDT 24 Jun 10 06:44:48 PM PDT 24 502281107 ps
T819 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3522716697 Jun 10 06:44:38 PM PDT 24 Jun 10 06:44:39 PM PDT 24 348125448 ps
T139 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.602014195 Jun 10 06:44:10 PM PDT 24 Jun 10 06:44:11 PM PDT 24 605256007 ps
T820 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.751219683 Jun 10 06:44:24 PM PDT 24 Jun 10 06:44:25 PM PDT 24 350311782 ps
T821 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2055984973 Jun 10 06:44:24 PM PDT 24 Jun 10 06:44:25 PM PDT 24 411232766 ps
T140 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3606733815 Jun 10 06:44:03 PM PDT 24 Jun 10 06:44:05 PM PDT 24 564758195 ps
T93 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3253357080 Jun 10 06:44:19 PM PDT 24 Jun 10 06:44:21 PM PDT 24 506078115 ps
T822 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3066020856 Jun 10 06:44:06 PM PDT 24 Jun 10 06:44:14 PM PDT 24 5284990271 ps
T823 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.649031977 Jun 10 06:44:26 PM PDT 24 Jun 10 06:44:28 PM PDT 24 360421962 ps
T824 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.1707553644 Jun 10 06:44:37 PM PDT 24 Jun 10 06:44:38 PM PDT 24 314016148 ps
T825 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.3760843014 Jun 10 06:44:36 PM PDT 24 Jun 10 06:44:37 PM PDT 24 450181809 ps
T826 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.2608949157 Jun 10 06:44:11 PM PDT 24 Jun 10 06:44:13 PM PDT 24 399341857 ps
T827 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2717834125 Jun 10 06:44:51 PM PDT 24 Jun 10 06:44:53 PM PDT 24 472636035 ps
T828 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.968966287 Jun 10 06:43:57 PM PDT 24 Jun 10 06:44:05 PM PDT 24 2762212817 ps
T829 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.3355064779 Jun 10 06:44:39 PM PDT 24 Jun 10 06:44:41 PM PDT 24 485207046 ps
T830 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.257896408 Jun 10 06:44:03 PM PDT 24 Jun 10 06:44:14 PM PDT 24 3022585066 ps
T100 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3511911561 Jun 10 06:44:15 PM PDT 24 Jun 10 06:44:20 PM PDT 24 5053928164 ps
T831 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3423173860 Jun 10 06:43:51 PM PDT 24 Jun 10 06:43:52 PM PDT 24 403711613 ps
T832 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1578543226 Jun 10 06:44:25 PM PDT 24 Jun 10 06:44:26 PM PDT 24 516770985 ps
T833 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.4148125456 Jun 10 06:44:03 PM PDT 24 Jun 10 06:44:05 PM PDT 24 542430436 ps
T834 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3780099684 Jun 10 06:43:55 PM PDT 24 Jun 10 06:43:57 PM PDT 24 416837153 ps
T835 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3865987923 Jun 10 06:44:25 PM PDT 24 Jun 10 06:44:36 PM PDT 24 2869925313 ps
T836 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.4155782275 Jun 10 06:44:03 PM PDT 24 Jun 10 06:44:04 PM PDT 24 501436037 ps
T837 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.635263636 Jun 10 06:44:42 PM PDT 24 Jun 10 06:44:44 PM PDT 24 461818485 ps
T838 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.316874686 Jun 10 06:44:24 PM PDT 24 Jun 10 06:44:25 PM PDT 24 543590877 ps
T839 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1385413064 Jun 10 06:43:55 PM PDT 24 Jun 10 06:44:00 PM PDT 24 1276375110 ps
T101 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3236805094 Jun 10 06:44:37 PM PDT 24 Jun 10 06:44:39 PM PDT 24 415468818 ps
T141 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3711414575 Jun 10 06:44:04 PM PDT 24 Jun 10 06:45:38 PM PDT 24 40687076216 ps
T840 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.4200074440 Jun 10 06:44:27 PM PDT 24 Jun 10 06:44:32 PM PDT 24 4545065357 ps
T841 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3402649843 Jun 10 06:44:48 PM PDT 24 Jun 10 06:44:50 PM PDT 24 518216009 ps
T97 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.2608726374 Jun 10 06:44:27 PM PDT 24 Jun 10 06:44:29 PM PDT 24 382054213 ps
T842 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.1665850656 Jun 10 06:44:38 PM PDT 24 Jun 10 06:44:39 PM PDT 24 321397681 ps
T843 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.1613710415 Jun 10 06:44:01 PM PDT 24 Jun 10 06:44:04 PM PDT 24 476146259 ps
T844 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.178564760 Jun 10 06:44:26 PM PDT 24 Jun 10 06:44:39 PM PDT 24 4692526906 ps
T845 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2289040823 Jun 10 06:43:59 PM PDT 24 Jun 10 06:44:01 PM PDT 24 465624252 ps
T846 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3475147827 Jun 10 06:44:14 PM PDT 24 Jun 10 06:44:16 PM PDT 24 560713529 ps
T847 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.1247257079 Jun 10 06:44:14 PM PDT 24 Jun 10 06:44:15 PM PDT 24 371652327 ps
T848 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.973837134 Jun 10 06:44:44 PM PDT 24 Jun 10 06:44:45 PM PDT 24 509175477 ps
T849 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.1458752885 Jun 10 06:44:14 PM PDT 24 Jun 10 06:44:15 PM PDT 24 478437094 ps
T850 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1266897516 Jun 10 06:44:25 PM PDT 24 Jun 10 06:44:27 PM PDT 24 385967027 ps
T851 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.739452761 Jun 10 06:43:57 PM PDT 24 Jun 10 06:44:00 PM PDT 24 4653707841 ps
T852 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.4273037684 Jun 10 06:44:36 PM PDT 24 Jun 10 06:44:38 PM PDT 24 420469633 ps
T853 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2861458693 Jun 10 06:44:07 PM PDT 24 Jun 10 06:44:08 PM PDT 24 501477451 ps
T854 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.3743693332 Jun 10 06:44:07 PM PDT 24 Jun 10 06:44:09 PM PDT 24 471841295 ps
T855 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1441887926 Jun 10 06:44:09 PM PDT 24 Jun 10 06:44:13 PM PDT 24 581337484 ps
T856 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.2674955638 Jun 10 06:44:49 PM PDT 24 Jun 10 06:44:50 PM PDT 24 435295063 ps
T857 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.163160839 Jun 10 06:44:11 PM PDT 24 Jun 10 06:44:13 PM PDT 24 491967000 ps
T858 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.4108735477 Jun 10 06:44:12 PM PDT 24 Jun 10 06:44:17 PM PDT 24 4527375829 ps
T859 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.271384549 Jun 10 06:44:41 PM PDT 24 Jun 10 06:44:43 PM PDT 24 473564448 ps
T860 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2065516350 Jun 10 06:44:27 PM PDT 24 Jun 10 06:44:35 PM PDT 24 4150340751 ps
T142 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3421143786 Jun 10 06:43:56 PM PDT 24 Jun 10 06:43:58 PM PDT 24 1297688758 ps
T861 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2710091348 Jun 10 06:44:24 PM PDT 24 Jun 10 06:44:26 PM PDT 24 390440093 ps
T862 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.682954599 Jun 10 06:44:41 PM PDT 24 Jun 10 06:44:42 PM PDT 24 471742245 ps
T863 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3062373811 Jun 10 06:44:33 PM PDT 24 Jun 10 06:44:35 PM PDT 24 539673999 ps
T864 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1602196679 Jun 10 06:44:03 PM PDT 24 Jun 10 06:44:06 PM PDT 24 379207702 ps
T143 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3275099933 Jun 10 06:43:52 PM PDT 24 Jun 10 06:43:54 PM PDT 24 717500343 ps
T865 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.4081346700 Jun 10 06:44:52 PM PDT 24 Jun 10 06:44:53 PM PDT 24 516223859 ps
T144 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.886755543 Jun 10 06:43:55 PM PDT 24 Jun 10 06:43:58 PM PDT 24 742161347 ps
T866 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1128411129 Jun 10 06:44:34 PM PDT 24 Jun 10 06:44:38 PM PDT 24 2437541568 ps
T867 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1239376563 Jun 10 06:43:51 PM PDT 24 Jun 10 06:43:52 PM PDT 24 538108330 ps
T145 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.855611690 Jun 10 06:44:04 PM PDT 24 Jun 10 06:44:08 PM PDT 24 1075354359 ps
T146 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2676074220 Jun 10 06:44:24 PM PDT 24 Jun 10 06:44:26 PM PDT 24 475434825 ps
T868 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2154764783 Jun 10 06:43:56 PM PDT 24 Jun 10 06:43:58 PM PDT 24 475359250 ps
T869 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.761131596 Jun 10 06:43:58 PM PDT 24 Jun 10 06:44:00 PM PDT 24 542064251 ps
T870 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1380643669 Jun 10 06:44:17 PM PDT 24 Jun 10 06:44:21 PM PDT 24 4731302275 ps
T871 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.172001732 Jun 10 06:44:42 PM PDT 24 Jun 10 06:44:43 PM PDT 24 345369173 ps
T872 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.6978444 Jun 10 06:44:25 PM PDT 24 Jun 10 06:44:29 PM PDT 24 627741001 ps
T151 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2000971355 Jun 10 06:43:56 PM PDT 24 Jun 10 06:43:58 PM PDT 24 513087574 ps
T873 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.4136140244 Jun 10 06:44:47 PM PDT 24 Jun 10 06:44:48 PM PDT 24 483659225 ps
T874 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.208069127 Jun 10 06:44:12 PM PDT 24 Jun 10 06:44:14 PM PDT 24 366770515 ps
T361 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1792659229 Jun 10 06:44:31 PM PDT 24 Jun 10 06:44:43 PM PDT 24 4217315432 ps
T875 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.84462356 Jun 10 06:44:03 PM PDT 24 Jun 10 06:44:07 PM PDT 24 488568228 ps
T876 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3075111942 Jun 10 06:44:23 PM PDT 24 Jun 10 06:44:28 PM PDT 24 5037422249 ps
T877 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3423407797 Jun 10 06:44:28 PM PDT 24 Jun 10 06:44:31 PM PDT 24 463182278 ps
T878 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.3469261852 Jun 10 06:44:26 PM PDT 24 Jun 10 06:44:30 PM PDT 24 2420879533 ps
T879 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1234548987 Jun 10 06:44:26 PM PDT 24 Jun 10 06:44:28 PM PDT 24 478003329 ps
T880 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.216160052 Jun 10 06:44:00 PM PDT 24 Jun 10 06:44:01 PM PDT 24 333485185 ps
T881 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3728363324 Jun 10 06:44:23 PM PDT 24 Jun 10 06:44:26 PM PDT 24 1820510538 ps
T152 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2981797912 Jun 10 06:44:05 PM PDT 24 Jun 10 06:44:06 PM PDT 24 539609632 ps
T882 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.530807010 Jun 10 06:44:46 PM PDT 24 Jun 10 06:44:47 PM PDT 24 445407553 ps
T359 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3700156769 Jun 10 06:44:28 PM PDT 24 Jun 10 06:44:40 PM PDT 24 8679924597 ps
T153 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.553980559 Jun 10 06:44:13 PM PDT 24 Jun 10 06:44:15 PM PDT 24 395360905 ps
T147 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.3335141371 Jun 10 06:43:58 PM PDT 24 Jun 10 06:44:03 PM PDT 24 2338753370 ps
T883 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.63352513 Jun 10 06:44:41 PM PDT 24 Jun 10 06:44:42 PM PDT 24 322789661 ps
T884 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.288630073 Jun 10 06:44:26 PM PDT 24 Jun 10 06:44:28 PM PDT 24 386081573 ps
T885 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.3684794379 Jun 10 06:44:38 PM PDT 24 Jun 10 06:44:40 PM PDT 24 533057858 ps
T886 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1490731769 Jun 10 06:44:15 PM PDT 24 Jun 10 06:44:18 PM PDT 24 363061017 ps
T154 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.566840648 Jun 10 06:44:26 PM PDT 24 Jun 10 06:44:28 PM PDT 24 584317980 ps
T887 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1019662524 Jun 10 06:44:11 PM PDT 24 Jun 10 06:44:14 PM PDT 24 4871155202 ps
T888 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.2927736291 Jun 10 06:44:25 PM PDT 24 Jun 10 06:44:26 PM PDT 24 350630275 ps
T889 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.704511091 Jun 10 06:44:26 PM PDT 24 Jun 10 06:44:28 PM PDT 24 558857955 ps
T890 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.1682962380 Jun 10 06:44:07 PM PDT 24 Jun 10 06:44:09 PM PDT 24 629610477 ps
T891 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.2133807852 Jun 10 06:44:04 PM PDT 24 Jun 10 06:44:07 PM PDT 24 602399896 ps
T892 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.1494281816 Jun 10 06:44:43 PM PDT 24 Jun 10 06:44:44 PM PDT 24 411951161 ps
T893 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.357463667 Jun 10 06:44:25 PM PDT 24 Jun 10 06:44:27 PM PDT 24 576879075 ps
T894 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2378564461 Jun 10 06:44:41 PM PDT 24 Jun 10 06:44:43 PM PDT 24 455249039 ps
T895 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1910608129 Jun 10 06:44:07 PM PDT 24 Jun 10 06:44:10 PM PDT 24 812792804 ps
T896 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.354199455 Jun 10 06:44:24 PM PDT 24 Jun 10 06:44:26 PM PDT 24 2276139651 ps
T897 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.702877787 Jun 10 06:44:25 PM PDT 24 Jun 10 06:44:26 PM PDT 24 362763024 ps
T898 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.969284248 Jun 10 06:44:07 PM PDT 24 Jun 10 06:44:11 PM PDT 24 3931002116 ps
T360 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3754276009 Jun 10 06:44:04 PM PDT 24 Jun 10 06:44:26 PM PDT 24 7925323363 ps
T899 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.285635288 Jun 10 06:43:54 PM PDT 24 Jun 10 06:43:59 PM PDT 24 8972339697 ps
T900 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.4035768573 Jun 10 06:44:32 PM PDT 24 Jun 10 06:44:33 PM PDT 24 593591658 ps
T901 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.60994661 Jun 10 06:44:01 PM PDT 24 Jun 10 06:44:04 PM PDT 24 398161931 ps
T902 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.1789900633 Jun 10 06:43:59 PM PDT 24 Jun 10 06:44:01 PM PDT 24 693052918 ps
T148 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3557310204 Jun 10 06:43:58 PM PDT 24 Jun 10 06:44:27 PM PDT 24 16762517577 ps
T903 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.4278318635 Jun 10 06:44:47 PM PDT 24 Jun 10 06:44:49 PM PDT 24 391368791 ps
T904 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.1515368210 Jun 10 06:44:28 PM PDT 24 Jun 10 06:44:31 PM PDT 24 382582571 ps
T905 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2963087734 Jun 10 06:44:45 PM PDT 24 Jun 10 06:44:46 PM PDT 24 372428819 ps
T906 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.2838571450 Jun 10 06:44:13 PM PDT 24 Jun 10 06:44:15 PM PDT 24 391100955 ps
T907 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.869004482 Jun 10 06:44:01 PM PDT 24 Jun 10 06:44:04 PM PDT 24 469107752 ps
T908 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.1401465758 Jun 10 06:44:53 PM PDT 24 Jun 10 06:44:54 PM PDT 24 354418717 ps
T909 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.2060850950 Jun 10 06:44:06 PM PDT 24 Jun 10 06:44:08 PM PDT 24 339966944 ps
T149 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.902161725 Jun 10 06:44:00 PM PDT 24 Jun 10 06:44:09 PM PDT 24 20796900146 ps
T910 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3773834294 Jun 10 06:44:16 PM PDT 24 Jun 10 06:44:18 PM PDT 24 410036951 ps
T911 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2876370569 Jun 10 06:44:00 PM PDT 24 Jun 10 06:44:01 PM PDT 24 599384404 ps
T912 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2481476964 Jun 10 06:44:06 PM PDT 24 Jun 10 06:44:07 PM PDT 24 545880841 ps
T103 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2128617765 Jun 10 06:43:55 PM PDT 24 Jun 10 06:44:19 PM PDT 24 8568284984 ps
T913 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2657637272 Jun 10 06:44:01 PM PDT 24 Jun 10 06:44:03 PM PDT 24 3979035061 ps
T914 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.4179024126 Jun 10 06:44:10 PM PDT 24 Jun 10 06:44:17 PM PDT 24 4350471596 ps
T915 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.413260765 Jun 10 06:44:07 PM PDT 24 Jun 10 06:44:12 PM PDT 24 4103207098 ps
T916 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.3248225120 Jun 10 06:44:50 PM PDT 24 Jun 10 06:44:52 PM PDT 24 506859837 ps
T150 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3445029669 Jun 10 06:43:56 PM PDT 24 Jun 10 06:43:58 PM PDT 24 575070806 ps
T917 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.279486776 Jun 10 06:44:33 PM PDT 24 Jun 10 06:44:34 PM PDT 24 448344843 ps
T918 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2175337147 Jun 10 06:44:06 PM PDT 24 Jun 10 06:44:10 PM PDT 24 369437663 ps
T919 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.258743611 Jun 10 06:44:49 PM PDT 24 Jun 10 06:44:50 PM PDT 24 349384904 ps

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.2233126467
Short name T5
Test name
Test status
Simulation time 201550738533 ps
CPU time 126.12 seconds
Started Jun 10 07:22:47 PM PDT 24
Finished Jun 10 07:24:54 PM PDT 24
Peak memory 201828 kb
Host smart-00d0c230-7030-4ba1-95c3-176fa6510890
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233126467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.2233126467
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.779694027
Short name T51
Test name
Test status
Simulation time 1313218505807 ps
CPU time 1630.82 seconds
Started Jun 10 07:18:08 PM PDT 24
Finished Jun 10 07:45:20 PM PDT 24
Peak memory 210368 kb
Host smart-c5d90899-179b-45cc-8ecf-d7deb30e9458
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779694027 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.779694027
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.1182056418
Short name T9
Test name
Test status
Simulation time 410382773920 ps
CPU time 100.56 seconds
Started Jun 10 07:23:06 PM PDT 24
Finished Jun 10 07:24:48 PM PDT 24
Peak memory 201776 kb
Host smart-90ec5d15-5d6f-45ff-81c9-a350ad5ee200
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182056418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.1182056418
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.213523001
Short name T109
Test name
Test status
Simulation time 500982499552 ps
CPU time 302.48 seconds
Started Jun 10 07:21:23 PM PDT 24
Finished Jun 10 07:26:26 PM PDT 24
Peak memory 201864 kb
Host smart-034a12b0-f67b-48fd-8444-ec51d838ed41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213523001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.213523001
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.193829114
Short name T203
Test name
Test status
Simulation time 571564310891 ps
CPU time 1269.84 seconds
Started Jun 10 07:16:18 PM PDT 24
Finished Jun 10 07:37:32 PM PDT 24
Peak memory 201800 kb
Host smart-a67b10bc-c863-47b5-8556-82d2bdbae7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193829114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.193829114
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.4271413973
Short name T15
Test name
Test status
Simulation time 52904787145 ps
CPU time 85.04 seconds
Started Jun 10 07:22:30 PM PDT 24
Finished Jun 10 07:23:56 PM PDT 24
Peak memory 210380 kb
Host smart-0058b502-97e1-4d29-ae59-0792f1df0b31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271413973 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.4271413973
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.84747869
Short name T188
Test name
Test status
Simulation time 518695869722 ps
CPU time 335.13 seconds
Started Jun 10 07:18:07 PM PDT 24
Finished Jun 10 07:23:44 PM PDT 24
Peak memory 201900 kb
Host smart-1e62f0b4-3d9b-4444-9bd6-13f81b63603f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84747869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.84747869
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.2824688321
Short name T2
Test name
Test status
Simulation time 130231009191 ps
CPU time 512.27 seconds
Started Jun 10 07:16:16 PM PDT 24
Finished Jun 10 07:24:50 PM PDT 24
Peak memory 202012 kb
Host smart-91adac1c-a58b-4b63-8dc4-f2a1a0dd63f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824688321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.2824688321
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.3485557259
Short name T106
Test name
Test status
Simulation time 551302494005 ps
CPU time 1417.7 seconds
Started Jun 10 07:17:47 PM PDT 24
Finished Jun 10 07:41:28 PM PDT 24
Peak memory 201672 kb
Host smart-9b218d05-b839-4de5-b751-b6f3f5f87b7a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485557259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.3485557259
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.1595005895
Short name T187
Test name
Test status
Simulation time 545463511957 ps
CPU time 856.29 seconds
Started Jun 10 07:20:52 PM PDT 24
Finished Jun 10 07:35:10 PM PDT 24
Peak memory 201744 kb
Host smart-ddbd61b7-27c4-435f-a978-39a1cb7f9003
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595005895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.1595005895
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2854828222
Short name T78
Test name
Test status
Simulation time 8288677797 ps
CPU time 12.48 seconds
Started Jun 10 06:44:04 PM PDT 24
Finished Jun 10 06:44:17 PM PDT 24
Peak memory 201988 kb
Host smart-4be54b96-fdda-4516-9672-47b1b032c7c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854828222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.2854828222
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.576332841
Short name T186
Test name
Test status
Simulation time 497414525714 ps
CPU time 156.93 seconds
Started Jun 10 07:21:04 PM PDT 24
Finished Jun 10 07:23:42 PM PDT 24
Peak memory 201812 kb
Host smart-18662bab-4dd0-465f-883a-a1e2480298fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576332841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.576332841
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.3489146336
Short name T217
Test name
Test status
Simulation time 563205096907 ps
CPU time 1350 seconds
Started Jun 10 07:17:31 PM PDT 24
Finished Jun 10 07:40:03 PM PDT 24
Peak memory 201800 kb
Host smart-36d9b1a8-0d20-4306-81cb-f6a66ae6b9a4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489146336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.3489146336
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.2705545224
Short name T169
Test name
Test status
Simulation time 519659424850 ps
CPU time 1186.99 seconds
Started Jun 10 07:24:06 PM PDT 24
Finished Jun 10 07:43:57 PM PDT 24
Peak memory 201912 kb
Host smart-e07e1964-4720-4809-876b-a520b33c4bfa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705545224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.2705545224
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.3323241881
Short name T84
Test name
Test status
Simulation time 3877782235 ps
CPU time 3.3 seconds
Started Jun 10 07:16:48 PM PDT 24
Finished Jun 10 07:16:55 PM PDT 24
Peak memory 217308 kb
Host smart-405355e3-126b-443e-93fa-4d1a9c443a54
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323241881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.3323241881
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.3825254324
Short name T49
Test name
Test status
Simulation time 482460817990 ps
CPU time 259.89 seconds
Started Jun 10 07:16:26 PM PDT 24
Finished Jun 10 07:20:50 PM PDT 24
Peak memory 201876 kb
Host smart-f77016c1-2a8d-487c-bbbb-edf2029a5f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825254324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.3825254324
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.2401208110
Short name T252
Test name
Test status
Simulation time 521101589265 ps
CPU time 237.38 seconds
Started Jun 10 07:16:37 PM PDT 24
Finished Jun 10 07:20:38 PM PDT 24
Peak memory 201756 kb
Host smart-42122c88-6ec7-419b-bb82-5926a071f916
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401208110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
2401208110
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3606733815
Short name T140
Test name
Test status
Simulation time 564758195 ps
CPU time 1.37 seconds
Started Jun 10 06:44:03 PM PDT 24
Finished Jun 10 06:44:05 PM PDT 24
Peak memory 201724 kb
Host smart-f339ac37-69f2-46ef-8ce4-dc647a3e89b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606733815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.3606733815
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.1300147142
Short name T76
Test name
Test status
Simulation time 527344257755 ps
CPU time 511.07 seconds
Started Jun 10 07:20:09 PM PDT 24
Finished Jun 10 07:28:41 PM PDT 24
Peak memory 201820 kb
Host smart-78f42ea5-13a4-4590-905d-d354c20fc944
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300147142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.1300147142
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.3227606725
Short name T89
Test name
Test status
Simulation time 1071385387 ps
CPU time 3.31 seconds
Started Jun 10 06:44:14 PM PDT 24
Finished Jun 10 06:44:17 PM PDT 24
Peak memory 201908 kb
Host smart-0f8a4ed4-8c7d-467e-81d4-5a212a121887
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227606725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.3227606725
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.1765490939
Short name T58
Test name
Test status
Simulation time 334335695028 ps
CPU time 785.68 seconds
Started Jun 10 07:22:08 PM PDT 24
Finished Jun 10 07:35:15 PM PDT 24
Peak memory 201840 kb
Host smart-93dc0cd0-c2a8-466a-9af6-5cfd276c84b8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765490939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.1765490939
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.1006839600
Short name T179
Test name
Test status
Simulation time 526387685407 ps
CPU time 310.25 seconds
Started Jun 10 07:17:04 PM PDT 24
Finished Jun 10 07:22:22 PM PDT 24
Peak memory 201884 kb
Host smart-53f2c4e6-55a0-4098-8d7e-72e170265ad9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006839600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.1006839600
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.1389659961
Short name T164
Test name
Test status
Simulation time 493742232894 ps
CPU time 964.22 seconds
Started Jun 10 07:23:16 PM PDT 24
Finished Jun 10 07:39:22 PM PDT 24
Peak memory 201796 kb
Host smart-29efad3e-0c86-41a6-bfeb-f2824faec34e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389659961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.1389659961
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.3175708332
Short name T242
Test name
Test status
Simulation time 624055387923 ps
CPU time 735.92 seconds
Started Jun 10 07:23:06 PM PDT 24
Finished Jun 10 07:35:24 PM PDT 24
Peak memory 201700 kb
Host smart-d428b74c-42ef-45cd-9c1c-fff1a7871d62
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175708332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.3175708332
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.2347176840
Short name T220
Test name
Test status
Simulation time 488764932180 ps
CPU time 197.8 seconds
Started Jun 10 07:23:26 PM PDT 24
Finished Jun 10 07:26:46 PM PDT 24
Peak memory 201764 kb
Host smart-eb11537f-2987-42da-94c6-1e4206fa6a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347176840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.2347176840
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.1769931762
Short name T130
Test name
Test status
Simulation time 438853007488 ps
CPU time 366.52 seconds
Started Jun 10 07:20:01 PM PDT 24
Finished Jun 10 07:26:09 PM PDT 24
Peak memory 211680 kb
Host smart-2e5efd1b-08dd-41c1-bb65-a710a59991a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769931762 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.1769931762
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.1205499887
Short name T312
Test name
Test status
Simulation time 327763188108 ps
CPU time 403.25 seconds
Started Jun 10 07:17:05 PM PDT 24
Finished Jun 10 07:23:55 PM PDT 24
Peak memory 201884 kb
Host smart-f30bcafc-be96-4ce8-a29c-83abe4afabb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205499887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.1205499887
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.3254234490
Short name T121
Test name
Test status
Simulation time 806844890215 ps
CPU time 535.52 seconds
Started Jun 10 07:16:31 PM PDT 24
Finished Jun 10 07:25:32 PM PDT 24
Peak memory 218556 kb
Host smart-2adae9a8-a5bb-489a-bed7-72fc0f487470
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254234490 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.3254234490
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.1420870914
Short name T92
Test name
Test status
Simulation time 494656897878 ps
CPU time 1151.6 seconds
Started Jun 10 07:17:03 PM PDT 24
Finished Jun 10 07:36:22 PM PDT 24
Peak memory 201948 kb
Host smart-e8b54a71-dd6c-48b0-af07-cf4ad33a9dcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420870914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.1420870914
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.2747696201
Short name T13
Test name
Test status
Simulation time 395527871 ps
CPU time 0.77 seconds
Started Jun 10 07:16:19 PM PDT 24
Finished Jun 10 07:16:23 PM PDT 24
Peak memory 201460 kb
Host smart-5cecd137-d929-48f2-ae27-28bf462f2446
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747696201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.2747696201
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.3964826428
Short name T273
Test name
Test status
Simulation time 359755552097 ps
CPU time 134.15 seconds
Started Jun 10 07:18:48 PM PDT 24
Finished Jun 10 07:21:04 PM PDT 24
Peak memory 210372 kb
Host smart-b7c58813-5f44-413e-b4d6-56bb0a72a514
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964826428 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.3964826428
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.3390858617
Short name T294
Test name
Test status
Simulation time 526189897566 ps
CPU time 1270.69 seconds
Started Jun 10 07:22:21 PM PDT 24
Finished Jun 10 07:43:33 PM PDT 24
Peak memory 201776 kb
Host smart-69c3044b-5cff-4aaf-b713-e23b12d3bae1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390858617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.3390858617
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.1044745489
Short name T55
Test name
Test status
Simulation time 291699255067 ps
CPU time 58.08 seconds
Started Jun 10 07:22:29 PM PDT 24
Finished Jun 10 07:23:28 PM PDT 24
Peak memory 201776 kb
Host smart-3e0e6ec5-1c61-4890-8e3a-1c7888fb0f6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044745489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.1044745489
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.3887445786
Short name T156
Test name
Test status
Simulation time 353417168 ps
CPU time 1.52 seconds
Started Jun 10 06:43:56 PM PDT 24
Finished Jun 10 06:43:58 PM PDT 24
Peak memory 201680 kb
Host smart-c4a6bd2e-0ec4-4eb5-af5a-734004c33180
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887445786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.3887445786
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.4169941697
Short name T311
Test name
Test status
Simulation time 533963614801 ps
CPU time 1272.1 seconds
Started Jun 10 07:22:39 PM PDT 24
Finished Jun 10 07:43:52 PM PDT 24
Peak memory 201932 kb
Host smart-e78b0097-ecb5-4de8-a94e-a9cf224907a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169941697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.4169941697
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.1142850859
Short name T240
Test name
Test status
Simulation time 236546323149 ps
CPU time 186.24 seconds
Started Jun 10 07:21:59 PM PDT 24
Finished Jun 10 07:25:07 PM PDT 24
Peak memory 210464 kb
Host smart-e17c35f7-be3d-486e-b0bb-aa081bddf4b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142850859 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.1142850859
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.1190500588
Short name T192
Test name
Test status
Simulation time 332831979298 ps
CPU time 89.01 seconds
Started Jun 10 07:17:21 PM PDT 24
Finished Jun 10 07:18:53 PM PDT 24
Peak memory 201784 kb
Host smart-38e7bea2-222e-4d49-afa1-c22629ff9939
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190500588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.1190500588
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.96296128
Short name T256
Test name
Test status
Simulation time 507597392665 ps
CPU time 301.38 seconds
Started Jun 10 07:16:27 PM PDT 24
Finished Jun 10 07:21:33 PM PDT 24
Peak memory 201796 kb
Host smart-62a4d2ed-e3e9-45c8-9073-47f0f1dca450
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96296128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gating
.96296128
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.342195095
Short name T268
Test name
Test status
Simulation time 330265861676 ps
CPU time 791.23 seconds
Started Jun 10 07:17:14 PM PDT 24
Finished Jun 10 07:30:29 PM PDT 24
Peak memory 201800 kb
Host smart-15c46026-2399-4ebf-b9d1-976e028701ef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342195095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gati
ng.342195095
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.2031266587
Short name T209
Test name
Test status
Simulation time 513097267737 ps
CPU time 33.98 seconds
Started Jun 10 07:18:33 PM PDT 24
Finished Jun 10 07:19:09 PM PDT 24
Peak memory 201908 kb
Host smart-0d753a61-e74c-41f3-967d-eb3c035a9521
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031266587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.2031266587
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1602196679
Short name T864
Test name
Test status
Simulation time 379207702 ps
CPU time 2.35 seconds
Started Jun 10 06:44:03 PM PDT 24
Finished Jun 10 06:44:06 PM PDT 24
Peak memory 201956 kb
Host smart-cf6ca5ad-efc5-4f70-bdc8-1a8a114bf624
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602196679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.1602196679
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.156378516
Short name T286
Test name
Test status
Simulation time 555041565637 ps
CPU time 613.03 seconds
Started Jun 10 07:20:27 PM PDT 24
Finished Jun 10 07:30:41 PM PDT 24
Peak memory 201800 kb
Host smart-c8375579-8b1f-4cea-a09a-722beede2b7a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156378516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_
wakeup.156378516
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.2207093209
Short name T280
Test name
Test status
Simulation time 323262857577 ps
CPU time 134.08 seconds
Started Jun 10 07:19:21 PM PDT 24
Finished Jun 10 07:21:38 PM PDT 24
Peak memory 210896 kb
Host smart-614b5bc8-e5b7-47c7-b4b6-cf675eb35861
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207093209 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.2207093209
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.3717523909
Short name T251
Test name
Test status
Simulation time 327936966199 ps
CPU time 824.68 seconds
Started Jun 10 07:17:39 PM PDT 24
Finished Jun 10 07:31:25 PM PDT 24
Peak memory 201812 kb
Host smart-1ec19c1a-7959-40b5-ad65-f428885f3dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717523909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.3717523909
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.1991872337
Short name T263
Test name
Test status
Simulation time 163675904152 ps
CPU time 116.95 seconds
Started Jun 10 07:20:43 PM PDT 24
Finished Jun 10 07:22:42 PM PDT 24
Peak memory 201784 kb
Host smart-bb40f642-e96b-45c9-a9e0-c5bf373034a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991872337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.1991872337
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.53719185
Short name T239
Test name
Test status
Simulation time 338871528166 ps
CPU time 387.75 seconds
Started Jun 10 07:21:04 PM PDT 24
Finished Jun 10 07:27:33 PM PDT 24
Peak memory 201764 kb
Host smart-2d814849-69cb-44a7-9c2e-7310e32b82cf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53719185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_w
akeup.53719185
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.1359746770
Short name T181
Test name
Test status
Simulation time 333293566442 ps
CPU time 830.87 seconds
Started Jun 10 07:16:30 PM PDT 24
Finished Jun 10 07:30:26 PM PDT 24
Peak memory 201808 kb
Host smart-78114017-077e-466c-9623-e46bec4e1c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359746770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.1359746770
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.2568256845
Short name T344
Test name
Test status
Simulation time 333218439363 ps
CPU time 297.46 seconds
Started Jun 10 07:16:39 PM PDT 24
Finished Jun 10 07:21:42 PM PDT 24
Peak memory 201876 kb
Host smart-d45b4623-3735-4c24-9e56-4c671ef7bb61
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568256845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.2568256845
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.2700075778
Short name T211
Test name
Test status
Simulation time 488139725204 ps
CPU time 291.53 seconds
Started Jun 10 07:16:34 PM PDT 24
Finished Jun 10 07:21:30 PM PDT 24
Peak memory 201788 kb
Host smart-57ecb542-2815-4bce-be93-479b4eeea135
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700075778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.2700075778
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.3613944610
Short name T19
Test name
Test status
Simulation time 57476602696 ps
CPU time 126.51 seconds
Started Jun 10 07:17:28 PM PDT 24
Finished Jun 10 07:19:36 PM PDT 24
Peak memory 218276 kb
Host smart-26178b7b-f001-4e73-8896-76e1c5096336
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613944610 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.3613944610
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.1963614450
Short name T258
Test name
Test status
Simulation time 564174337966 ps
CPU time 1348.18 seconds
Started Jun 10 07:16:26 PM PDT 24
Finished Jun 10 07:39:00 PM PDT 24
Peak memory 201792 kb
Host smart-ccdd0c3a-dcec-4782-ae80-6ffe0ce28c61
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963614450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.1963614450
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.4113051817
Short name T225
Test name
Test status
Simulation time 494320487110 ps
CPU time 1109.11 seconds
Started Jun 10 07:18:19 PM PDT 24
Finished Jun 10 07:36:52 PM PDT 24
Peak memory 201864 kb
Host smart-dfaea88d-6732-42d5-9e74-163e1d991fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113051817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.4113051817
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.1756551722
Short name T264
Test name
Test status
Simulation time 742955038134 ps
CPU time 423.14 seconds
Started Jun 10 07:21:23 PM PDT 24
Finished Jun 10 07:28:27 PM PDT 24
Peak memory 201888 kb
Host smart-bee939af-c12b-41ba-84f4-6af12bfecef7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756551722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.1756551722
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.2388683654
Short name T300
Test name
Test status
Simulation time 166053280233 ps
CPU time 386.47 seconds
Started Jun 10 07:22:28 PM PDT 24
Finished Jun 10 07:28:56 PM PDT 24
Peak memory 201796 kb
Host smart-10ebb188-6d3e-40d1-844a-e5845319db43
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388683654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.2388683654
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.37322596
Short name T20
Test name
Test status
Simulation time 119386311352 ps
CPU time 252.93 seconds
Started Jun 10 07:24:18 PM PDT 24
Finished Jun 10 07:28:33 PM PDT 24
Peak memory 210152 kb
Host smart-eb99ca38-6b27-402f-947f-76c0adb25bb8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37322596 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.37322596
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.3856534682
Short name T227
Test name
Test status
Simulation time 117538823134 ps
CPU time 617.72 seconds
Started Jun 10 07:16:31 PM PDT 24
Finished Jun 10 07:26:54 PM PDT 24
Peak memory 202104 kb
Host smart-f4baae40-a7bd-4135-9e29-f0fc1862231c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856534682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.3856534682
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.3791404224
Short name T302
Test name
Test status
Simulation time 167333144774 ps
CPU time 190.25 seconds
Started Jun 10 07:16:36 PM PDT 24
Finished Jun 10 07:19:51 PM PDT 24
Peak memory 201824 kb
Host smart-232b7d0c-588b-4367-81df-bae29d84d73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791404224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.3791404224
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3511911561
Short name T100
Test name
Test status
Simulation time 5053928164 ps
CPU time 4.4 seconds
Started Jun 10 06:44:15 PM PDT 24
Finished Jun 10 06:44:20 PM PDT 24
Peak memory 202004 kb
Host smart-c7ffed0f-60de-49a6-97ce-b4069efbd89d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511911561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.3511911561
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.2048834840
Short name T40
Test name
Test status
Simulation time 555352430379 ps
CPU time 169.99 seconds
Started Jun 10 07:16:16 PM PDT 24
Finished Jun 10 07:19:08 PM PDT 24
Peak memory 201908 kb
Host smart-36c7ccea-d7aa-4408-bc4d-c3dd48534d90
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048834840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.2048834840
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.1706839807
Short name T165
Test name
Test status
Simulation time 490855282322 ps
CPU time 989.38 seconds
Started Jun 10 07:16:32 PM PDT 24
Finished Jun 10 07:33:06 PM PDT 24
Peak memory 201788 kb
Host smart-1670d529-6565-41fc-8f8c-6e2d8931e6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706839807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.1706839807
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.1932549215
Short name T238
Test name
Test status
Simulation time 341205608831 ps
CPU time 421.97 seconds
Started Jun 10 07:16:37 PM PDT 24
Finished Jun 10 07:23:43 PM PDT 24
Peak memory 201780 kb
Host smart-9cbad735-1af8-459e-9eea-dd17c698e3ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932549215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.1932549215
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.4235964183
Short name T343
Test name
Test status
Simulation time 629778876849 ps
CPU time 239.46 seconds
Started Jun 10 07:16:52 PM PDT 24
Finished Jun 10 07:20:57 PM PDT 24
Peak memory 201800 kb
Host smart-80684ffe-57cd-42e7-9171-9a6f4793b3df
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235964183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.4235964183
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.527207879
Short name T281
Test name
Test status
Simulation time 166121619035 ps
CPU time 111.74 seconds
Started Jun 10 07:17:15 PM PDT 24
Finished Jun 10 07:19:11 PM PDT 24
Peak memory 201784 kb
Host smart-4cb2d32e-f3b4-459b-b037-301a61ebab43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527207879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.527207879
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.2775756566
Short name T266
Test name
Test status
Simulation time 66569904933 ps
CPU time 186.52 seconds
Started Jun 10 07:20:55 PM PDT 24
Finished Jun 10 07:24:03 PM PDT 24
Peak memory 210408 kb
Host smart-eb4961cb-22b0-482a-82b5-04325c860729
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775756566 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.2775756566
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.605453104
Short name T260
Test name
Test status
Simulation time 546988477649 ps
CPU time 1337.85 seconds
Started Jun 10 07:22:48 PM PDT 24
Finished Jun 10 07:45:07 PM PDT 24
Peak memory 201808 kb
Host smart-b9e39b2c-43da-4e9b-aac6-4e91f483ad08
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605453104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_
wakeup.605453104
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.483884248
Short name T349
Test name
Test status
Simulation time 524834369187 ps
CPU time 1160.2 seconds
Started Jun 10 07:24:31 PM PDT 24
Finished Jun 10 07:43:56 PM PDT 24
Peak memory 201824 kb
Host smart-61982480-2f24-40a6-a01d-0d857b90b008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483884248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.483884248
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.857689548
Short name T21
Test name
Test status
Simulation time 65381482176 ps
CPU time 180.67 seconds
Started Jun 10 07:16:17 PM PDT 24
Finished Jun 10 07:19:20 PM PDT 24
Peak memory 218604 kb
Host smart-143a7ca7-5745-47ab-8743-87fd2c583fac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857689548 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.857689548
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.3777605161
Short name T228
Test name
Test status
Simulation time 74519261423 ps
CPU time 255.43 seconds
Started Jun 10 07:16:40 PM PDT 24
Finished Jun 10 07:21:01 PM PDT 24
Peak memory 202096 kb
Host smart-777164f8-ca15-4c7a-bcca-48fe5f840c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777605161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.3777605161
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.62330879
Short name T81
Test name
Test status
Simulation time 196203543239 ps
CPU time 178.22 seconds
Started Jun 10 07:17:05 PM PDT 24
Finished Jun 10 07:20:10 PM PDT 24
Peak memory 210416 kb
Host smart-092495a9-998d-4506-b139-3603f7b83c92
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62330879 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.62330879
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.3127993936
Short name T231
Test name
Test status
Simulation time 86609255580 ps
CPU time 480.98 seconds
Started Jun 10 07:17:55 PM PDT 24
Finished Jun 10 07:26:00 PM PDT 24
Peak memory 202120 kb
Host smart-0bc4bff8-4b1b-4e0c-95fe-9c4f39c6987d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127993936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.3127993936
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.3847660902
Short name T175
Test name
Test status
Simulation time 516839177674 ps
CPU time 236.01 seconds
Started Jun 10 07:19:21 PM PDT 24
Finished Jun 10 07:23:20 PM PDT 24
Peak memory 201884 kb
Host smart-52d3fcc5-7d20-4a8c-a147-f17b46b11613
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847660902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.3847660902
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.431235196
Short name T282
Test name
Test status
Simulation time 501377765227 ps
CPU time 1120.25 seconds
Started Jun 10 07:22:50 PM PDT 24
Finished Jun 10 07:41:32 PM PDT 24
Peak memory 201896 kb
Host smart-3cc296e8-6f44-45ea-946d-4bbc48c4a3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431235196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.431235196
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3700156769
Short name T359
Test name
Test status
Simulation time 8679924597 ps
CPU time 11.69 seconds
Started Jun 10 06:44:28 PM PDT 24
Finished Jun 10 06:44:40 PM PDT 24
Peak memory 201960 kb
Host smart-f8478b59-b436-42ec-ab3d-90f6853ccb9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700156769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.3700156769
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.1343459998
Short name T743
Test name
Test status
Simulation time 176211648449 ps
CPU time 230.03 seconds
Started Jun 10 07:17:22 PM PDT 24
Finished Jun 10 07:21:14 PM PDT 24
Peak memory 210440 kb
Host smart-c0c6f925-16c5-4c50-97c1-69d2674d8047
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343459998 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.1343459998
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.1380096893
Short name T306
Test name
Test status
Simulation time 66150368514 ps
CPU time 69.28 seconds
Started Jun 10 07:20:38 PM PDT 24
Finished Jun 10 07:21:49 PM PDT 24
Peak memory 210444 kb
Host smart-bea908ed-38c6-4bc7-ba4e-58ee1d31767f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380096893 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.1380096893
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.606774409
Short name T250
Test name
Test status
Simulation time 336515077965 ps
CPU time 79.6 seconds
Started Jun 10 07:20:36 PM PDT 24
Finished Jun 10 07:21:58 PM PDT 24
Peak memory 201808 kb
Host smart-0e4c061e-53c9-4e08-a5a4-d4b8dac7ddc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606774409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.606774409
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.3891152682
Short name T292
Test name
Test status
Simulation time 323229990027 ps
CPU time 744.72 seconds
Started Jun 10 07:16:27 PM PDT 24
Finished Jun 10 07:28:57 PM PDT 24
Peak memory 201736 kb
Host smart-0212057d-2a0c-4762-b259-ab794047e984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891152682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.3891152682
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.1850043949
Short name T351
Test name
Test status
Simulation time 370101993824 ps
CPU time 873.72 seconds
Started Jun 10 07:21:59 PM PDT 24
Finished Jun 10 07:36:34 PM PDT 24
Peak memory 201820 kb
Host smart-26e50b3f-a65a-4b91-8873-3ee09c5da091
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850043949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.1850043949
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.2572440245
Short name T235
Test name
Test status
Simulation time 413051285711 ps
CPU time 1254.78 seconds
Started Jun 10 07:23:29 PM PDT 24
Finished Jun 10 07:44:26 PM PDT 24
Peak memory 218540 kb
Host smart-e0d6b1c8-0ee0-4ea1-bf72-bb00161343a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572440245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.2572440245
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.1264692833
Short name T131
Test name
Test status
Simulation time 368155992225 ps
CPU time 796.28 seconds
Started Jun 10 07:23:56 PM PDT 24
Finished Jun 10 07:37:16 PM PDT 24
Peak memory 201804 kb
Host smart-c508a074-8fcb-4a30-a8b5-963bea02e943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264692833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.1264692833
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.2299520380
Short name T345
Test name
Test status
Simulation time 420532402266 ps
CPU time 1028.33 seconds
Started Jun 10 07:23:57 PM PDT 24
Finished Jun 10 07:41:10 PM PDT 24
Peak memory 201764 kb
Host smart-a8c5fbe7-0d4e-4619-bead-bd98f68c33cc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299520380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.2299520380
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3445029669
Short name T150
Test name
Test status
Simulation time 575070806 ps
CPU time 1.86 seconds
Started Jun 10 06:43:56 PM PDT 24
Finished Jun 10 06:43:58 PM PDT 24
Peak memory 201928 kb
Host smart-0a4348a5-9d0b-49b8-b382-1ecee0ff8936
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445029669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.3445029669
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.3335141371
Short name T147
Test name
Test status
Simulation time 2338753370 ps
CPU time 4.37 seconds
Started Jun 10 06:43:58 PM PDT 24
Finished Jun 10 06:44:03 PM PDT 24
Peak memory 201968 kb
Host smart-1ec269f5-abb4-4f2b-a88e-0474a7cbaac6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335141371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.3335141371
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3275099933
Short name T143
Test name
Test status
Simulation time 717500343 ps
CPU time 1.58 seconds
Started Jun 10 06:43:52 PM PDT 24
Finished Jun 10 06:43:54 PM PDT 24
Peak memory 201720 kb
Host smart-88b02d98-aea4-4606-9f1a-d0b7f7b40ded
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275099933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.3275099933
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3423173860
Short name T831
Test name
Test status
Simulation time 403711613 ps
CPU time 1.02 seconds
Started Jun 10 06:43:51 PM PDT 24
Finished Jun 10 06:43:52 PM PDT 24
Peak memory 201764 kb
Host smart-26740361-3348-4242-b8d8-6d9ca61dcc7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423173860 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.3423173860
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2000971355
Short name T151
Test name
Test status
Simulation time 513087574 ps
CPU time 2.01 seconds
Started Jun 10 06:43:56 PM PDT 24
Finished Jun 10 06:43:58 PM PDT 24
Peak memory 201708 kb
Host smart-68a4e5be-881a-4002-9893-7c1c16422810
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000971355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.2000971355
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.3597969131
Short name T808
Test name
Test status
Simulation time 403384916 ps
CPU time 1.6 seconds
Started Jun 10 06:43:57 PM PDT 24
Finished Jun 10 06:43:59 PM PDT 24
Peak memory 201712 kb
Host smart-470eeb0b-285f-4af0-bf2d-9dc10fa2d4f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597969131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.3597969131
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.3796148606
Short name T160
Test name
Test status
Simulation time 4689168643 ps
CPU time 18.73 seconds
Started Jun 10 06:43:55 PM PDT 24
Finished Jun 10 06:44:14 PM PDT 24
Peak memory 201968 kb
Host smart-65f24b6a-df2b-4bdc-8f87-17c603685c23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796148606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.3796148606
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.84462356
Short name T875
Test name
Test status
Simulation time 488568228 ps
CPU time 3.5 seconds
Started Jun 10 06:44:03 PM PDT 24
Finished Jun 10 06:44:07 PM PDT 24
Peak memory 210992 kb
Host smart-a415c739-2985-4526-8429-9da533f42204
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84462356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.84462356
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.739452761
Short name T851
Test name
Test status
Simulation time 4653707841 ps
CPU time 3.02 seconds
Started Jun 10 06:43:57 PM PDT 24
Finished Jun 10 06:44:00 PM PDT 24
Peak memory 201972 kb
Host smart-b8f95cee-58b3-46b2-8fa6-87be4f1a2ccb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739452761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_int
g_err.739452761
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.886755543
Short name T144
Test name
Test status
Simulation time 742161347 ps
CPU time 3.04 seconds
Started Jun 10 06:43:55 PM PDT 24
Finished Jun 10 06:43:58 PM PDT 24
Peak memory 201880 kb
Host smart-fce2be57-ac7e-4353-a4cc-4634d97e9869
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886755543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alias
ing.886755543
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.489941621
Short name T72
Test name
Test status
Simulation time 52533885588 ps
CPU time 109.24 seconds
Started Jun 10 06:43:58 PM PDT 24
Finished Jun 10 06:45:48 PM PDT 24
Peak memory 202008 kb
Host smart-2a1c46a0-fb91-4ef9-b1c3-90a5b8d7075b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489941621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_b
ash.489941621
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.4070948567
Short name T137
Test name
Test status
Simulation time 1197500828 ps
CPU time 3.41 seconds
Started Jun 10 06:44:03 PM PDT 24
Finished Jun 10 06:44:07 PM PDT 24
Peak memory 201608 kb
Host smart-6542d395-84ae-45fe-aebc-11b8a1e0d18b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070948567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.4070948567
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.932671751
Short name T87
Test name
Test status
Simulation time 513358486 ps
CPU time 1.33 seconds
Started Jun 10 06:43:57 PM PDT 24
Finished Jun 10 06:43:59 PM PDT 24
Peak memory 212228 kb
Host smart-91e1473f-b902-4429-adc9-7cfe493348e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932671751 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.932671751
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1239376563
Short name T867
Test name
Test status
Simulation time 538108330 ps
CPU time 1.03 seconds
Started Jun 10 06:43:51 PM PDT 24
Finished Jun 10 06:43:52 PM PDT 24
Peak memory 201648 kb
Host smart-3ce9ba25-35ef-4cf3-8a1d-a94bb5885e03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239376563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.1239376563
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.2717526606
Short name T75
Test name
Test status
Simulation time 2381770254 ps
CPU time 2.53 seconds
Started Jun 10 06:43:57 PM PDT 24
Finished Jun 10 06:44:00 PM PDT 24
Peak memory 201760 kb
Host smart-efb885a7-0479-4648-909e-773a3af42f34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717526606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.2717526606
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1457737541
Short name T96
Test name
Test status
Simulation time 458234641 ps
CPU time 2.62 seconds
Started Jun 10 06:43:49 PM PDT 24
Finished Jun 10 06:43:53 PM PDT 24
Peak memory 201976 kb
Host smart-d7e45606-8d84-4ccd-8f45-7cfd4eef651d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457737541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.1457737541
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2128617765
Short name T103
Test name
Test status
Simulation time 8568284984 ps
CPU time 23.84 seconds
Started Jun 10 06:43:55 PM PDT 24
Finished Jun 10 06:44:19 PM PDT 24
Peak memory 202012 kb
Host smart-e18ecd62-265f-4cf8-bef8-4845cf1c72a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128617765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.2128617765
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3773834294
Short name T910
Test name
Test status
Simulation time 410036951 ps
CPU time 1.78 seconds
Started Jun 10 06:44:16 PM PDT 24
Finished Jun 10 06:44:18 PM PDT 24
Peak memory 201776 kb
Host smart-ba5c0f29-b9a5-40ee-8c9b-0f40ebf15065
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773834294 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.3773834294
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.553980559
Short name T153
Test name
Test status
Simulation time 395360905 ps
CPU time 1.08 seconds
Started Jun 10 06:44:13 PM PDT 24
Finished Jun 10 06:44:15 PM PDT 24
Peak memory 201648 kb
Host smart-a08084d6-4f93-411a-88e9-a5a5aa40a16a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553980559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.553980559
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.1247257079
Short name T847
Test name
Test status
Simulation time 371652327 ps
CPU time 1.03 seconds
Started Jun 10 06:44:14 PM PDT 24
Finished Jun 10 06:44:15 PM PDT 24
Peak memory 201704 kb
Host smart-d3736187-ac33-43c5-94dd-5f02061c9773
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247257079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.1247257079
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.4108735477
Short name T858
Test name
Test status
Simulation time 4527375829 ps
CPU time 4.47 seconds
Started Jun 10 06:44:12 PM PDT 24
Finished Jun 10 06:44:17 PM PDT 24
Peak memory 202084 kb
Host smart-9e12999a-301f-4a22-9743-ac3d42ff9ceb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108735477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.4108735477
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3253357080
Short name T93
Test name
Test status
Simulation time 506078115 ps
CPU time 1.49 seconds
Started Jun 10 06:44:19 PM PDT 24
Finished Jun 10 06:44:21 PM PDT 24
Peak memory 201612 kb
Host smart-9884df2e-8411-458d-98f2-9dea59345842
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253357080 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.3253357080
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.208069127
Short name T874
Test name
Test status
Simulation time 366770515 ps
CPU time 0.88 seconds
Started Jun 10 06:44:12 PM PDT 24
Finished Jun 10 06:44:14 PM PDT 24
Peak memory 201628 kb
Host smart-fdfcf8f7-1da7-44b4-95af-6c6632a7a116
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208069127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.208069127
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.2838571450
Short name T906
Test name
Test status
Simulation time 391100955 ps
CPU time 0.77 seconds
Started Jun 10 06:44:13 PM PDT 24
Finished Jun 10 06:44:15 PM PDT 24
Peak memory 201532 kb
Host smart-2690d48c-c3a3-4179-8e82-4c2b555baaf0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838571450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.2838571450
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.354199455
Short name T896
Test name
Test status
Simulation time 2276139651 ps
CPU time 1.65 seconds
Started Jun 10 06:44:24 PM PDT 24
Finished Jun 10 06:44:26 PM PDT 24
Peak memory 201800 kb
Host smart-e7a24018-868c-4570-828f-dd9c3af5a4fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354199455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_c
trl_same_csr_outstanding.354199455
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1490731769
Short name T886
Test name
Test status
Simulation time 363061017 ps
CPU time 2.35 seconds
Started Jun 10 06:44:15 PM PDT 24
Finished Jun 10 06:44:18 PM PDT 24
Peak memory 202000 kb
Host smart-09a5e8fe-b533-4584-826d-da0f4031884c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490731769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.1490731769
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1380643669
Short name T870
Test name
Test status
Simulation time 4731302275 ps
CPU time 4.05 seconds
Started Jun 10 06:44:17 PM PDT 24
Finished Jun 10 06:44:21 PM PDT 24
Peak memory 201940 kb
Host smart-ffb56817-c301-49ab-be79-9777f0a9f955
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380643669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.1380643669
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.357463667
Short name T893
Test name
Test status
Simulation time 576879075 ps
CPU time 1.35 seconds
Started Jun 10 06:44:25 PM PDT 24
Finished Jun 10 06:44:27 PM PDT 24
Peak memory 201768 kb
Host smart-2d1a8fb7-f7f9-4532-8b0e-a2b35f0c7cb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357463667 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.357463667
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.751219683
Short name T820
Test name
Test status
Simulation time 350311782 ps
CPU time 1.13 seconds
Started Jun 10 06:44:24 PM PDT 24
Finished Jun 10 06:44:25 PM PDT 24
Peak memory 201712 kb
Host smart-d6f077d8-ca57-4b45-91ef-2186f940ae40
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751219683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.751219683
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.702877787
Short name T897
Test name
Test status
Simulation time 362763024 ps
CPU time 1.49 seconds
Started Jun 10 06:44:25 PM PDT 24
Finished Jun 10 06:44:26 PM PDT 24
Peak memory 201700 kb
Host smart-6a82f32d-c9ce-40aa-a313-98a946a1ab00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702877787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.702877787
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3865987923
Short name T835
Test name
Test status
Simulation time 2869925313 ps
CPU time 10.33 seconds
Started Jun 10 06:44:25 PM PDT 24
Finished Jun 10 06:44:36 PM PDT 24
Peak memory 202000 kb
Host smart-93cfb801-5001-4d0e-9400-d166412e1c92
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865987923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.3865987923
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.250092576
Short name T95
Test name
Test status
Simulation time 355945554 ps
CPU time 1.63 seconds
Started Jun 10 06:44:27 PM PDT 24
Finished Jun 10 06:44:29 PM PDT 24
Peak memory 201920 kb
Host smart-d8315655-ea55-483f-8fac-e539a9aef082
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250092576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.250092576
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3075111942
Short name T876
Test name
Test status
Simulation time 5037422249 ps
CPU time 4.69 seconds
Started Jun 10 06:44:23 PM PDT 24
Finished Jun 10 06:44:28 PM PDT 24
Peak memory 201892 kb
Host smart-b809c32b-1d87-47bf-870f-ae7dbd1a3587
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075111942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.3075111942
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2710091348
Short name T861
Test name
Test status
Simulation time 390440093 ps
CPU time 1.19 seconds
Started Jun 10 06:44:24 PM PDT 24
Finished Jun 10 06:44:26 PM PDT 24
Peak memory 201744 kb
Host smart-a91d7b69-f074-4771-85e6-bc1c98e1b020
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710091348 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.2710091348
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1578543226
Short name T832
Test name
Test status
Simulation time 516770985 ps
CPU time 1.04 seconds
Started Jun 10 06:44:25 PM PDT 24
Finished Jun 10 06:44:26 PM PDT 24
Peak memory 201740 kb
Host smart-444e8909-b41a-4e3f-9f88-e045aa8678e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578543226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.1578543226
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1739873068
Short name T813
Test name
Test status
Simulation time 330805598 ps
CPU time 0.84 seconds
Started Jun 10 06:44:25 PM PDT 24
Finished Jun 10 06:44:26 PM PDT 24
Peak memory 201720 kb
Host smart-b6641677-7576-42c2-b644-7286989569eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739873068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.1739873068
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2065516350
Short name T860
Test name
Test status
Simulation time 4150340751 ps
CPU time 8.2 seconds
Started Jun 10 06:44:27 PM PDT 24
Finished Jun 10 06:44:35 PM PDT 24
Peak memory 201996 kb
Host smart-df0818c9-81e0-43fe-bf7c-598bd43a3b50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065516350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.2065516350
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.6978444
Short name T872
Test name
Test status
Simulation time 627741001 ps
CPU time 3.94 seconds
Started Jun 10 06:44:25 PM PDT 24
Finished Jun 10 06:44:29 PM PDT 24
Peak memory 210212 kb
Host smart-345df746-1d33-4084-ad40-10a1b88d4d62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6978444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.6978444
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1436158551
Short name T79
Test name
Test status
Simulation time 8528019431 ps
CPU time 8.83 seconds
Started Jun 10 06:44:26 PM PDT 24
Finished Jun 10 06:44:35 PM PDT 24
Peak memory 201996 kb
Host smart-e5f0cb64-7ae3-43a3-8909-6f1fc4450559
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436158551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.1436158551
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.2770707950
Short name T102
Test name
Test status
Simulation time 623377049 ps
CPU time 1.3 seconds
Started Jun 10 06:44:23 PM PDT 24
Finished Jun 10 06:44:24 PM PDT 24
Peak memory 201784 kb
Host smart-2902cb57-1829-4f44-8fb8-87ef51a58e3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770707950 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.2770707950
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2676074220
Short name T146
Test name
Test status
Simulation time 475434825 ps
CPU time 1.39 seconds
Started Jun 10 06:44:24 PM PDT 24
Finished Jun 10 06:44:26 PM PDT 24
Peak memory 201684 kb
Host smart-686db634-e5f6-4b94-a129-e91919358c3f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676074220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.2676074220
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.2927736291
Short name T888
Test name
Test status
Simulation time 350630275 ps
CPU time 0.83 seconds
Started Jun 10 06:44:25 PM PDT 24
Finished Jun 10 06:44:26 PM PDT 24
Peak memory 201696 kb
Host smart-e6f33c23-70c1-47d5-8e1e-1cf739d2cff4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927736291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.2927736291
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3728363324
Short name T881
Test name
Test status
Simulation time 1820510538 ps
CPU time 2.37 seconds
Started Jun 10 06:44:23 PM PDT 24
Finished Jun 10 06:44:26 PM PDT 24
Peak memory 201696 kb
Host smart-8c65a4e3-071b-4210-8f30-ac0b6977b92f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728363324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.3728363324
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.288630073
Short name T884
Test name
Test status
Simulation time 386081573 ps
CPU time 1.73 seconds
Started Jun 10 06:44:26 PM PDT 24
Finished Jun 10 06:44:28 PM PDT 24
Peak memory 202008 kb
Host smart-0869ab4a-4340-46e9-8142-ffa4dbb0e80e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288630073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.288630073
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2579418853
Short name T90
Test name
Test status
Simulation time 4122560122 ps
CPU time 10.99 seconds
Started Jun 10 06:44:26 PM PDT 24
Finished Jun 10 06:44:38 PM PDT 24
Peak memory 201920 kb
Host smart-63dfa067-e397-496d-80ff-efd9768c63db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579418853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.2579418853
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1234548987
Short name T879
Test name
Test status
Simulation time 478003329 ps
CPU time 1.31 seconds
Started Jun 10 06:44:26 PM PDT 24
Finished Jun 10 06:44:28 PM PDT 24
Peak memory 209980 kb
Host smart-e9438eac-3c0e-44f8-bfab-5a170f335ffb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234548987 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.1234548987
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2055984973
Short name T821
Test name
Test status
Simulation time 411232766 ps
CPU time 0.97 seconds
Started Jun 10 06:44:24 PM PDT 24
Finished Jun 10 06:44:25 PM PDT 24
Peak memory 201672 kb
Host smart-189d75c6-eb02-4793-8fce-c18bd63ac1b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055984973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.2055984973
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.316874686
Short name T838
Test name
Test status
Simulation time 543590877 ps
CPU time 0.86 seconds
Started Jun 10 06:44:24 PM PDT 24
Finished Jun 10 06:44:25 PM PDT 24
Peak memory 201628 kb
Host smart-b66cab2d-8967-4238-93df-836faf718a2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316874686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.316874686
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1375424432
Short name T74
Test name
Test status
Simulation time 2617742790 ps
CPU time 7.16 seconds
Started Jun 10 06:44:26 PM PDT 24
Finished Jun 10 06:44:34 PM PDT 24
Peak memory 201796 kb
Host smart-7fbefcd1-99ea-46de-867b-ec8df4eefda7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375424432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.1375424432
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3836425251
Short name T88
Test name
Test status
Simulation time 416610674 ps
CPU time 1.62 seconds
Started Jun 10 06:44:23 PM PDT 24
Finished Jun 10 06:44:25 PM PDT 24
Peak memory 201960 kb
Host smart-0b1d5c52-fb37-416f-8802-265cc03196bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836425251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.3836425251
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.317564231
Short name T77
Test name
Test status
Simulation time 8295223921 ps
CPU time 7 seconds
Started Jun 10 06:44:26 PM PDT 24
Finished Jun 10 06:44:34 PM PDT 24
Peak memory 202016 kb
Host smart-841b0323-5379-4110-a4e4-6a78da2a3fb2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317564231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_in
tg_err.317564231
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.704511091
Short name T889
Test name
Test status
Simulation time 558857955 ps
CPU time 1.43 seconds
Started Jun 10 06:44:26 PM PDT 24
Finished Jun 10 06:44:28 PM PDT 24
Peak memory 201760 kb
Host smart-00dacc4e-3623-4115-be34-295271cd8f07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704511091 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.704511091
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.566840648
Short name T154
Test name
Test status
Simulation time 584317980 ps
CPU time 1.05 seconds
Started Jun 10 06:44:26 PM PDT 24
Finished Jun 10 06:44:28 PM PDT 24
Peak memory 201684 kb
Host smart-d8c351fc-6f88-44d0-acd9-a5ba79afc25d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566840648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.566840648
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1266897516
Short name T850
Test name
Test status
Simulation time 385967027 ps
CPU time 1.02 seconds
Started Jun 10 06:44:25 PM PDT 24
Finished Jun 10 06:44:27 PM PDT 24
Peak memory 201704 kb
Host smart-ed600481-cf1c-44fe-a9c7-5d1106d652a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266897516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.1266897516
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.3469261852
Short name T878
Test name
Test status
Simulation time 2420879533 ps
CPU time 3.64 seconds
Started Jun 10 06:44:26 PM PDT 24
Finished Jun 10 06:44:30 PM PDT 24
Peak memory 201896 kb
Host smart-ed06a034-72ea-4e5b-b3a3-b8ceab1d2904
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469261852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.3469261852
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.1515368210
Short name T904
Test name
Test status
Simulation time 382582571 ps
CPU time 2.39 seconds
Started Jun 10 06:44:28 PM PDT 24
Finished Jun 10 06:44:31 PM PDT 24
Peak memory 202036 kb
Host smart-1e8d7d12-b8c1-4780-a5a0-fb6f66abf206
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515368210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.1515368210
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.178564760
Short name T844
Test name
Test status
Simulation time 4692526906 ps
CPU time 12.16 seconds
Started Jun 10 06:44:26 PM PDT 24
Finished Jun 10 06:44:39 PM PDT 24
Peak memory 202036 kb
Host smart-9519766f-0273-43a1-a803-55779e52cfc6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178564760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_in
tg_err.178564760
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.2608726374
Short name T97
Test name
Test status
Simulation time 382054213 ps
CPU time 1.26 seconds
Started Jun 10 06:44:27 PM PDT 24
Finished Jun 10 06:44:29 PM PDT 24
Peak memory 201720 kb
Host smart-7fc7969f-862d-4c59-9a4b-a9f2156e403f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608726374 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.2608726374
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3511122153
Short name T138
Test name
Test status
Simulation time 323987549 ps
CPU time 0.95 seconds
Started Jun 10 06:44:28 PM PDT 24
Finished Jun 10 06:44:29 PM PDT 24
Peak memory 201656 kb
Host smart-6535c211-f445-4106-b945-729dd8669d8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511122153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.3511122153
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.649031977
Short name T823
Test name
Test status
Simulation time 360421962 ps
CPU time 1.08 seconds
Started Jun 10 06:44:26 PM PDT 24
Finished Jun 10 06:44:28 PM PDT 24
Peak memory 201620 kb
Host smart-1f442bf7-323f-4e88-9725-983d4b942a8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649031977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.649031977
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.341393727
Short name T816
Test name
Test status
Simulation time 4854481571 ps
CPU time 3.87 seconds
Started Jun 10 06:44:27 PM PDT 24
Finished Jun 10 06:44:31 PM PDT 24
Peak memory 202024 kb
Host smart-43caf316-4f6d-4754-b4b3-aa892d915311
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341393727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_c
trl_same_csr_outstanding.341393727
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2482035055
Short name T91
Test name
Test status
Simulation time 524818323 ps
CPU time 1.64 seconds
Started Jun 10 06:44:26 PM PDT 24
Finished Jun 10 06:44:28 PM PDT 24
Peak memory 201984 kb
Host smart-a79a5aee-d689-49cb-b163-3473d6a534f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482035055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.2482035055
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.4200074440
Short name T840
Test name
Test status
Simulation time 4545065357 ps
CPU time 4.26 seconds
Started Jun 10 06:44:27 PM PDT 24
Finished Jun 10 06:44:32 PM PDT 24
Peak memory 202004 kb
Host smart-f63b3e7e-7667-4c07-8e7b-2bee50f06ba3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200074440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.4200074440
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.4035768573
Short name T900
Test name
Test status
Simulation time 593591658 ps
CPU time 1.5 seconds
Started Jun 10 06:44:32 PM PDT 24
Finished Jun 10 06:44:33 PM PDT 24
Peak memory 210164 kb
Host smart-47ec90c0-336e-4693-97b6-30e720a03065
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035768573 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.4035768573
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.279486776
Short name T917
Test name
Test status
Simulation time 448344843 ps
CPU time 0.8 seconds
Started Jun 10 06:44:33 PM PDT 24
Finished Jun 10 06:44:34 PM PDT 24
Peak memory 201724 kb
Host smart-e01022fb-5a9f-4cd9-a61e-a143f977b538
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279486776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.279486776
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.1766662390
Short name T811
Test name
Test status
Simulation time 367173304 ps
CPU time 0.83 seconds
Started Jun 10 06:44:28 PM PDT 24
Finished Jun 10 06:44:29 PM PDT 24
Peak memory 201708 kb
Host smart-95294d0b-b742-4916-ab3d-89d877e58f69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766662390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.1766662390
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1128411129
Short name T866
Test name
Test status
Simulation time 2437541568 ps
CPU time 3.09 seconds
Started Jun 10 06:44:34 PM PDT 24
Finished Jun 10 06:44:38 PM PDT 24
Peak memory 201792 kb
Host smart-198f2624-c4d8-4e96-84c4-394cc7c66db8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128411129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.1128411129
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3423407797
Short name T877
Test name
Test status
Simulation time 463182278 ps
CPU time 1.96 seconds
Started Jun 10 06:44:28 PM PDT 24
Finished Jun 10 06:44:31 PM PDT 24
Peak memory 201944 kb
Host smart-1a8c2752-915c-46f4-a6db-45e919fde2fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423407797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.3423407797
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3062373811
Short name T863
Test name
Test status
Simulation time 539673999 ps
CPU time 1.19 seconds
Started Jun 10 06:44:33 PM PDT 24
Finished Jun 10 06:44:35 PM PDT 24
Peak memory 201788 kb
Host smart-b92cea54-e38b-4be0-9809-c33adfb0406a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062373811 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.3062373811
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3949968708
Short name T158
Test name
Test status
Simulation time 524319272 ps
CPU time 1.04 seconds
Started Jun 10 06:44:34 PM PDT 24
Finished Jun 10 06:44:35 PM PDT 24
Peak memory 201708 kb
Host smart-dcc87f69-a7be-44e7-80a9-7fc50a0709b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949968708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.3949968708
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.3549574029
Short name T814
Test name
Test status
Simulation time 485020264 ps
CPU time 1.1 seconds
Started Jun 10 06:44:34 PM PDT 24
Finished Jun 10 06:44:36 PM PDT 24
Peak memory 201748 kb
Host smart-11daff11-8970-41e8-999a-7bf8a248f32e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549574029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.3549574029
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2092590394
Short name T817
Test name
Test status
Simulation time 2676858097 ps
CPU time 2.49 seconds
Started Jun 10 06:44:36 PM PDT 24
Finished Jun 10 06:44:39 PM PDT 24
Peak memory 201788 kb
Host smart-3973af8d-62d0-4b1d-aea4-ac959a2a92bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092590394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.2092590394
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3236805094
Short name T101
Test name
Test status
Simulation time 415468818 ps
CPU time 1.5 seconds
Started Jun 10 06:44:37 PM PDT 24
Finished Jun 10 06:44:39 PM PDT 24
Peak memory 201960 kb
Host smart-e3b22e39-51d4-4976-a3cf-31217eaef159
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236805094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.3236805094
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.1792659229
Short name T361
Test name
Test status
Simulation time 4217315432 ps
CPU time 11.15 seconds
Started Jun 10 06:44:31 PM PDT 24
Finished Jun 10 06:44:43 PM PDT 24
Peak memory 201964 kb
Host smart-1fe5363f-2c3b-407f-865b-470ac7ce410c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792659229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.1792659229
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1385413064
Short name T839
Test name
Test status
Simulation time 1276375110 ps
CPU time 4.99 seconds
Started Jun 10 06:43:55 PM PDT 24
Finished Jun 10 06:44:00 PM PDT 24
Peak memory 201856 kb
Host smart-8bbfeba8-d042-4bb2-bc84-055c848b8e44
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385413064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.1385413064
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3557310204
Short name T148
Test name
Test status
Simulation time 16762517577 ps
CPU time 28.29 seconds
Started Jun 10 06:43:58 PM PDT 24
Finished Jun 10 06:44:27 PM PDT 24
Peak memory 201988 kb
Host smart-6f6d395b-9313-4bb3-8a85-709037281e35
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557310204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.3557310204
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3421143786
Short name T142
Test name
Test status
Simulation time 1297688758 ps
CPU time 1.79 seconds
Started Jun 10 06:43:56 PM PDT 24
Finished Jun 10 06:43:58 PM PDT 24
Peak memory 201732 kb
Host smart-a4968f05-25ef-45c0-88d5-0d2c4e00d328
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421143786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.3421143786
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2154764783
Short name T868
Test name
Test status
Simulation time 475359250 ps
CPU time 1.27 seconds
Started Jun 10 06:43:56 PM PDT 24
Finished Jun 10 06:43:58 PM PDT 24
Peak memory 201740 kb
Host smart-87aa0e1c-501b-4c62-b20c-0655a4d09250
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154764783 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.2154764783
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3780099684
Short name T834
Test name
Test status
Simulation time 416837153 ps
CPU time 1.81 seconds
Started Jun 10 06:43:55 PM PDT 24
Finished Jun 10 06:43:57 PM PDT 24
Peak memory 201720 kb
Host smart-5701532a-f7f1-4eda-a0f0-a50875e32107
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780099684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.3780099684
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3331785545
Short name T815
Test name
Test status
Simulation time 304656147 ps
CPU time 0.96 seconds
Started Jun 10 06:43:55 PM PDT 24
Finished Jun 10 06:43:56 PM PDT 24
Peak memory 201756 kb
Host smart-69a7afda-252f-410b-a685-daf9703e6f53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331785545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.3331785545
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.968966287
Short name T828
Test name
Test status
Simulation time 2762212817 ps
CPU time 7.51 seconds
Started Jun 10 06:43:57 PM PDT 24
Finished Jun 10 06:44:05 PM PDT 24
Peak memory 201804 kb
Host smart-9d985029-6f80-4505-a92e-45f6b3f31510
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968966287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ct
rl_same_csr_outstanding.968966287
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.227510746
Short name T83
Test name
Test status
Simulation time 4600005274 ps
CPU time 4.46 seconds
Started Jun 10 06:43:57 PM PDT 24
Finished Jun 10 06:44:01 PM PDT 24
Peak memory 202020 kb
Host smart-6cbb0121-12c7-499a-bbef-167b3bbec8fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227510746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_int
g_err.227510746
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.1707553644
Short name T824
Test name
Test status
Simulation time 314016148 ps
CPU time 1.04 seconds
Started Jun 10 06:44:37 PM PDT 24
Finished Jun 10 06:44:38 PM PDT 24
Peak memory 201628 kb
Host smart-dd173397-e5cd-4177-916f-fdfee4bafa68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707553644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.1707553644
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.4273037684
Short name T852
Test name
Test status
Simulation time 420469633 ps
CPU time 1.58 seconds
Started Jun 10 06:44:36 PM PDT 24
Finished Jun 10 06:44:38 PM PDT 24
Peak memory 201668 kb
Host smart-6f7d8ac9-a8a0-4d5f-92b1-f5116914c54e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273037684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.4273037684
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.3760843014
Short name T825
Test name
Test status
Simulation time 450181809 ps
CPU time 0.73 seconds
Started Jun 10 06:44:36 PM PDT 24
Finished Jun 10 06:44:37 PM PDT 24
Peak memory 201708 kb
Host smart-d059bdb1-0e14-46e2-bb4c-70ca8b659a93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760843014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.3760843014
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.1494281816
Short name T892
Test name
Test status
Simulation time 411951161 ps
CPU time 0.75 seconds
Started Jun 10 06:44:43 PM PDT 24
Finished Jun 10 06:44:44 PM PDT 24
Peak memory 201708 kb
Host smart-9a111471-4240-4148-915b-ee6d39b3a58d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494281816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.1494281816
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.230299950
Short name T810
Test name
Test status
Simulation time 358179585 ps
CPU time 1.4 seconds
Started Jun 10 06:44:38 PM PDT 24
Finished Jun 10 06:44:40 PM PDT 24
Peak memory 201688 kb
Host smart-2fd11491-4631-4509-a04f-650c49ed8096
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230299950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.230299950
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.3355064779
Short name T829
Test name
Test status
Simulation time 485207046 ps
CPU time 1.77 seconds
Started Jun 10 06:44:39 PM PDT 24
Finished Jun 10 06:44:41 PM PDT 24
Peak memory 201648 kb
Host smart-8f4082ca-3fff-40d9-bbf6-194f673925ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355064779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.3355064779
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.3684794379
Short name T885
Test name
Test status
Simulation time 533057858 ps
CPU time 0.92 seconds
Started Jun 10 06:44:38 PM PDT 24
Finished Jun 10 06:44:40 PM PDT 24
Peak memory 201680 kb
Host smart-8a0ba6ea-6fe7-4e7e-8290-dda417c154f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684794379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.3684794379
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.1665850656
Short name T842
Test name
Test status
Simulation time 321397681 ps
CPU time 0.89 seconds
Started Jun 10 06:44:38 PM PDT 24
Finished Jun 10 06:44:39 PM PDT 24
Peak memory 201684 kb
Host smart-e082b9b2-ce24-4bf5-9bf2-d16913ae1595
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665850656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.1665850656
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3522716697
Short name T819
Test name
Test status
Simulation time 348125448 ps
CPU time 1.45 seconds
Started Jun 10 06:44:38 PM PDT 24
Finished Jun 10 06:44:39 PM PDT 24
Peak memory 201672 kb
Host smart-6f26a2e2-4cc8-4931-bc7f-f97a0dc173cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522716697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.3522716697
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.635263636
Short name T837
Test name
Test status
Simulation time 461818485 ps
CPU time 1.31 seconds
Started Jun 10 06:44:42 PM PDT 24
Finished Jun 10 06:44:44 PM PDT 24
Peak memory 201684 kb
Host smart-452818ec-3cea-4c49-acb4-7639eac7a865
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635263636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.635263636
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.1789900633
Short name T902
Test name
Test status
Simulation time 693052918 ps
CPU time 1.87 seconds
Started Jun 10 06:43:59 PM PDT 24
Finished Jun 10 06:44:01 PM PDT 24
Peak memory 201948 kb
Host smart-5afdbaa0-7ea7-4f79-85b3-14255f002152
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789900633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.1789900633
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.902161725
Short name T149
Test name
Test status
Simulation time 20796900146 ps
CPU time 8.59 seconds
Started Jun 10 06:44:00 PM PDT 24
Finished Jun 10 06:44:09 PM PDT 24
Peak memory 202012 kb
Host smart-9247dfdd-8043-49fb-a817-bf7302d6cda1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902161725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_b
ash.902161725
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2876370569
Short name T911
Test name
Test status
Simulation time 599384404 ps
CPU time 1.47 seconds
Started Jun 10 06:44:00 PM PDT 24
Finished Jun 10 06:44:01 PM PDT 24
Peak memory 201736 kb
Host smart-760cfe55-3b80-4653-a3ad-10bab6f06837
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876370569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.2876370569
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.4159882270
Short name T98
Test name
Test status
Simulation time 524345681 ps
CPU time 2.19 seconds
Started Jun 10 06:44:01 PM PDT 24
Finished Jun 10 06:44:03 PM PDT 24
Peak memory 201772 kb
Host smart-121061da-5361-488e-b967-e1a19e0f356d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159882270 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.4159882270
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.761131596
Short name T869
Test name
Test status
Simulation time 542064251 ps
CPU time 1.92 seconds
Started Jun 10 06:43:58 PM PDT 24
Finished Jun 10 06:44:00 PM PDT 24
Peak memory 201716 kb
Host smart-d088b457-34fb-449e-ad74-ed42a1d8f809
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761131596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.761131596
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.216160052
Short name T880
Test name
Test status
Simulation time 333485185 ps
CPU time 1.04 seconds
Started Jun 10 06:44:00 PM PDT 24
Finished Jun 10 06:44:01 PM PDT 24
Peak memory 201696 kb
Host smart-bf501bf2-5b57-41b3-9a6f-1315948d864c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216160052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.216160052
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2657637272
Short name T913
Test name
Test status
Simulation time 3979035061 ps
CPU time 2.16 seconds
Started Jun 10 06:44:01 PM PDT 24
Finished Jun 10 06:44:03 PM PDT 24
Peak memory 202028 kb
Host smart-74650c9a-2748-4816-973e-93394b52465b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657637272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.2657637272
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.1613710415
Short name T843
Test name
Test status
Simulation time 476146259 ps
CPU time 2.52 seconds
Started Jun 10 06:44:01 PM PDT 24
Finished Jun 10 06:44:04 PM PDT 24
Peak memory 210204 kb
Host smart-68f8b00c-6f34-489b-8048-8f59ac975697
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613710415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.1613710415
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.285635288
Short name T899
Test name
Test status
Simulation time 8972339697 ps
CPU time 4.83 seconds
Started Jun 10 06:43:54 PM PDT 24
Finished Jun 10 06:43:59 PM PDT 24
Peak memory 202000 kb
Host smart-fd8ab1a4-f106-4b44-b300-9413c0df7c30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285635288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_int
g_err.285635288
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.682954599
Short name T862
Test name
Test status
Simulation time 471742245 ps
CPU time 0.97 seconds
Started Jun 10 06:44:41 PM PDT 24
Finished Jun 10 06:44:42 PM PDT 24
Peak memory 201680 kb
Host smart-efd40c54-7874-42f4-a068-959a97828ecb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682954599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.682954599
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.973837134
Short name T848
Test name
Test status
Simulation time 509175477 ps
CPU time 0.89 seconds
Started Jun 10 06:44:44 PM PDT 24
Finished Jun 10 06:44:45 PM PDT 24
Peak memory 201700 kb
Host smart-42129b1e-ee5f-4f65-a2c4-504f8ec98c2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973837134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.973837134
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.63352513
Short name T883
Test name
Test status
Simulation time 322789661 ps
CPU time 1.33 seconds
Started Jun 10 06:44:41 PM PDT 24
Finished Jun 10 06:44:42 PM PDT 24
Peak memory 201664 kb
Host smart-b08c8fb7-e5f0-49ac-a0d7-7152d2222405
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63352513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.63352513
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.271384549
Short name T859
Test name
Test status
Simulation time 473564448 ps
CPU time 1.82 seconds
Started Jun 10 06:44:41 PM PDT 24
Finished Jun 10 06:44:43 PM PDT 24
Peak memory 201692 kb
Host smart-4cdd277e-48bf-4ad5-b304-c8ec8fe20743
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271384549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.271384549
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2378564461
Short name T894
Test name
Test status
Simulation time 455249039 ps
CPU time 1.58 seconds
Started Jun 10 06:44:41 PM PDT 24
Finished Jun 10 06:44:43 PM PDT 24
Peak memory 201772 kb
Host smart-9f45ab69-e57d-4f41-bea3-0ce723b40edd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378564461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.2378564461
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.172001732
Short name T871
Test name
Test status
Simulation time 345369173 ps
CPU time 0.8 seconds
Started Jun 10 06:44:42 PM PDT 24
Finished Jun 10 06:44:43 PM PDT 24
Peak memory 201716 kb
Host smart-3224740a-8b8e-49df-9651-8e960b9bb039
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172001732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.172001732
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2963087734
Short name T905
Test name
Test status
Simulation time 372428819 ps
CPU time 0.85 seconds
Started Jun 10 06:44:45 PM PDT 24
Finished Jun 10 06:44:46 PM PDT 24
Peak memory 201736 kb
Host smart-a6de4707-942e-4319-a093-9f13175a34e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963087734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.2963087734
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.4278318635
Short name T903
Test name
Test status
Simulation time 391368791 ps
CPU time 1.54 seconds
Started Jun 10 06:44:47 PM PDT 24
Finished Jun 10 06:44:49 PM PDT 24
Peak memory 201800 kb
Host smart-1508456d-529a-48f7-a3fc-b755025dfc6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278318635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.4278318635
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.530807010
Short name T882
Test name
Test status
Simulation time 445407553 ps
CPU time 0.98 seconds
Started Jun 10 06:44:46 PM PDT 24
Finished Jun 10 06:44:47 PM PDT 24
Peak memory 201672 kb
Host smart-327f519b-ba0c-4371-95b9-69b04c2227bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530807010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.530807010
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.1074909565
Short name T812
Test name
Test status
Simulation time 412787911 ps
CPU time 0.88 seconds
Started Jun 10 06:44:46 PM PDT 24
Finished Jun 10 06:44:48 PM PDT 24
Peak memory 201808 kb
Host smart-53badfff-a19d-4ec8-90f9-743d70e0369e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074909565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.1074909565
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.855611690
Short name T145
Test name
Test status
Simulation time 1075354359 ps
CPU time 2.91 seconds
Started Jun 10 06:44:04 PM PDT 24
Finished Jun 10 06:44:08 PM PDT 24
Peak memory 201956 kb
Host smart-818856ad-5a90-4d24-9dcb-9352df726b87
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855611690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alias
ing.855611690
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3711414575
Short name T141
Test name
Test status
Simulation time 40687076216 ps
CPU time 94.14 seconds
Started Jun 10 06:44:04 PM PDT 24
Finished Jun 10 06:45:38 PM PDT 24
Peak memory 202004 kb
Host smart-1748c3b1-a082-420e-957e-b3d36defce90
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711414575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.3711414575
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.1441275714
Short name T161
Test name
Test status
Simulation time 861380909 ps
CPU time 1.75 seconds
Started Jun 10 06:44:01 PM PDT 24
Finished Jun 10 06:44:03 PM PDT 24
Peak memory 201720 kb
Host smart-4667f7db-d6b6-4065-a910-bf3cde813b60
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441275714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.1441275714
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.1031058336
Short name T99
Test name
Test status
Simulation time 327102836 ps
CPU time 1.15 seconds
Started Jun 10 06:44:02 PM PDT 24
Finished Jun 10 06:44:04 PM PDT 24
Peak memory 201880 kb
Host smart-f4b4cc01-369b-49ba-8672-14cd05bd4880
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031058336 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.1031058336
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2289040823
Short name T845
Test name
Test status
Simulation time 465624252 ps
CPU time 0.91 seconds
Started Jun 10 06:43:59 PM PDT 24
Finished Jun 10 06:44:01 PM PDT 24
Peak memory 201772 kb
Host smart-b5dcf8dc-281d-4165-b020-fb9c976ea4ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289040823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.2289040823
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.3594457235
Short name T157
Test name
Test status
Simulation time 2152004842 ps
CPU time 4.72 seconds
Started Jun 10 06:44:06 PM PDT 24
Finished Jun 10 06:44:11 PM PDT 24
Peak memory 201788 kb
Host smart-648c3fc0-c6d8-4eb1-bbe3-7437ad5ac389
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594457235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.3594457235
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.869004482
Short name T907
Test name
Test status
Simulation time 469107752 ps
CPU time 2.59 seconds
Started Jun 10 06:44:01 PM PDT 24
Finished Jun 10 06:44:04 PM PDT 24
Peak memory 210148 kb
Host smart-cc40da37-8230-4cc9-9a97-b51c3edab800
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869004482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.869004482
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.784560079
Short name T82
Test name
Test status
Simulation time 8053301495 ps
CPU time 22.2 seconds
Started Jun 10 06:43:57 PM PDT 24
Finished Jun 10 06:44:20 PM PDT 24
Peak memory 201960 kb
Host smart-d35b897d-2166-4f96-9921-96327a75f64e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784560079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_int
g_err.784560079
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3185418923
Short name T818
Test name
Test status
Simulation time 502281107 ps
CPU time 0.89 seconds
Started Jun 10 06:44:47 PM PDT 24
Finished Jun 10 06:44:48 PM PDT 24
Peak memory 201728 kb
Host smart-db1df60a-5ec2-455a-bd5c-44db51a6f6b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185418923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.3185418923
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.4136140244
Short name T873
Test name
Test status
Simulation time 483659225 ps
CPU time 0.94 seconds
Started Jun 10 06:44:47 PM PDT 24
Finished Jun 10 06:44:48 PM PDT 24
Peak memory 201712 kb
Host smart-60c76dec-a055-4d43-a46d-22e7510da10d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136140244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.4136140244
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.4081346700
Short name T865
Test name
Test status
Simulation time 516223859 ps
CPU time 0.68 seconds
Started Jun 10 06:44:52 PM PDT 24
Finished Jun 10 06:44:53 PM PDT 24
Peak memory 201696 kb
Host smart-2e9fd0f9-1ec2-488c-8f62-a5cac26188ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081346700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.4081346700
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.3248225120
Short name T916
Test name
Test status
Simulation time 506859837 ps
CPU time 1.85 seconds
Started Jun 10 06:44:50 PM PDT 24
Finished Jun 10 06:44:52 PM PDT 24
Peak memory 201712 kb
Host smart-e753d4fa-35ae-4e58-bbe8-139844938e58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248225120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.3248225120
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3402649843
Short name T841
Test name
Test status
Simulation time 518216009 ps
CPU time 1.78 seconds
Started Jun 10 06:44:48 PM PDT 24
Finished Jun 10 06:44:50 PM PDT 24
Peak memory 201680 kb
Host smart-c0692bfe-973b-46d1-9c3c-5da2f679c7dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402649843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.3402649843
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.3818792404
Short name T809
Test name
Test status
Simulation time 348256523 ps
CPU time 0.89 seconds
Started Jun 10 06:44:52 PM PDT 24
Finished Jun 10 06:44:53 PM PDT 24
Peak memory 201700 kb
Host smart-8240cd33-805f-4ebe-929c-22d331a8969b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818792404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.3818792404
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.258743611
Short name T919
Test name
Test status
Simulation time 349384904 ps
CPU time 0.83 seconds
Started Jun 10 06:44:49 PM PDT 24
Finished Jun 10 06:44:50 PM PDT 24
Peak memory 201700 kb
Host smart-b6dc734d-09b8-49e6-a96b-6551941b2c07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258743611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.258743611
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.2674955638
Short name T856
Test name
Test status
Simulation time 435295063 ps
CPU time 0.88 seconds
Started Jun 10 06:44:49 PM PDT 24
Finished Jun 10 06:44:50 PM PDT 24
Peak memory 201708 kb
Host smart-80a2c7ca-25bc-4ba8-8899-3e8770edcca1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674955638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.2674955638
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2717834125
Short name T827
Test name
Test status
Simulation time 472636035 ps
CPU time 1.74 seconds
Started Jun 10 06:44:51 PM PDT 24
Finished Jun 10 06:44:53 PM PDT 24
Peak memory 201712 kb
Host smart-b1ac2ecb-03a3-4fdb-9cec-1529a49b28b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717834125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.2717834125
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.1401465758
Short name T908
Test name
Test status
Simulation time 354418717 ps
CPU time 0.82 seconds
Started Jun 10 06:44:53 PM PDT 24
Finished Jun 10 06:44:54 PM PDT 24
Peak memory 201540 kb
Host smart-2a3df1c9-9f18-4a21-8047-ab873c087529
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401465758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.1401465758
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.4148125456
Short name T833
Test name
Test status
Simulation time 542430436 ps
CPU time 1.6 seconds
Started Jun 10 06:44:03 PM PDT 24
Finished Jun 10 06:44:05 PM PDT 24
Peak memory 201792 kb
Host smart-9f4e2a79-5823-45e7-8621-510d59809c2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148125456 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.4148125456
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2981797912
Short name T152
Test name
Test status
Simulation time 539609632 ps
CPU time 0.98 seconds
Started Jun 10 06:44:05 PM PDT 24
Finished Jun 10 06:44:06 PM PDT 24
Peak memory 201696 kb
Host smart-de28fcbb-6d57-4f9f-8ee7-3a90ebfc13e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981797912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.2981797912
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.4155782275
Short name T836
Test name
Test status
Simulation time 501436037 ps
CPU time 0.83 seconds
Started Jun 10 06:44:03 PM PDT 24
Finished Jun 10 06:44:04 PM PDT 24
Peak memory 201680 kb
Host smart-eb716c68-aedc-461e-b3fa-45479bdb4b0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155782275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.4155782275
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.257896408
Short name T830
Test name
Test status
Simulation time 3022585066 ps
CPU time 10.23 seconds
Started Jun 10 06:44:03 PM PDT 24
Finished Jun 10 06:44:14 PM PDT 24
Peak memory 201788 kb
Host smart-b27b4c8d-9083-4df7-88c8-9b6a821c2f60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257896408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ct
rl_same_csr_outstanding.257896408
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.2133807852
Short name T891
Test name
Test status
Simulation time 602399896 ps
CPU time 3.08 seconds
Started Jun 10 06:44:04 PM PDT 24
Finished Jun 10 06:44:07 PM PDT 24
Peak memory 210252 kb
Host smart-b8025da8-fc9e-479d-9173-c5547bf9a312
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133807852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.2133807852
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3754276009
Short name T360
Test name
Test status
Simulation time 7925323363 ps
CPU time 21.54 seconds
Started Jun 10 06:44:04 PM PDT 24
Finished Jun 10 06:44:26 PM PDT 24
Peak memory 201968 kb
Host smart-88ecce5a-55f5-4281-8058-6509b6d67e80
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754276009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.3754276009
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.3743693332
Short name T854
Test name
Test status
Simulation time 471841295 ps
CPU time 1.13 seconds
Started Jun 10 06:44:07 PM PDT 24
Finished Jun 10 06:44:09 PM PDT 24
Peak memory 201768 kb
Host smart-49f97e46-ce7a-4ec9-9549-4d6c40b2c818
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743693332 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.3743693332
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.2060850950
Short name T909
Test name
Test status
Simulation time 339966944 ps
CPU time 1.64 seconds
Started Jun 10 06:44:06 PM PDT 24
Finished Jun 10 06:44:08 PM PDT 24
Peak memory 201736 kb
Host smart-7728fe47-2120-45e4-a178-5c7648980d34
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060850950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.2060850950
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2861458693
Short name T853
Test name
Test status
Simulation time 501477451 ps
CPU time 0.79 seconds
Started Jun 10 06:44:07 PM PDT 24
Finished Jun 10 06:44:08 PM PDT 24
Peak memory 201700 kb
Host smart-37aa5681-c53d-4cb2-8f88-1c2ea1e35aba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861458693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.2861458693
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3066020856
Short name T822
Test name
Test status
Simulation time 5284990271 ps
CPU time 7.57 seconds
Started Jun 10 06:44:06 PM PDT 24
Finished Jun 10 06:44:14 PM PDT 24
Peak memory 201980 kb
Host smart-976e345c-19cf-4e3e-8f72-4c1a97f1e094
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066020856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.3066020856
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.60994661
Short name T901
Test name
Test status
Simulation time 398161931 ps
CPU time 2.65 seconds
Started Jun 10 06:44:01 PM PDT 24
Finished Jun 10 06:44:04 PM PDT 24
Peak memory 201988 kb
Host smart-8a61260b-23d7-4a3b-b655-1e6b804af0c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60994661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.60994661
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.1682962380
Short name T890
Test name
Test status
Simulation time 629610477 ps
CPU time 1.63 seconds
Started Jun 10 06:44:07 PM PDT 24
Finished Jun 10 06:44:09 PM PDT 24
Peak memory 201792 kb
Host smart-f991591c-bf3e-455e-8275-9857daf1610c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682962380 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.1682962380
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.602014195
Short name T139
Test name
Test status
Simulation time 605256007 ps
CPU time 0.97 seconds
Started Jun 10 06:44:10 PM PDT 24
Finished Jun 10 06:44:11 PM PDT 24
Peak memory 201708 kb
Host smart-6393a63a-f538-498b-8735-cf83994c5476
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602014195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.602014195
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2481476964
Short name T912
Test name
Test status
Simulation time 545880841 ps
CPU time 0.91 seconds
Started Jun 10 06:44:06 PM PDT 24
Finished Jun 10 06:44:07 PM PDT 24
Peak memory 201700 kb
Host smart-3257559e-303a-4e65-9a28-9d88e78dd031
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481476964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.2481476964
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.969284248
Short name T898
Test name
Test status
Simulation time 3931002116 ps
CPU time 4.24 seconds
Started Jun 10 06:44:07 PM PDT 24
Finished Jun 10 06:44:11 PM PDT 24
Peak memory 201964 kb
Host smart-8565213e-1c28-4104-ae83-3964d0ff30fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969284248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ct
rl_same_csr_outstanding.969284248
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2175337147
Short name T918
Test name
Test status
Simulation time 369437663 ps
CPU time 2.96 seconds
Started Jun 10 06:44:06 PM PDT 24
Finished Jun 10 06:44:10 PM PDT 24
Peak memory 217800 kb
Host smart-d30afee8-bb77-47bf-87f2-a6d61437b32d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175337147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.2175337147
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.413260765
Short name T915
Test name
Test status
Simulation time 4103207098 ps
CPU time 3.85 seconds
Started Jun 10 06:44:07 PM PDT 24
Finished Jun 10 06:44:12 PM PDT 24
Peak memory 201972 kb
Host smart-c73e8514-838d-4069-9c00-91e1f33bbd1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413260765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_int
g_err.413260765
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.163160839
Short name T857
Test name
Test status
Simulation time 491967000 ps
CPU time 2.04 seconds
Started Jun 10 06:44:11 PM PDT 24
Finished Jun 10 06:44:13 PM PDT 24
Peak memory 201784 kb
Host smart-7883a512-e3e2-423d-aebd-d8738e79d697
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163160839 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.163160839
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.1334439722
Short name T155
Test name
Test status
Simulation time 684956415 ps
CPU time 1.01 seconds
Started Jun 10 06:44:11 PM PDT 24
Finished Jun 10 06:44:12 PM PDT 24
Peak memory 201704 kb
Host smart-2827de9f-334b-4ecf-9a7a-b45e5306b61d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334439722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.1334439722
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.2608949157
Short name T826
Test name
Test status
Simulation time 399341857 ps
CPU time 1.61 seconds
Started Jun 10 06:44:11 PM PDT 24
Finished Jun 10 06:44:13 PM PDT 24
Peak memory 201676 kb
Host smart-fb6631ba-9cbb-475a-9b76-1e5d31c43d00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608949157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.2608949157
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3405846913
Short name T71
Test name
Test status
Simulation time 4773474963 ps
CPU time 5.81 seconds
Started Jun 10 06:44:12 PM PDT 24
Finished Jun 10 06:44:18 PM PDT 24
Peak memory 201976 kb
Host smart-5940f76c-831a-4a9e-a995-b2b57bf1a085
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405846913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.3405846913
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1910608129
Short name T895
Test name
Test status
Simulation time 812792804 ps
CPU time 2.58 seconds
Started Jun 10 06:44:07 PM PDT 24
Finished Jun 10 06:44:10 PM PDT 24
Peak memory 211240 kb
Host smart-4a5768eb-85d7-471c-a569-400bd3d7fcf2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910608129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.1910608129
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1019662524
Short name T887
Test name
Test status
Simulation time 4871155202 ps
CPU time 2.76 seconds
Started Jun 10 06:44:11 PM PDT 24
Finished Jun 10 06:44:14 PM PDT 24
Peak memory 201988 kb
Host smart-683a1ee1-3c28-464d-974d-53f149aa5f66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019662524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.1019662524
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3475147827
Short name T846
Test name
Test status
Simulation time 560713529 ps
CPU time 2.19 seconds
Started Jun 10 06:44:14 PM PDT 24
Finished Jun 10 06:44:16 PM PDT 24
Peak memory 201792 kb
Host smart-fb71dd6d-e948-46c3-817c-9e984fef4ac7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475147827 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.3475147827
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.787768802
Short name T159
Test name
Test status
Simulation time 466157650 ps
CPU time 1.04 seconds
Started Jun 10 06:44:14 PM PDT 24
Finished Jun 10 06:44:16 PM PDT 24
Peak memory 201576 kb
Host smart-a18c5ac3-b4b3-444c-8468-130e4027887c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787768802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.787768802
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.1458752885
Short name T849
Test name
Test status
Simulation time 478437094 ps
CPU time 0.9 seconds
Started Jun 10 06:44:14 PM PDT 24
Finished Jun 10 06:44:15 PM PDT 24
Peak memory 201676 kb
Host smart-278a6ac3-f7ba-4cd9-ab03-b1c2bfd7e151
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458752885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.1458752885
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2880928209
Short name T73
Test name
Test status
Simulation time 2281830671 ps
CPU time 2.54 seconds
Started Jun 10 06:44:14 PM PDT 24
Finished Jun 10 06:44:17 PM PDT 24
Peak memory 201692 kb
Host smart-658df2ad-68b4-45a1-8c5d-cd8b249b232c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880928209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.2880928209
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1441887926
Short name T855
Test name
Test status
Simulation time 581337484 ps
CPU time 3.2 seconds
Started Jun 10 06:44:09 PM PDT 24
Finished Jun 10 06:44:13 PM PDT 24
Peak memory 201980 kb
Host smart-4524efe6-3a63-490e-9394-9d308f98242b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441887926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.1441887926
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.4179024126
Short name T914
Test name
Test status
Simulation time 4350471596 ps
CPU time 7.11 seconds
Started Jun 10 06:44:10 PM PDT 24
Finished Jun 10 06:44:17 PM PDT 24
Peak memory 202008 kb
Host smart-be64b18a-6f86-43d1-816d-b80b2672b117
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179024126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.4179024126
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.621148411
Short name T657
Test name
Test status
Simulation time 501366495 ps
CPU time 0.8 seconds
Started Jun 10 07:16:15 PM PDT 24
Finished Jun 10 07:16:18 PM PDT 24
Peak memory 201500 kb
Host smart-6177fd5f-8d48-4e4f-bc73-b1483f6a884b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621148411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.621148411
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.2871081440
Short name T512
Test name
Test status
Simulation time 337687698676 ps
CPU time 467.05 seconds
Started Jun 10 07:16:20 PM PDT 24
Finished Jun 10 07:24:11 PM PDT 24
Peak memory 201776 kb
Host smart-c1524dac-17f5-4b20-bce5-e1b45931ea25
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871081440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.2871081440
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.4025904674
Short name T270
Test name
Test status
Simulation time 491388512559 ps
CPU time 1182.2 seconds
Started Jun 10 07:16:19 PM PDT 24
Finished Jun 10 07:36:05 PM PDT 24
Peak memory 201876 kb
Host smart-47185ff0-a832-4ecf-9b0a-e79fd2846b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025904674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.4025904674
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.1319951432
Short name T579
Test name
Test status
Simulation time 494478753443 ps
CPU time 116.67 seconds
Started Jun 10 07:16:20 PM PDT 24
Finished Jun 10 07:18:21 PM PDT 24
Peak memory 201600 kb
Host smart-d653a7dd-c334-488b-a536-fd1b6b362263
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319951432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.1319951432
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.932334618
Short name T241
Test name
Test status
Simulation time 493327106220 ps
CPU time 315.52 seconds
Started Jun 10 07:16:17 PM PDT 24
Finished Jun 10 07:21:35 PM PDT 24
Peak memory 201796 kb
Host smart-d6da5c89-d587-4b14-a28e-067b5d08449f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932334618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.932334618
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.1400750693
Short name T375
Test name
Test status
Simulation time 163900126970 ps
CPU time 385.4 seconds
Started Jun 10 07:16:14 PM PDT 24
Finished Jun 10 07:22:42 PM PDT 24
Peak memory 201868 kb
Host smart-cfe0369a-092f-4420-aa05-1fbc3f11f6a9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400750693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.1400750693
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.3739857539
Short name T259
Test name
Test status
Simulation time 192224474197 ps
CPU time 454.55 seconds
Started Jun 10 07:16:16 PM PDT 24
Finished Jun 10 07:23:53 PM PDT 24
Peak memory 201808 kb
Host smart-6048dae3-b7a1-4ef0-8fba-15f9be422fd1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739857539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.3739857539
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.1927532024
Short name T588
Test name
Test status
Simulation time 400426609667 ps
CPU time 924.81 seconds
Started Jun 10 07:16:17 PM PDT 24
Finished Jun 10 07:31:44 PM PDT 24
Peak memory 201784 kb
Host smart-b66edd69-ee14-4605-9093-1e009490d5ac
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927532024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.1927532024
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.682519516
Short name T408
Test name
Test status
Simulation time 44600757256 ps
CPU time 38.58 seconds
Started Jun 10 07:16:20 PM PDT 24
Finished Jun 10 07:17:03 PM PDT 24
Peak memory 201444 kb
Host smart-4cbcfe7f-3a25-4da1-8bac-3eb26c21db73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682519516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.682519516
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.1795361128
Short name T516
Test name
Test status
Simulation time 4219999945 ps
CPU time 4.78 seconds
Started Jun 10 07:16:17 PM PDT 24
Finished Jun 10 07:16:23 PM PDT 24
Peak memory 201604 kb
Host smart-8edda616-8a2a-4461-bc69-767e8aba1617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795361128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.1795361128
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.4040366740
Short name T383
Test name
Test status
Simulation time 5887648950 ps
CPU time 10.23 seconds
Started Jun 10 07:16:19 PM PDT 24
Finished Jun 10 07:16:32 PM PDT 24
Peak memory 201648 kb
Host smart-6c177bce-38bf-44cf-8e79-8f59ff62ca8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040366740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.4040366740
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.3257542637
Short name T319
Test name
Test status
Simulation time 345213825032 ps
CPU time 212.68 seconds
Started Jun 10 07:16:18 PM PDT 24
Finished Jun 10 07:19:55 PM PDT 24
Peak memory 201900 kb
Host smart-6387344e-c47b-4b2a-84ae-d81075210803
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257542637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
3257542637
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.2806924664
Short name T267
Test name
Test status
Simulation time 210749319162 ps
CPU time 162.23 seconds
Started Jun 10 07:16:19 PM PDT 24
Finished Jun 10 07:19:05 PM PDT 24
Peak memory 201816 kb
Host smart-947c6e07-474d-4a4b-86b6-14e7218e5806
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806924664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.2806924664
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.343906333
Short name T694
Test name
Test status
Simulation time 167675476042 ps
CPU time 190.53 seconds
Started Jun 10 07:16:19 PM PDT 24
Finished Jun 10 07:19:33 PM PDT 24
Peak memory 201800 kb
Host smart-b01b0798-ecea-4d4d-9de2-11f544bc4a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343906333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.343906333
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.2099943063
Short name T288
Test name
Test status
Simulation time 167512028226 ps
CPU time 96.58 seconds
Started Jun 10 07:16:20 PM PDT 24
Finished Jun 10 07:18:00 PM PDT 24
Peak memory 201812 kb
Host smart-389f8299-b923-45e3-88cd-9dac09f5d1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099943063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.2099943063
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.784895498
Short name T462
Test name
Test status
Simulation time 170271727622 ps
CPU time 109.54 seconds
Started Jun 10 07:16:17 PM PDT 24
Finished Jun 10 07:18:09 PM PDT 24
Peak memory 201732 kb
Host smart-afe132c6-0a30-463b-bc0d-7be5c9ad6fa5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=784895498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt
_fixed.784895498
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.854624746
Short name T686
Test name
Test status
Simulation time 319054284404 ps
CPU time 219.59 seconds
Started Jun 10 07:16:17 PM PDT 24
Finished Jun 10 07:19:59 PM PDT 24
Peak memory 201908 kb
Host smart-cd8ebce1-3fbf-4b80-88f9-2cd17c853cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854624746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.854624746
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.1456556742
Short name T126
Test name
Test status
Simulation time 167021249687 ps
CPU time 148.32 seconds
Started Jun 10 07:16:19 PM PDT 24
Finished Jun 10 07:18:51 PM PDT 24
Peak memory 201764 kb
Host smart-2b3e6511-2701-4f2b-bf16-dbe8e47f1688
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456556742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.1456556742
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.64774983
Short name T482
Test name
Test status
Simulation time 202554920582 ps
CPU time 124.02 seconds
Started Jun 10 07:16:18 PM PDT 24
Finished Jun 10 07:18:25 PM PDT 24
Peak memory 201840 kb
Host smart-76de7f23-acdb-4eb4-8563-5cb47b9a9c88
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64774983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.ad
c_ctrl_filters_wakeup_fixed.64774983
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.819727807
Short name T615
Test name
Test status
Simulation time 93902154407 ps
CPU time 457.69 seconds
Started Jun 10 07:16:20 PM PDT 24
Finished Jun 10 07:24:01 PM PDT 24
Peak memory 202108 kb
Host smart-67057ef5-eb8d-49b2-8fce-79367b57292f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819727807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.819727807
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.293065974
Short name T407
Test name
Test status
Simulation time 42459621620 ps
CPU time 102.34 seconds
Started Jun 10 07:16:20 PM PDT 24
Finished Jun 10 07:18:06 PM PDT 24
Peak memory 201596 kb
Host smart-80f08a88-a974-4eb3-b5cc-b66ec3cae172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293065974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.293065974
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.782659275
Short name T447
Test name
Test status
Simulation time 3720837876 ps
CPU time 6.37 seconds
Started Jun 10 07:16:20 PM PDT 24
Finished Jun 10 07:16:30 PM PDT 24
Peak memory 201592 kb
Host smart-6dd81c61-4bc4-453f-aba3-2768bd696c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782659275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.782659275
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.1042450820
Short name T105
Test name
Test status
Simulation time 4206899635 ps
CPU time 10.98 seconds
Started Jun 10 07:16:19 PM PDT 24
Finished Jun 10 07:16:34 PM PDT 24
Peak memory 217288 kb
Host smart-ba89a077-93ab-4f6b-9fc8-6fce382911a9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042450820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.1042450820
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.2450659519
Short name T751
Test name
Test status
Simulation time 6009111450 ps
CPU time 13.95 seconds
Started Jun 10 07:16:19 PM PDT 24
Finished Jun 10 07:16:36 PM PDT 24
Peak memory 201692 kb
Host smart-6b253e0e-75aa-4c36-a6bb-cc411caeab57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450659519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.2450659519
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.592886938
Short name T244
Test name
Test status
Simulation time 338998704911 ps
CPU time 404.79 seconds
Started Jun 10 07:16:19 PM PDT 24
Finished Jun 10 07:23:08 PM PDT 24
Peak memory 201764 kb
Host smart-0ca93796-41ff-44b9-9e1e-5b4bf43b58f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592886938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.592886938
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.3868476023
Short name T18
Test name
Test status
Simulation time 66889197137 ps
CPU time 33.99 seconds
Started Jun 10 07:16:19 PM PDT 24
Finished Jun 10 07:16:57 PM PDT 24
Peak memory 210092 kb
Host smart-305d5d58-0b86-42c8-9bbe-c96c48d3d077
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868476023 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.3868476023
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.1891231344
Short name T798
Test name
Test status
Simulation time 506950225 ps
CPU time 0.91 seconds
Started Jun 10 07:16:37 PM PDT 24
Finished Jun 10 07:16:42 PM PDT 24
Peak memory 201460 kb
Host smart-8acfbf50-88b5-4c48-9f9d-46f3c6e5c663
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891231344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.1891231344
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.1817529411
Short name T243
Test name
Test status
Simulation time 494735605584 ps
CPU time 238.37 seconds
Started Jun 10 07:16:37 PM PDT 24
Finished Jun 10 07:20:40 PM PDT 24
Peak memory 201872 kb
Host smart-a06cf7a4-aa90-4ecd-a2cb-ad9fdfc71c54
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817529411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.1817529411
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.1519949473
Short name T723
Test name
Test status
Simulation time 174222926988 ps
CPU time 404.6 seconds
Started Jun 10 07:16:38 PM PDT 24
Finished Jun 10 07:23:27 PM PDT 24
Peak memory 201796 kb
Host smart-ded06bed-fc90-4404-b42d-0ab3e5eef7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519949473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.1519949473
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.1126209403
Short name T295
Test name
Test status
Simulation time 333176852355 ps
CPU time 213.83 seconds
Started Jun 10 07:16:39 PM PDT 24
Finished Jun 10 07:20:17 PM PDT 24
Peak memory 201888 kb
Host smart-f4b6749d-fba0-4bfa-9609-b1c1ac6f0d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126209403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.1126209403
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.896622431
Short name T787
Test name
Test status
Simulation time 163884056607 ps
CPU time 393.85 seconds
Started Jun 10 07:16:40 PM PDT 24
Finished Jun 10 07:23:19 PM PDT 24
Peak memory 201772 kb
Host smart-99262a01-0bc2-4afe-8375-d1f1dc2ddb08
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=896622431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrup
t_fixed.896622431
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.3080619721
Short name T495
Test name
Test status
Simulation time 491696672075 ps
CPU time 543.85 seconds
Started Jun 10 07:16:40 PM PDT 24
Finished Jun 10 07:25:49 PM PDT 24
Peak memory 201740 kb
Host smart-adfa27d8-6048-4526-be70-ea55d082bce3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080619721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.3080619721
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.3423674847
Short name T461
Test name
Test status
Simulation time 189394856202 ps
CPU time 113.32 seconds
Started Jun 10 07:16:39 PM PDT 24
Finished Jun 10 07:18:37 PM PDT 24
Peak memory 201796 kb
Host smart-bb03c376-6329-4538-884b-0945a8899bf4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423674847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.3423674847
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.3975942742
Short name T576
Test name
Test status
Simulation time 402946586282 ps
CPU time 941.47 seconds
Started Jun 10 07:16:37 PM PDT 24
Finished Jun 10 07:32:22 PM PDT 24
Peak memory 201820 kb
Host smart-263108cb-2397-4378-9646-3311ecf661c8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975942742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.3975942742
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.2153659787
Short name T540
Test name
Test status
Simulation time 31158860966 ps
CPU time 75.09 seconds
Started Jun 10 07:16:34 PM PDT 24
Finished Jun 10 07:17:54 PM PDT 24
Peak memory 201620 kb
Host smart-40753e96-6482-4db2-9fd5-00bb1597edfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153659787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.2153659787
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.2918438601
Short name T605
Test name
Test status
Simulation time 3398134317 ps
CPU time 5.33 seconds
Started Jun 10 07:16:40 PM PDT 24
Finished Jun 10 07:16:51 PM PDT 24
Peak memory 201608 kb
Host smart-fb743da6-cdbe-4108-befa-567940d7713f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918438601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.2918438601
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.3766966374
Short name T802
Test name
Test status
Simulation time 6083314840 ps
CPU time 8.14 seconds
Started Jun 10 07:16:37 PM PDT 24
Finished Jun 10 07:16:49 PM PDT 24
Peak memory 201632 kb
Host smart-67df0b30-8e92-49cb-8df0-691a206e909f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766966374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.3766966374
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.3540462058
Short name T298
Test name
Test status
Simulation time 461126845989 ps
CPU time 147.53 seconds
Started Jun 10 07:16:36 PM PDT 24
Finished Jun 10 07:19:08 PM PDT 24
Peak memory 210384 kb
Host smart-dc932e56-b62b-41c3-bdf7-36abedb300fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540462058 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.3540462058
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.1250382039
Short name T403
Test name
Test status
Simulation time 487657525 ps
CPU time 1.22 seconds
Started Jun 10 07:16:51 PM PDT 24
Finished Jun 10 07:16:57 PM PDT 24
Peak memory 201484 kb
Host smart-3ca008d5-1ca9-488a-accb-fa4f5c5a777f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250382039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.1250382039
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.3157089979
Short name T769
Test name
Test status
Simulation time 179170030934 ps
CPU time 78.56 seconds
Started Jun 10 07:16:37 PM PDT 24
Finished Jun 10 07:18:00 PM PDT 24
Peak memory 201908 kb
Host smart-ded1139a-a1b7-4e53-a796-7b797fc68026
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157089979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.3157089979
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.900591716
Short name T119
Test name
Test status
Simulation time 160532239334 ps
CPU time 210.15 seconds
Started Jun 10 07:16:36 PM PDT 24
Finished Jun 10 07:20:10 PM PDT 24
Peak memory 201832 kb
Host smart-14723650-a026-4677-b516-af5fb3e42717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900591716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.900591716
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.3681937469
Short name T729
Test name
Test status
Simulation time 164868806426 ps
CPU time 379.97 seconds
Started Jun 10 07:16:41 PM PDT 24
Finished Jun 10 07:23:06 PM PDT 24
Peak memory 201852 kb
Host smart-2d125391-4686-48c5-8a0d-c6ddfec708ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681937469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.3681937469
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.1478843543
Short name T132
Test name
Test status
Simulation time 484653057680 ps
CPU time 1117.23 seconds
Started Jun 10 07:16:41 PM PDT 24
Finished Jun 10 07:35:23 PM PDT 24
Peak memory 201860 kb
Host smart-69c90bdc-661c-4e48-b3c3-f75f57220e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478843543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.1478843543
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.2669410230
Short name T630
Test name
Test status
Simulation time 167102029761 ps
CPU time 105.94 seconds
Started Jun 10 07:16:34 PM PDT 24
Finished Jun 10 07:18:24 PM PDT 24
Peak memory 201772 kb
Host smart-3a9f5f24-ba3c-472a-b421-bcebfaa58634
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669410230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.2669410230
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.3332037098
Short name T191
Test name
Test status
Simulation time 524319757874 ps
CPU time 284.74 seconds
Started Jun 10 07:16:36 PM PDT 24
Finished Jun 10 07:21:25 PM PDT 24
Peak memory 201872 kb
Host smart-3855d34a-c03d-471e-b66b-f4ee3fe2b486
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332037098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.3332037098
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.4107348394
Short name T660
Test name
Test status
Simulation time 622022225903 ps
CPU time 1510.71 seconds
Started Jun 10 07:16:37 PM PDT 24
Finished Jun 10 07:41:52 PM PDT 24
Peak memory 201752 kb
Host smart-5c2df92e-49b6-4925-a1df-dc0c239a475f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107348394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.4107348394
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.375079077
Short name T663
Test name
Test status
Simulation time 112041133561 ps
CPU time 598.96 seconds
Started Jun 10 07:16:41 PM PDT 24
Finished Jun 10 07:26:45 PM PDT 24
Peak memory 202128 kb
Host smart-63d15c93-a963-456c-834c-f72b64fb727b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375079077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.375079077
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.3594794634
Short name T479
Test name
Test status
Simulation time 28302770648 ps
CPU time 65.93 seconds
Started Jun 10 07:16:39 PM PDT 24
Finished Jun 10 07:17:49 PM PDT 24
Peak memory 201640 kb
Host smart-65a4e791-c64f-417c-83e1-d71bc500d252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594794634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.3594794634
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.3409222384
Short name T611
Test name
Test status
Simulation time 2988173390 ps
CPU time 2.55 seconds
Started Jun 10 07:16:37 PM PDT 24
Finished Jun 10 07:16:43 PM PDT 24
Peak memory 201616 kb
Host smart-61de0ae6-d7b2-47c4-902d-c46ca2550aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409222384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.3409222384
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.2465291476
Short name T455
Test name
Test status
Simulation time 5734729760 ps
CPU time 4.59 seconds
Started Jun 10 07:16:35 PM PDT 24
Finished Jun 10 07:16:43 PM PDT 24
Peak memory 201632 kb
Host smart-1c41a2de-e443-4fed-bf99-9ffc2b5f4bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465291476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.2465291476
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.2041141160
Short name T356
Test name
Test status
Simulation time 523339032961 ps
CPU time 1280.6 seconds
Started Jun 10 07:16:40 PM PDT 24
Finished Jun 10 07:38:06 PM PDT 24
Peak memory 201864 kb
Host smart-d3d88587-269f-4b85-80dd-fb713882e0dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041141160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.2041141160
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.4293344721
Short name T545
Test name
Test status
Simulation time 47884689718 ps
CPU time 248.93 seconds
Started Jun 10 07:16:38 PM PDT 24
Finished Jun 10 07:20:51 PM PDT 24
Peak memory 210388 kb
Host smart-74ebf90e-ec2f-4924-b65e-91d147501a70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293344721 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.4293344721
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.2714408477
Short name T421
Test name
Test status
Simulation time 331029201 ps
CPU time 0.77 seconds
Started Jun 10 07:17:04 PM PDT 24
Finished Jun 10 07:17:11 PM PDT 24
Peak memory 201428 kb
Host smart-a25d0e5c-a382-4e00-aa62-e7cb0856bf83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714408477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.2714408477
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.915776144
Short name T24
Test name
Test status
Simulation time 165868834789 ps
CPU time 194.8 seconds
Started Jun 10 07:16:52 PM PDT 24
Finished Jun 10 07:20:12 PM PDT 24
Peak memory 201812 kb
Host smart-a1624d89-3b1b-4c99-9f9f-9ccf11e0b3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915776144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.915776144
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.3856436214
Short name T214
Test name
Test status
Simulation time 337711676299 ps
CPU time 141.79 seconds
Started Jun 10 07:16:47 PM PDT 24
Finished Jun 10 07:19:13 PM PDT 24
Peak memory 201896 kb
Host smart-4f5278b7-c40b-4e46-a1eb-67d4865809c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856436214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.3856436214
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.3199266988
Short name T672
Test name
Test status
Simulation time 160388175691 ps
CPU time 199.1 seconds
Started Jun 10 07:16:55 PM PDT 24
Finished Jun 10 07:20:20 PM PDT 24
Peak memory 201788 kb
Host smart-9ae73aeb-4806-43ca-9995-cf5b6501daa9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199266988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.3199266988
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.2215896727
Short name T283
Test name
Test status
Simulation time 330121230347 ps
CPU time 797 seconds
Started Jun 10 07:16:47 PM PDT 24
Finished Jun 10 07:30:07 PM PDT 24
Peak memory 201788 kb
Host smart-4a622b75-20ee-4686-b1a2-f60990941dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215896727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.2215896727
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.3461596928
Short name T766
Test name
Test status
Simulation time 161318301018 ps
CPU time 95.45 seconds
Started Jun 10 07:16:51 PM PDT 24
Finished Jun 10 07:18:33 PM PDT 24
Peak memory 201768 kb
Host smart-9d2501a3-fd65-4796-9180-e689036a4b77
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461596928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.3461596928
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.529253858
Short name T208
Test name
Test status
Simulation time 367913536467 ps
CPU time 245.75 seconds
Started Jun 10 07:16:56 PM PDT 24
Finished Jun 10 07:21:08 PM PDT 24
Peak memory 201800 kb
Host smart-22011439-f2ba-4d69-905c-09808627f39e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529253858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_
wakeup.529253858
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.2191580599
Short name T444
Test name
Test status
Simulation time 595124294536 ps
CPU time 687.56 seconds
Started Jun 10 07:16:52 PM PDT 24
Finished Jun 10 07:28:26 PM PDT 24
Peak memory 201876 kb
Host smart-cda23322-74cd-481e-9ea0-c805d14748f8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191580599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.2191580599
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.2080807744
Short name T69
Test name
Test status
Simulation time 119189871782 ps
CPU time 441.93 seconds
Started Jun 10 07:17:00 PM PDT 24
Finished Jun 10 07:24:29 PM PDT 24
Peak memory 202192 kb
Host smart-632725d7-a61c-466f-84c9-0d60bea051b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080807744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.2080807744
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.2051053380
Short name T603
Test name
Test status
Simulation time 40697547001 ps
CPU time 95.2 seconds
Started Jun 10 07:16:59 PM PDT 24
Finished Jun 10 07:18:41 PM PDT 24
Peak memory 201624 kb
Host smart-121fdd78-be8a-4f59-96cc-d0f3aef697b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051053380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.2051053380
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.3211495256
Short name T527
Test name
Test status
Simulation time 5317951494 ps
CPU time 5.8 seconds
Started Jun 10 07:16:56 PM PDT 24
Finished Jun 10 07:17:08 PM PDT 24
Peak memory 201596 kb
Host smart-96b16d4b-6788-41e2-9295-58bcb0e0a62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211495256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.3211495256
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.3058462389
Short name T378
Test name
Test status
Simulation time 5715539414 ps
CPU time 4.4 seconds
Started Jun 10 07:16:55 PM PDT 24
Finished Jun 10 07:17:06 PM PDT 24
Peak memory 201624 kb
Host smart-56fe26a6-c146-48d8-aab8-675a339f923b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058462389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.3058462389
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.3029477787
Short name T320
Test name
Test status
Simulation time 331699958326 ps
CPU time 110.48 seconds
Started Jun 10 07:17:05 PM PDT 24
Finished Jun 10 07:19:03 PM PDT 24
Peak memory 201876 kb
Host smart-eed505c5-a700-4f09-8a0a-f690c7631283
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029477787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.3029477787
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.3285913741
Short name T415
Test name
Test status
Simulation time 429259613 ps
CPU time 1.6 seconds
Started Jun 10 07:17:05 PM PDT 24
Finished Jun 10 07:17:13 PM PDT 24
Peak memory 201476 kb
Host smart-db632ac2-e263-46fc-9adc-bfc482800947
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285913741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.3285913741
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.4036803275
Short name T278
Test name
Test status
Simulation time 350648413569 ps
CPU time 521.01 seconds
Started Jun 10 07:17:08 PM PDT 24
Finished Jun 10 07:25:55 PM PDT 24
Peak memory 201796 kb
Host smart-fa773cd1-fc45-4e23-ac14-ffe8a75b5d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036803275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.4036803275
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.4030826518
Short name T219
Test name
Test status
Simulation time 486807581685 ps
CPU time 280.85 seconds
Started Jun 10 07:17:06 PM PDT 24
Finished Jun 10 07:21:54 PM PDT 24
Peak memory 201764 kb
Host smart-486561d0-683f-440f-ac80-d307f2881e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030826518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.4030826518
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.3315633255
Short name T742
Test name
Test status
Simulation time 333724481282 ps
CPU time 196.01 seconds
Started Jun 10 07:17:04 PM PDT 24
Finished Jun 10 07:20:27 PM PDT 24
Peak memory 201872 kb
Host smart-774b5999-a6d2-4b48-9875-e1a980c8e4af
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315633255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.3315633255
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.1697333128
Short name T478
Test name
Test status
Simulation time 497675555238 ps
CPU time 356.34 seconds
Started Jun 10 07:17:04 PM PDT 24
Finished Jun 10 07:23:08 PM PDT 24
Peak memory 201868 kb
Host smart-5d6eb8d1-a460-46c3-86e6-263c1977b1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697333128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.1697333128
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.1329762269
Short name T464
Test name
Test status
Simulation time 165944691319 ps
CPU time 394.69 seconds
Started Jun 10 07:17:04 PM PDT 24
Finished Jun 10 07:23:46 PM PDT 24
Peak memory 201852 kb
Host smart-8ac40dc7-a789-48f3-92b8-4a0c9b7dd592
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329762269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.1329762269
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.1573657063
Short name T176
Test name
Test status
Simulation time 438914059176 ps
CPU time 1040.08 seconds
Started Jun 10 07:17:03 PM PDT 24
Finished Jun 10 07:34:30 PM PDT 24
Peak memory 201844 kb
Host smart-c51ee71b-5e12-46b6-8602-dbbaab88ad94
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573657063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.1573657063
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.396849127
Short name T10
Test name
Test status
Simulation time 199972911008 ps
CPU time 64.46 seconds
Started Jun 10 07:17:04 PM PDT 24
Finished Jun 10 07:18:15 PM PDT 24
Peak memory 201816 kb
Host smart-27dbef61-257e-46cf-96c2-a4205a8ab1d6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396849127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
adc_ctrl_filters_wakeup_fixed.396849127
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.55993246
Short name T755
Test name
Test status
Simulation time 102805217517 ps
CPU time 557.76 seconds
Started Jun 10 07:17:04 PM PDT 24
Finished Jun 10 07:26:29 PM PDT 24
Peak memory 202064 kb
Host smart-e6386589-a952-43b5-8008-cc4b23b8677e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55993246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.55993246
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.3691812583
Short name T488
Test name
Test status
Simulation time 21730561942 ps
CPU time 13.15 seconds
Started Jun 10 07:17:10 PM PDT 24
Finished Jun 10 07:17:28 PM PDT 24
Peak memory 201624 kb
Host smart-7d25a146-f231-42ff-8a78-cce3624d0203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691812583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.3691812583
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.2523366589
Short name T557
Test name
Test status
Simulation time 4401338498 ps
CPU time 10.82 seconds
Started Jun 10 07:17:05 PM PDT 24
Finished Jun 10 07:17:23 PM PDT 24
Peak memory 201592 kb
Host smart-ee00dd7a-9cb3-46e7-b771-5ef92ad5414b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523366589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.2523366589
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.3854057461
Short name T483
Test name
Test status
Simulation time 5859110163 ps
CPU time 4.57 seconds
Started Jun 10 07:17:05 PM PDT 24
Finished Jun 10 07:17:16 PM PDT 24
Peak memory 201612 kb
Host smart-65f0ee3d-8d46-49ae-9cc4-b53149631544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854057461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.3854057461
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.1706194750
Short name T418
Test name
Test status
Simulation time 306666982 ps
CPU time 0.84 seconds
Started Jun 10 07:17:14 PM PDT 24
Finished Jun 10 07:17:19 PM PDT 24
Peak memory 201488 kb
Host smart-227a7081-bc13-48ed-b4d3-15ee4c5ce638
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706194750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.1706194750
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.3640010996
Short name T218
Test name
Test status
Simulation time 576324494462 ps
CPU time 328.51 seconds
Started Jun 10 07:17:06 PM PDT 24
Finished Jun 10 07:22:41 PM PDT 24
Peak memory 201776 kb
Host smart-384e2157-e832-456a-852b-89f8e61d3903
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640010996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.3640010996
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.1012306257
Short name T277
Test name
Test status
Simulation time 173583534821 ps
CPU time 412.64 seconds
Started Jun 10 07:17:05 PM PDT 24
Finished Jun 10 07:24:05 PM PDT 24
Peak memory 201804 kb
Host smart-68287253-9f50-43af-86a9-94b47a6faedc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012306257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.1012306257
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.1898884574
Short name T773
Test name
Test status
Simulation time 165093465180 ps
CPU time 383.72 seconds
Started Jun 10 07:17:04 PM PDT 24
Finished Jun 10 07:23:35 PM PDT 24
Peak memory 201808 kb
Host smart-2a090c35-6516-4800-8520-297744cbe603
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898884574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.1898884574
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.2087321797
Short name T43
Test name
Test status
Simulation time 330164658561 ps
CPU time 393.35 seconds
Started Jun 10 07:17:03 PM PDT 24
Finished Jun 10 07:23:43 PM PDT 24
Peak memory 201700 kb
Host smart-a6a5c4e0-abfb-44aa-9ce0-4a9c7eea7609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087321797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.2087321797
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.2244918642
Short name T643
Test name
Test status
Simulation time 332271732217 ps
CPU time 84.56 seconds
Started Jun 10 07:17:05 PM PDT 24
Finished Jun 10 07:18:37 PM PDT 24
Peak memory 201764 kb
Host smart-6c075cdb-3ac5-4a47-9cea-7ac370e8e55d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244918642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.2244918642
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.2198331409
Short name T328
Test name
Test status
Simulation time 520980429520 ps
CPU time 347.28 seconds
Started Jun 10 07:17:05 PM PDT 24
Finished Jun 10 07:23:00 PM PDT 24
Peak memory 201872 kb
Host smart-cdf6e70d-c3d8-44ee-9221-cb9469c110b8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198331409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.2198331409
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.1834725036
Short name T8
Test name
Test status
Simulation time 201952844843 ps
CPU time 209.84 seconds
Started Jun 10 07:17:04 PM PDT 24
Finished Jun 10 07:20:41 PM PDT 24
Peak memory 201860 kb
Host smart-c0c62faf-2d3b-4327-b290-4e23d58f4bf7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834725036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.1834725036
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.2541750861
Short name T237
Test name
Test status
Simulation time 124643723683 ps
CPU time 611.06 seconds
Started Jun 10 07:17:10 PM PDT 24
Finished Jun 10 07:27:26 PM PDT 24
Peak memory 202200 kb
Host smart-76d621f9-6e9a-4c30-9e3d-9d6d9232da24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541750861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.2541750861
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.3309897372
Short name T443
Test name
Test status
Simulation time 36302433310 ps
CPU time 42.46 seconds
Started Jun 10 07:17:06 PM PDT 24
Finished Jun 10 07:17:55 PM PDT 24
Peak memory 201596 kb
Host smart-0514d113-f43e-4dac-9cae-9d2cea4a0fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309897372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.3309897372
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.1578494086
Short name T44
Test name
Test status
Simulation time 3197146449 ps
CPU time 2.82 seconds
Started Jun 10 07:17:05 PM PDT 24
Finished Jun 10 07:17:15 PM PDT 24
Peak memory 201600 kb
Host smart-e4d43d86-a536-4867-85e8-20d2cca8ee18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578494086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.1578494086
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.2336753606
Short name T570
Test name
Test status
Simulation time 6138628294 ps
CPU time 3 seconds
Started Jun 10 07:17:04 PM PDT 24
Finished Jun 10 07:17:14 PM PDT 24
Peak memory 201628 kb
Host smart-1ef394ad-ef0d-425d-af72-7cf875f79f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336753606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.2336753606
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.944469432
Short name T275
Test name
Test status
Simulation time 570754515970 ps
CPU time 583.89 seconds
Started Jun 10 07:17:14 PM PDT 24
Finished Jun 10 07:27:02 PM PDT 24
Peak memory 202232 kb
Host smart-e201662a-14cc-4ccc-a1a1-044c1fa9bee9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944469432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all.
944469432
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.1397275139
Short name T62
Test name
Test status
Simulation time 343582925394 ps
CPU time 100.39 seconds
Started Jun 10 07:17:16 PM PDT 24
Finished Jun 10 07:19:00 PM PDT 24
Peak memory 210484 kb
Host smart-ba3d8577-d0a3-4e3f-987e-369cafff9521
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397275139 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.1397275139
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.347708618
Short name T468
Test name
Test status
Simulation time 427933176 ps
CPU time 0.99 seconds
Started Jun 10 07:17:22 PM PDT 24
Finished Jun 10 07:17:25 PM PDT 24
Peak memory 201492 kb
Host smart-378db5df-ae4e-4b62-b9a7-ddc273c834d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347708618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.347708618
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.138746209
Short name T335
Test name
Test status
Simulation time 543305986460 ps
CPU time 1313.94 seconds
Started Jun 10 07:17:14 PM PDT 24
Finished Jun 10 07:39:12 PM PDT 24
Peak memory 201784 kb
Host smart-9fe765cb-ca7f-49e2-8a55-4a318ba59466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138746209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.138746209
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.3599964876
Short name T419
Test name
Test status
Simulation time 499156846729 ps
CPU time 609.03 seconds
Started Jun 10 07:17:15 PM PDT 24
Finished Jun 10 07:27:28 PM PDT 24
Peak memory 201768 kb
Host smart-75b9d943-8ab6-45e6-8a9f-e9931d0f9265
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599964876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.3599964876
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.2718275451
Short name T329
Test name
Test status
Simulation time 170459962605 ps
CPU time 60.99 seconds
Started Jun 10 07:17:12 PM PDT 24
Finished Jun 10 07:18:18 PM PDT 24
Peak memory 201812 kb
Host smart-0d5edb4b-46b4-4897-867d-83c582ae3ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718275451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.2718275451
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.2156034777
Short name T693
Test name
Test status
Simulation time 168160540958 ps
CPU time 367.12 seconds
Started Jun 10 07:17:16 PM PDT 24
Finished Jun 10 07:23:27 PM PDT 24
Peak memory 201768 kb
Host smart-353f1779-f061-4eef-bdee-b8b59f66a1cb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156034777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.2156034777
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.634585496
Short name T788
Test name
Test status
Simulation time 375960466048 ps
CPU time 915.6 seconds
Started Jun 10 07:17:15 PM PDT 24
Finished Jun 10 07:32:35 PM PDT 24
Peak memory 201908 kb
Host smart-5e4f6253-f497-4e28-9a97-a8f22cde4354
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634585496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_
wakeup.634585496
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.1426392813
Short name T470
Test name
Test status
Simulation time 401890553064 ps
CPU time 230.5 seconds
Started Jun 10 07:17:12 PM PDT 24
Finished Jun 10 07:21:07 PM PDT 24
Peak memory 201884 kb
Host smart-4b08d751-c7c3-434f-8d96-f44088a32808
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426392813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.1426392813
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.3888242822
Short name T752
Test name
Test status
Simulation time 118308203026 ps
CPU time 502 seconds
Started Jun 10 07:17:21 PM PDT 24
Finished Jun 10 07:25:46 PM PDT 24
Peak memory 202116 kb
Host smart-06d1a38f-4c18-42be-b250-2e4cd7538b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888242822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.3888242822
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.2371863321
Short name T598
Test name
Test status
Simulation time 27038561709 ps
CPU time 30.86 seconds
Started Jun 10 07:17:21 PM PDT 24
Finished Jun 10 07:17:54 PM PDT 24
Peak memory 201656 kb
Host smart-27a30e4a-fc9b-49d8-a080-d45f7f7bafa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371863321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.2371863321
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.3769460585
Short name T115
Test name
Test status
Simulation time 4008253164 ps
CPU time 3.08 seconds
Started Jun 10 07:17:14 PM PDT 24
Finished Jun 10 07:17:21 PM PDT 24
Peak memory 201652 kb
Host smart-62cb6f24-7066-4a47-b1d8-182453c8d42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769460585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.3769460585
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.2137018028
Short name T564
Test name
Test status
Simulation time 5783949108 ps
CPU time 4.64 seconds
Started Jun 10 07:17:13 PM PDT 24
Finished Jun 10 07:17:22 PM PDT 24
Peak memory 201608 kb
Host smart-e5b03bc5-e77b-47e9-befd-6ac080e10b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137018028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.2137018028
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.2954672946
Short name T226
Test name
Test status
Simulation time 164087320984 ps
CPU time 89.71 seconds
Started Jun 10 07:17:21 PM PDT 24
Finished Jun 10 07:18:54 PM PDT 24
Peak memory 201892 kb
Host smart-8b8be737-7932-4d08-9d9a-c5987a49ff00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954672946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.2954672946
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.3688077250
Short name T32
Test name
Test status
Simulation time 65088514302 ps
CPU time 149.15 seconds
Started Jun 10 07:17:23 PM PDT 24
Finished Jun 10 07:19:55 PM PDT 24
Peak memory 210156 kb
Host smart-8add9ddb-3c24-4dac-bc00-f9a03e0e3d28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688077250 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.3688077250
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.1594511418
Short name T474
Test name
Test status
Simulation time 551396549 ps
CPU time 0.79 seconds
Started Jun 10 07:17:29 PM PDT 24
Finished Jun 10 07:17:31 PM PDT 24
Peak memory 201496 kb
Host smart-e835164d-ebaa-4cbb-b228-6420d74176d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594511418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.1594511418
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.2634265267
Short name T133
Test name
Test status
Simulation time 379823212611 ps
CPU time 476.65 seconds
Started Jun 10 07:17:25 PM PDT 24
Finished Jun 10 07:25:24 PM PDT 24
Peak memory 201860 kb
Host smart-f47b98c8-0f59-4f4e-b27b-78a37837496f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634265267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.2634265267
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.8352843
Short name T718
Test name
Test status
Simulation time 322766557147 ps
CPU time 138.42 seconds
Started Jun 10 07:17:21 PM PDT 24
Finished Jun 10 07:19:42 PM PDT 24
Peak memory 201724 kb
Host smart-287a92d9-ae22-4fe7-aff8-c1df94400b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8352843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.8352843
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.330809992
Short name T422
Test name
Test status
Simulation time 485889861613 ps
CPU time 557.16 seconds
Started Jun 10 07:17:22 PM PDT 24
Finished Jun 10 07:26:42 PM PDT 24
Peak memory 201840 kb
Host smart-1e6446ca-9a0b-4dba-8638-f649c893be0a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=330809992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrup
t_fixed.330809992
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.1074620453
Short name T792
Test name
Test status
Simulation time 323035981867 ps
CPU time 748.43 seconds
Started Jun 10 07:17:20 PM PDT 24
Finished Jun 10 07:29:51 PM PDT 24
Peak memory 201848 kb
Host smart-7bb5764f-f822-4a03-b9bd-08a7b8cb0ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074620453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.1074620453
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.675310806
Short name T549
Test name
Test status
Simulation time 163906115144 ps
CPU time 203.02 seconds
Started Jun 10 07:17:23 PM PDT 24
Finished Jun 10 07:20:48 PM PDT 24
Peak memory 201856 kb
Host smart-51e03c50-62f0-4c9d-8afd-e8ec77400597
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=675310806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fixe
d.675310806
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.505356228
Short name T665
Test name
Test status
Simulation time 362613021439 ps
CPU time 228.98 seconds
Started Jun 10 07:17:20 PM PDT 24
Finished Jun 10 07:21:11 PM PDT 24
Peak memory 201944 kb
Host smart-38cabfb1-7942-447e-843e-ca8f31832541
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505356228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_
wakeup.505356228
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.743372522
Short name T756
Test name
Test status
Simulation time 621666761480 ps
CPU time 498.76 seconds
Started Jun 10 07:17:20 PM PDT 24
Finished Jun 10 07:25:42 PM PDT 24
Peak memory 201840 kb
Host smart-f850a2c9-3f3b-46cf-95be-d6813f31277e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743372522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
adc_ctrl_filters_wakeup_fixed.743372522
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.2143322387
Short name T804
Test name
Test status
Simulation time 105220337749 ps
CPU time 345.21 seconds
Started Jun 10 07:17:20 PM PDT 24
Finished Jun 10 07:23:07 PM PDT 24
Peak memory 202192 kb
Host smart-3b0a621f-5390-40d0-86e5-112e5f7e8f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143322387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.2143322387
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.2883878758
Short name T520
Test name
Test status
Simulation time 34116814420 ps
CPU time 80.1 seconds
Started Jun 10 07:17:21 PM PDT 24
Finished Jun 10 07:18:44 PM PDT 24
Peak memory 201604 kb
Host smart-6d4db39f-5ddb-4d9c-95db-e8b75267cb78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883878758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.2883878758
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.1317942898
Short name T758
Test name
Test status
Simulation time 3441481398 ps
CPU time 1.96 seconds
Started Jun 10 07:17:21 PM PDT 24
Finished Jun 10 07:17:25 PM PDT 24
Peak memory 201596 kb
Host smart-025b477f-eb47-4b58-a776-b6e8c4255d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317942898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.1317942898
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.3516958971
Short name T391
Test name
Test status
Simulation time 5764085186 ps
CPU time 14.05 seconds
Started Jun 10 07:17:21 PM PDT 24
Finished Jun 10 07:17:37 PM PDT 24
Peak memory 201544 kb
Host smart-142d8654-178e-4ada-b118-d590ddeb4273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516958971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.3516958971
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.2579387679
Short name T48
Test name
Test status
Simulation time 119524194094 ps
CPU time 428.25 seconds
Started Jun 10 07:17:25 PM PDT 24
Finished Jun 10 07:24:35 PM PDT 24
Peak memory 202240 kb
Host smart-7fd37c5e-8d63-48e0-9d76-2b1367571a09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579387679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.2579387679
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.3997419883
Short name T541
Test name
Test status
Simulation time 309146821 ps
CPU time 1.33 seconds
Started Jun 10 07:17:37 PM PDT 24
Finished Jun 10 07:17:40 PM PDT 24
Peak memory 201464 kb
Host smart-7416da3b-fc75-43c0-9b73-e7160d21fb37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997419883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.3997419883
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.3639339572
Short name T245
Test name
Test status
Simulation time 167705479431 ps
CPU time 391.65 seconds
Started Jun 10 07:17:30 PM PDT 24
Finished Jun 10 07:24:03 PM PDT 24
Peak memory 201860 kb
Host smart-023383e5-b137-4023-8393-a4368e271c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639339572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.3639339572
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.1185318933
Short name T537
Test name
Test status
Simulation time 322930918246 ps
CPU time 633.97 seconds
Started Jun 10 07:17:30 PM PDT 24
Finished Jun 10 07:28:06 PM PDT 24
Peak memory 201792 kb
Host smart-eb43fa0d-8d5f-45ab-9226-f85585ba9416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185318933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.1185318933
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.705661293
Short name T38
Test name
Test status
Simulation time 487444556168 ps
CPU time 139.65 seconds
Started Jun 10 07:17:30 PM PDT 24
Finished Jun 10 07:19:51 PM PDT 24
Peak memory 201820 kb
Host smart-78b0e5fc-b36b-4d9a-8ce8-f82db4440158
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=705661293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrup
t_fixed.705661293
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.2776715803
Short name T346
Test name
Test status
Simulation time 500770885425 ps
CPU time 1210.21 seconds
Started Jun 10 07:17:31 PM PDT 24
Finished Jun 10 07:37:44 PM PDT 24
Peak memory 201864 kb
Host smart-27795cb1-1af4-4cea-94f3-077cf00acf8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776715803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.2776715803
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.3690098851
Short name T805
Test name
Test status
Simulation time 502805161147 ps
CPU time 1207.24 seconds
Started Jun 10 07:17:30 PM PDT 24
Finished Jun 10 07:37:39 PM PDT 24
Peak memory 201748 kb
Host smart-044acdd1-b308-42a7-8163-4afdd7154e9f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690098851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.3690098851
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.1798170120
Short name T296
Test name
Test status
Simulation time 331145101209 ps
CPU time 640.67 seconds
Started Jun 10 07:17:30 PM PDT 24
Finished Jun 10 07:28:12 PM PDT 24
Peak memory 201904 kb
Host smart-977b87ce-1d76-4a8d-a06d-a00f9c992506
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798170120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.1798170120
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.2215151137
Short name T795
Test name
Test status
Simulation time 616830153413 ps
CPU time 122.98 seconds
Started Jun 10 07:17:30 PM PDT 24
Finished Jun 10 07:19:35 PM PDT 24
Peak memory 201796 kb
Host smart-70e8c23d-826b-453a-910e-0f0961678192
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215151137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.2215151137
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.1345607185
Short name T122
Test name
Test status
Simulation time 126412676743 ps
CPU time 690.84 seconds
Started Jun 10 07:17:39 PM PDT 24
Finished Jun 10 07:29:11 PM PDT 24
Peak memory 202104 kb
Host smart-b848baf7-c797-4f9c-bb4e-7d17ba058dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345607185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.1345607185
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.3578249171
Short name T580
Test name
Test status
Simulation time 31067589081 ps
CPU time 39.39 seconds
Started Jun 10 07:17:39 PM PDT 24
Finished Jun 10 07:18:20 PM PDT 24
Peak memory 201604 kb
Host smart-a42d8e54-0231-4cf2-b1de-8659f16d4aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578249171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.3578249171
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.2204967139
Short name T656
Test name
Test status
Simulation time 3682088376 ps
CPU time 3.01 seconds
Started Jun 10 07:17:29 PM PDT 24
Finished Jun 10 07:17:33 PM PDT 24
Peak memory 201592 kb
Host smart-33649256-a2f0-41ea-8f45-4cf984730387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204967139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.2204967139
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.2932408469
Short name T582
Test name
Test status
Simulation time 5912586775 ps
CPU time 14.21 seconds
Started Jun 10 07:17:31 PM PDT 24
Finished Jun 10 07:17:48 PM PDT 24
Peak memory 201640 kb
Host smart-cc68864b-0e53-44ed-a9d7-06e25799423a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932408469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.2932408469
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.1356307397
Short name T671
Test name
Test status
Simulation time 355764891100 ps
CPU time 214.5 seconds
Started Jun 10 07:17:39 PM PDT 24
Finished Jun 10 07:21:15 PM PDT 24
Peak memory 201844 kb
Host smart-616c51d7-c937-4009-bc10-d9fca3e04043
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356307397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.1356307397
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.3587720355
Short name T529
Test name
Test status
Simulation time 524440678 ps
CPU time 1.45 seconds
Started Jun 10 07:17:55 PM PDT 24
Finished Jun 10 07:18:00 PM PDT 24
Peak memory 201468 kb
Host smart-2a18476f-a9e0-41ff-95af-aa7c518c93c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587720355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.3587720355
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.3766505252
Short name T624
Test name
Test status
Simulation time 181613365413 ps
CPU time 201.02 seconds
Started Jun 10 07:17:50 PM PDT 24
Finished Jun 10 07:21:14 PM PDT 24
Peak memory 201788 kb
Host smart-a68a7f47-50cd-4444-b15c-1055f0171671
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766505252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.3766505252
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.2296299524
Short name T737
Test name
Test status
Simulation time 172277635597 ps
CPU time 244.6 seconds
Started Jun 10 07:17:50 PM PDT 24
Finished Jun 10 07:21:57 PM PDT 24
Peak memory 201876 kb
Host smart-60a3bf24-4e00-43c5-9b72-5732d56815dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296299524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.2296299524
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.1498235362
Short name T31
Test name
Test status
Simulation time 493399822086 ps
CPU time 589.27 seconds
Started Jun 10 07:17:50 PM PDT 24
Finished Jun 10 07:27:42 PM PDT 24
Peak memory 201752 kb
Host smart-a1dd13d5-6df2-46d3-b57f-727c271bde6d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498235362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.1498235362
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.515942376
Short name T509
Test name
Test status
Simulation time 168348971027 ps
CPU time 194.24 seconds
Started Jun 10 07:17:38 PM PDT 24
Finished Jun 10 07:20:54 PM PDT 24
Peak memory 201884 kb
Host smart-4648a1e6-7732-4080-9332-e11cfdea3b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515942376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.515942376
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.1521579157
Short name T794
Test name
Test status
Simulation time 484885753977 ps
CPU time 1011.88 seconds
Started Jun 10 07:17:40 PM PDT 24
Finished Jun 10 07:34:35 PM PDT 24
Peak memory 201764 kb
Host smart-4c016563-5efb-4172-abab-3fe46edca6c4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521579157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.1521579157
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.2281606499
Short name T784
Test name
Test status
Simulation time 392703394523 ps
CPU time 216.52 seconds
Started Jun 10 07:17:48 PM PDT 24
Finished Jun 10 07:21:27 PM PDT 24
Peak memory 201952 kb
Host smart-cc8fb8da-1d8b-4443-be81-e8e1e75fd0f3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281606499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.2281606499
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.2764715579
Short name T515
Test name
Test status
Simulation time 31034096874 ps
CPU time 40.54 seconds
Started Jun 10 07:17:56 PM PDT 24
Finished Jun 10 07:18:40 PM PDT 24
Peak memory 201560 kb
Host smart-9d293a97-cfe6-4a45-aa6b-2d9326ae48fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764715579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.2764715579
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.153929728
Short name T597
Test name
Test status
Simulation time 5418805254 ps
CPU time 7.61 seconds
Started Jun 10 07:17:47 PM PDT 24
Finished Jun 10 07:17:58 PM PDT 24
Peak memory 201592 kb
Host smart-d4c8fc93-b2c0-4f5c-9cd4-7462425352fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153929728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.153929728
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.2203945734
Short name T622
Test name
Test status
Simulation time 5668206889 ps
CPU time 3.23 seconds
Started Jun 10 07:17:38 PM PDT 24
Finished Jun 10 07:17:43 PM PDT 24
Peak memory 201612 kb
Host smart-8237a239-4329-4be5-b2df-b9ab4eaee021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203945734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.2203945734
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.1730223931
Short name T317
Test name
Test status
Simulation time 216992184594 ps
CPU time 127.35 seconds
Started Jun 10 07:17:55 PM PDT 24
Finished Jun 10 07:20:05 PM PDT 24
Peak memory 201804 kb
Host smart-e49bd23d-548e-4cff-9f12-6e2a4f6448a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730223931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.1730223931
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.675555004
Short name T727
Test name
Test status
Simulation time 183009595920 ps
CPU time 47.27 seconds
Started Jun 10 07:17:55 PM PDT 24
Finished Jun 10 07:18:46 PM PDT 24
Peak memory 210104 kb
Host smart-b7f9d5e3-c446-4462-a220-7c3fc1ad00d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675555004 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.675555004
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.2666644625
Short name T799
Test name
Test status
Simulation time 380411246 ps
CPU time 1.51 seconds
Started Jun 10 07:18:07 PM PDT 24
Finished Jun 10 07:18:11 PM PDT 24
Peak memory 201484 kb
Host smart-9091ab85-f18c-411e-b8e7-f521a0f0c635
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666644625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.2666644625
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.440200034
Short name T248
Test name
Test status
Simulation time 175935085982 ps
CPU time 428.33 seconds
Started Jun 10 07:18:08 PM PDT 24
Finished Jun 10 07:25:18 PM PDT 24
Peak memory 201884 kb
Host smart-2af7eabf-56cf-424d-a49c-f569809d8b72
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440200034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gati
ng.440200034
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.3616506744
Short name T322
Test name
Test status
Simulation time 492104538588 ps
CPU time 80.75 seconds
Started Jun 10 07:17:56 PM PDT 24
Finished Jun 10 07:19:20 PM PDT 24
Peak memory 201784 kb
Host smart-2a8921f4-53a6-4621-975b-d41cf673578c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616506744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.3616506744
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.196244181
Short name T376
Test name
Test status
Simulation time 332357557976 ps
CPU time 416.09 seconds
Started Jun 10 07:17:55 PM PDT 24
Finished Jun 10 07:24:55 PM PDT 24
Peak memory 201796 kb
Host smart-20ec28a8-6af6-4d84-a3a6-d75a6660334d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=196244181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrup
t_fixed.196244181
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.1378149108
Short name T177
Test name
Test status
Simulation time 489970835577 ps
CPU time 129.1 seconds
Started Jun 10 07:17:56 PM PDT 24
Finished Jun 10 07:20:08 PM PDT 24
Peak memory 201860 kb
Host smart-5eda0eb8-c6ea-415d-8cc3-53984bad5fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378149108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.1378149108
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.2688990331
Short name T28
Test name
Test status
Simulation time 166506639117 ps
CPU time 100.37 seconds
Started Jun 10 07:17:55 PM PDT 24
Finished Jun 10 07:19:39 PM PDT 24
Peak memory 201748 kb
Host smart-a668222a-118e-4a2a-9a7f-38168ef1b8e8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688990331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.2688990331
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.2336121858
Short name T775
Test name
Test status
Simulation time 369290544031 ps
CPU time 79.17 seconds
Started Jun 10 07:18:07 PM PDT 24
Finished Jun 10 07:19:27 PM PDT 24
Peak memory 201776 kb
Host smart-03880f6c-2aea-43b4-ac91-99b912eea882
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336121858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.2336121858
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.2494087148
Short name T65
Test name
Test status
Simulation time 609583817899 ps
CPU time 359.11 seconds
Started Jun 10 07:18:07 PM PDT 24
Finished Jun 10 07:24:08 PM PDT 24
Peak memory 201788 kb
Host smart-0bc65bd6-ab63-4e5e-b527-9e07e6449606
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494087148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.2494087148
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.1223881789
Short name T641
Test name
Test status
Simulation time 94300056771 ps
CPU time 520.47 seconds
Started Jun 10 07:18:07 PM PDT 24
Finished Jun 10 07:26:49 PM PDT 24
Peak memory 202192 kb
Host smart-e724cbfe-9719-4c3a-9e84-ecf033cff8bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223881789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.1223881789
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.614792727
Short name T709
Test name
Test status
Simulation time 45009141965 ps
CPU time 115.1 seconds
Started Jun 10 07:18:06 PM PDT 24
Finished Jun 10 07:20:03 PM PDT 24
Peak memory 201628 kb
Host smart-73b8668a-ed08-4753-84e3-2a1de113cb4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614792727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.614792727
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.3798666839
Short name T566
Test name
Test status
Simulation time 5259285323 ps
CPU time 4.54 seconds
Started Jun 10 07:18:08 PM PDT 24
Finished Jun 10 07:18:14 PM PDT 24
Peak memory 201616 kb
Host smart-69fc3a17-088a-471e-8c04-f0f22511fc00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798666839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.3798666839
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.4116522231
Short name T390
Test name
Test status
Simulation time 5910705040 ps
CPU time 15.15 seconds
Started Jun 10 07:17:56 PM PDT 24
Finished Jun 10 07:18:15 PM PDT 24
Peak memory 201624 kb
Host smart-9f7b0f1d-ea1e-414d-84af-1dc1c6ed40a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116522231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.4116522231
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.1365158939
Short name T644
Test name
Test status
Simulation time 366939627716 ps
CPU time 924.48 seconds
Started Jun 10 07:18:08 PM PDT 24
Finished Jun 10 07:33:34 PM PDT 24
Peak memory 201784 kb
Host smart-8aa11862-90a9-4384-83da-6175345021c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365158939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.1365158939
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.3454846670
Short name T400
Test name
Test status
Simulation time 305479914 ps
CPU time 1.37 seconds
Started Jun 10 07:16:27 PM PDT 24
Finished Jun 10 07:16:33 PM PDT 24
Peak memory 201436 kb
Host smart-23665a6c-9407-451c-b53b-3c05d23ab443
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454846670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.3454846670
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.3692551267
Short name T807
Test name
Test status
Simulation time 195094823633 ps
CPU time 105.64 seconds
Started Jun 10 07:16:29 PM PDT 24
Finished Jun 10 07:18:19 PM PDT 24
Peak memory 201776 kb
Host smart-0c107f4e-b45c-4d30-921c-0e01f35c8b14
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692551267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.3692551267
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.3372803258
Short name T276
Test name
Test status
Simulation time 510908558065 ps
CPU time 331.71 seconds
Started Jun 10 07:16:27 PM PDT 24
Finished Jun 10 07:22:03 PM PDT 24
Peak memory 201752 kb
Host smart-f76325bf-f0af-4a0c-a58a-4dce18e8e19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372803258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.3372803258
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.2836979609
Short name T607
Test name
Test status
Simulation time 336852767738 ps
CPU time 233.61 seconds
Started Jun 10 07:16:20 PM PDT 24
Finished Jun 10 07:20:17 PM PDT 24
Peak memory 201888 kb
Host smart-e29d5ce1-16e6-4cab-b711-8eff8957faeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836979609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.2836979609
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.2043000771
Short name T389
Test name
Test status
Simulation time 493603014066 ps
CPU time 303.71 seconds
Started Jun 10 07:16:24 PM PDT 24
Finished Jun 10 07:21:31 PM PDT 24
Peak memory 201764 kb
Host smart-30efab6e-9805-41fa-9892-23f21d435da2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043000771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.2043000771
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.3797355179
Short name T197
Test name
Test status
Simulation time 488332906591 ps
CPU time 175.86 seconds
Started Jun 10 07:16:19 PM PDT 24
Finished Jun 10 07:19:18 PM PDT 24
Peak memory 201908 kb
Host smart-1ac5f742-9a3c-44d7-9957-13e80c213c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797355179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.3797355179
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.2406235001
Short name T590
Test name
Test status
Simulation time 327267231886 ps
CPU time 810.36 seconds
Started Jun 10 07:16:20 PM PDT 24
Finished Jun 10 07:29:54 PM PDT 24
Peak memory 201796 kb
Host smart-0d0904be-dd81-48a3-b236-8a17b3b3f7d1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406235001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.2406235001
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.679307525
Short name T136
Test name
Test status
Simulation time 198263445339 ps
CPU time 234.39 seconds
Started Jun 10 07:16:27 PM PDT 24
Finished Jun 10 07:20:26 PM PDT 24
Peak memory 201788 kb
Host smart-106f9c98-b62c-4ac9-8691-1f22c2d9346f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679307525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.a
dc_ctrl_filters_wakeup_fixed.679307525
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.95867029
Short name T691
Test name
Test status
Simulation time 87268847290 ps
CPU time 305.78 seconds
Started Jun 10 07:16:28 PM PDT 24
Finished Jun 10 07:21:39 PM PDT 24
Peak memory 202084 kb
Host smart-7f2524dd-b175-406c-b158-4df54b0cf5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95867029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.95867029
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.510781948
Short name T635
Test name
Test status
Simulation time 34128736711 ps
CPU time 20.14 seconds
Started Jun 10 07:16:26 PM PDT 24
Finished Jun 10 07:16:51 PM PDT 24
Peak memory 201616 kb
Host smart-12a65c28-e5e8-46bb-8be9-0144436e6de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510781948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.510781948
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.3539897343
Short name T496
Test name
Test status
Simulation time 3049851907 ps
CPU time 3.27 seconds
Started Jun 10 07:16:27 PM PDT 24
Finished Jun 10 07:16:36 PM PDT 24
Peak memory 201536 kb
Host smart-48d40f35-95b1-49e7-a6e3-18f595bd61ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539897343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.3539897343
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.3943849770
Short name T104
Test name
Test status
Simulation time 8019929540 ps
CPU time 5.57 seconds
Started Jun 10 07:16:27 PM PDT 24
Finished Jun 10 07:16:37 PM PDT 24
Peak memory 217344 kb
Host smart-049abf63-3cfe-445b-8423-305f2429cff9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943849770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.3943849770
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.2365991121
Short name T404
Test name
Test status
Simulation time 5842409023 ps
CPU time 16.69 seconds
Started Jun 10 07:16:20 PM PDT 24
Finished Jun 10 07:16:40 PM PDT 24
Peak memory 201648 kb
Host smart-5ce42fa6-1173-45c4-bcbf-57510199db74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365991121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.2365991121
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.306313159
Short name T362
Test name
Test status
Simulation time 84472535361 ps
CPU time 309.19 seconds
Started Jun 10 07:16:27 PM PDT 24
Finished Jun 10 07:21:41 PM PDT 24
Peak memory 217936 kb
Host smart-a1b070ce-4804-47de-aba1-3a84479d6d56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306313159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.306313159
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.1120048136
Short name T357
Test name
Test status
Simulation time 152585058208 ps
CPU time 145.92 seconds
Started Jun 10 07:16:27 PM PDT 24
Finished Jun 10 07:18:58 PM PDT 24
Peak memory 216276 kb
Host smart-7acfddab-7785-45c7-8c2f-8e799ca8494c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120048136 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.1120048136
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.1543519027
Short name T765
Test name
Test status
Simulation time 368234956 ps
CPU time 1.47 seconds
Started Jun 10 07:18:19 PM PDT 24
Finished Jun 10 07:18:24 PM PDT 24
Peak memory 201472 kb
Host smart-49896b56-a994-4ee9-8e70-7cccb424c2b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543519027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.1543519027
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.2150345719
Short name T732
Test name
Test status
Simulation time 338871964258 ps
CPU time 325.7 seconds
Started Jun 10 07:18:17 PM PDT 24
Finished Jun 10 07:23:45 PM PDT 24
Peak memory 201868 kb
Host smart-6075fb5d-085f-4d65-83b1-a6bd878618f0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150345719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.2150345719
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.3072673033
Short name T355
Test name
Test status
Simulation time 198701171077 ps
CPU time 510.6 seconds
Started Jun 10 07:18:20 PM PDT 24
Finished Jun 10 07:26:54 PM PDT 24
Peak memory 201792 kb
Host smart-8d8b3436-4873-4df3-97d0-226fbf3e5eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072673033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.3072673033
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.2664376725
Short name T715
Test name
Test status
Simulation time 156361747607 ps
CPU time 362.23 seconds
Started Jun 10 07:18:15 PM PDT 24
Finished Jun 10 07:24:19 PM PDT 24
Peak memory 201812 kb
Host smart-c46b85af-99c6-49ba-a33f-3c72698bf940
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664376725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.2664376725
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.473733447
Short name T57
Test name
Test status
Simulation time 488332265964 ps
CPU time 72.35 seconds
Started Jun 10 07:18:15 PM PDT 24
Finished Jun 10 07:19:29 PM PDT 24
Peak memory 201748 kb
Host smart-5447fd7e-005a-44dc-9e89-fef4d3659559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473733447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.473733447
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.10458538
Short name T780
Test name
Test status
Simulation time 488113356950 ps
CPU time 179.99 seconds
Started Jun 10 07:18:17 PM PDT 24
Finished Jun 10 07:21:19 PM PDT 24
Peak memory 201776 kb
Host smart-b33fd9c7-7d48-4d97-b6a4-039c0d0027f5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=10458538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fixed
.10458538
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.3084653258
Short name T196
Test name
Test status
Simulation time 539869712614 ps
CPU time 342.54 seconds
Started Jun 10 07:18:17 PM PDT 24
Finished Jun 10 07:24:02 PM PDT 24
Peak memory 201848 kb
Host smart-f3511089-fd5f-4b48-b8bc-972451ec35df
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084653258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.3084653258
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.3442285612
Short name T490
Test name
Test status
Simulation time 406096199548 ps
CPU time 251.83 seconds
Started Jun 10 07:18:19 PM PDT 24
Finished Jun 10 07:22:34 PM PDT 24
Peak memory 201800 kb
Host smart-5b62a686-eb79-4961-a3d5-b5fbbb5ab301
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442285612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.3442285612
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.1500805386
Short name T763
Test name
Test status
Simulation time 119157222543 ps
CPU time 483.77 seconds
Started Jun 10 07:18:14 PM PDT 24
Finished Jun 10 07:26:20 PM PDT 24
Peak memory 202184 kb
Host smart-35c1699d-c75f-484d-9089-e39f37182c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500805386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.1500805386
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.1012158132
Short name T704
Test name
Test status
Simulation time 28177283425 ps
CPU time 60.61 seconds
Started Jun 10 07:18:16 PM PDT 24
Finished Jun 10 07:19:19 PM PDT 24
Peak memory 201596 kb
Host smart-9ad3e8a0-d648-4f33-b555-2ff39c85e981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012158132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.1012158132
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.2786744664
Short name T712
Test name
Test status
Simulation time 3407079162 ps
CPU time 2.43 seconds
Started Jun 10 07:18:16 PM PDT 24
Finished Jun 10 07:18:20 PM PDT 24
Peak memory 201628 kb
Host smart-e627a290-d06e-450a-bc6d-9f1d878ec391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786744664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.2786744664
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.729867767
Short name T681
Test name
Test status
Simulation time 5914573759 ps
CPU time 3.65 seconds
Started Jun 10 07:18:06 PM PDT 24
Finished Jun 10 07:18:12 PM PDT 24
Peak memory 201640 kb
Host smart-c5108809-74bd-42c7-aabd-ea0bcd4cf492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729867767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.729867767
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.3057084590
Short name T291
Test name
Test status
Simulation time 680316889202 ps
CPU time 755.8 seconds
Started Jun 10 07:18:16 PM PDT 24
Finished Jun 10 07:30:54 PM PDT 24
Peak memory 201788 kb
Host smart-784a9882-521e-40d5-af0f-b4138323c09e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057084590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.3057084590
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.3449780014
Short name T116
Test name
Test status
Simulation time 177350267271 ps
CPU time 128.97 seconds
Started Jun 10 07:18:15 PM PDT 24
Finished Jun 10 07:20:26 PM PDT 24
Peak memory 210092 kb
Host smart-dce6ff1a-f545-4041-9847-91f39af56b62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449780014 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.3449780014
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.3783449802
Short name T736
Test name
Test status
Simulation time 316813332 ps
CPU time 1.35 seconds
Started Jun 10 07:18:34 PM PDT 24
Finished Jun 10 07:18:37 PM PDT 24
Peak memory 201464 kb
Host smart-20568586-6ac7-47e1-959b-61ae01e19c9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783449802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.3783449802
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.1559118684
Short name T664
Test name
Test status
Simulation time 165699984702 ps
CPU time 104.14 seconds
Started Jun 10 07:18:34 PM PDT 24
Finished Jun 10 07:20:21 PM PDT 24
Peak memory 201748 kb
Host smart-92482be1-6367-4452-a6c5-09f3b77c3f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559118684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.1559118684
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.1195824594
Short name T172
Test name
Test status
Simulation time 478594599543 ps
CPU time 1078.39 seconds
Started Jun 10 07:18:25 PM PDT 24
Finished Jun 10 07:36:28 PM PDT 24
Peak memory 201752 kb
Host smart-2a898b8d-8171-4485-b9ee-35ff8ea654c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195824594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.1195824594
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.3626905207
Short name T426
Test name
Test status
Simulation time 500599501563 ps
CPU time 316.68 seconds
Started Jun 10 07:18:25 PM PDT 24
Finished Jun 10 07:23:45 PM PDT 24
Peak memory 201720 kb
Host smart-2875d068-f6e4-40c7-aeec-57bd63ee1502
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626905207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.3626905207
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.233408716
Short name T3
Test name
Test status
Simulation time 168507311263 ps
CPU time 360.57 seconds
Started Jun 10 07:18:26 PM PDT 24
Finished Jun 10 07:24:31 PM PDT 24
Peak memory 201776 kb
Host smart-58392824-d998-42fa-8fa2-af39983e8948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233408716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.233408716
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.2484224915
Short name T567
Test name
Test status
Simulation time 173339668352 ps
CPU time 98.91 seconds
Started Jun 10 07:18:25 PM PDT 24
Finished Jun 10 07:20:07 PM PDT 24
Peak memory 201800 kb
Host smart-079a71c3-3ea4-42be-8fa2-6e9892142b20
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484224915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.2484224915
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.922765053
Short name T323
Test name
Test status
Simulation time 652155801370 ps
CPU time 1527.87 seconds
Started Jun 10 07:18:24 PM PDT 24
Finished Jun 10 07:43:56 PM PDT 24
Peak memory 201872 kb
Host smart-0872af43-ee8f-4aaf-8a38-f0da6add2857
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922765053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_
wakeup.922765053
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.2347829523
Short name T542
Test name
Test status
Simulation time 411139021461 ps
CPU time 449.62 seconds
Started Jun 10 07:18:23 PM PDT 24
Finished Jun 10 07:25:57 PM PDT 24
Peak memory 201828 kb
Host smart-e65c63b0-466d-456b-8ac0-f210c42bf167
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347829523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.2347829523
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.263461995
Short name T70
Test name
Test status
Simulation time 89548239267 ps
CPU time 495.59 seconds
Started Jun 10 07:18:33 PM PDT 24
Finished Jun 10 07:26:51 PM PDT 24
Peak memory 202124 kb
Host smart-385ae4bf-21e4-42c0-a57f-f6627fb0400c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263461995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.263461995
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.834725708
Short name T578
Test name
Test status
Simulation time 22748494999 ps
CPU time 14.24 seconds
Started Jun 10 07:18:33 PM PDT 24
Finished Jun 10 07:18:50 PM PDT 24
Peak memory 201648 kb
Host smart-4f604b48-f610-489a-9806-0240e84ce770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834725708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.834725708
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.3125364725
Short name T427
Test name
Test status
Simulation time 4631583186 ps
CPU time 3.37 seconds
Started Jun 10 07:18:33 PM PDT 24
Finished Jun 10 07:18:39 PM PDT 24
Peak memory 201628 kb
Host smart-f28da418-303d-4df1-b3f2-882ce6304dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125364725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.3125364725
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.3505811344
Short name T110
Test name
Test status
Simulation time 6005309092 ps
CPU time 15.31 seconds
Started Jun 10 07:18:26 PM PDT 24
Finished Jun 10 07:18:46 PM PDT 24
Peak memory 201620 kb
Host smart-361f6813-17f8-4eec-bfb2-c65184e53abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505811344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.3505811344
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.1473960651
Short name T613
Test name
Test status
Simulation time 103951702974 ps
CPU time 503.86 seconds
Started Jun 10 07:18:33 PM PDT 24
Finished Jun 10 07:26:59 PM PDT 24
Peak memory 202180 kb
Host smart-513e188d-cd08-4430-ab08-2a0ca35fcb30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473960651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.1473960651
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.2282885130
Short name T46
Test name
Test status
Simulation time 225806184342 ps
CPU time 176.23 seconds
Started Jun 10 07:18:32 PM PDT 24
Finished Jun 10 07:21:31 PM PDT 24
Peak memory 210396 kb
Host smart-9e9df358-988b-4c5a-b057-ab6b6f478a71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282885130 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.2282885130
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.3939532929
Short name T610
Test name
Test status
Simulation time 339684013 ps
CPU time 1.33 seconds
Started Jun 10 07:18:49 PM PDT 24
Finished Jun 10 07:18:52 PM PDT 24
Peak memory 201496 kb
Host smart-de7b5454-a7cd-4a7c-bcf1-da7c0ce11567
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939532929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.3939532929
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.917484545
Short name T457
Test name
Test status
Simulation time 455088696379 ps
CPU time 295.01 seconds
Started Jun 10 07:18:43 PM PDT 24
Finished Jun 10 07:23:40 PM PDT 24
Peak memory 201808 kb
Host smart-a005f610-1690-49e9-845d-f49337cc7f6d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917484545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gati
ng.917484545
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.3794235806
Short name T674
Test name
Test status
Simulation time 405518057355 ps
CPU time 975.56 seconds
Started Jun 10 07:18:40 PM PDT 24
Finished Jun 10 07:34:56 PM PDT 24
Peak memory 201788 kb
Host smart-e2a2be90-8379-48b0-a9c9-8effdc875be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794235806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.3794235806
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.124323659
Short name T684
Test name
Test status
Simulation time 325392376581 ps
CPU time 95.04 seconds
Started Jun 10 07:18:42 PM PDT 24
Finished Jun 10 07:20:19 PM PDT 24
Peak memory 201796 kb
Host smart-d6e73c20-8339-4d5f-9109-52f7c3378a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124323659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.124323659
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.615565813
Short name T628
Test name
Test status
Simulation time 332202407766 ps
CPU time 728.54 seconds
Started Jun 10 07:18:43 PM PDT 24
Finished Jun 10 07:30:54 PM PDT 24
Peak memory 201788 kb
Host smart-e868e78e-443c-47b4-a377-c1e285b2a992
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=615565813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrup
t_fixed.615565813
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.3763277187
Short name T730
Test name
Test status
Simulation time 480952278234 ps
CPU time 538.1 seconds
Started Jun 10 07:18:33 PM PDT 24
Finished Jun 10 07:27:34 PM PDT 24
Peak memory 201912 kb
Host smart-eb14a05c-c6bb-4b11-96e9-24fd3510d10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763277187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.3763277187
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.2808616785
Short name T414
Test name
Test status
Simulation time 161467081660 ps
CPU time 102.81 seconds
Started Jun 10 07:18:39 PM PDT 24
Finished Jun 10 07:20:23 PM PDT 24
Peak memory 201800 kb
Host smart-d2764c74-c0f2-4b14-acf4-18c988e3f88e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808616785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.2808616785
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.1245472262
Short name T334
Test name
Test status
Simulation time 367474900366 ps
CPU time 882.78 seconds
Started Jun 10 07:18:44 PM PDT 24
Finished Jun 10 07:33:29 PM PDT 24
Peak memory 201860 kb
Host smart-ab41bc91-7173-4017-b4ee-348fbdc68ed6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245472262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.1245472262
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.2332712510
Short name T212
Test name
Test status
Simulation time 211627666159 ps
CPU time 53.46 seconds
Started Jun 10 07:18:44 PM PDT 24
Finished Jun 10 07:19:40 PM PDT 24
Peak memory 201804 kb
Host smart-bb243d0e-2e39-458c-b7dc-5144b6f1aa86
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332712510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.2332712510
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.938080198
Short name T502
Test name
Test status
Simulation time 98855770509 ps
CPU time 528.65 seconds
Started Jun 10 07:18:50 PM PDT 24
Finished Jun 10 07:27:40 PM PDT 24
Peak memory 202176 kb
Host smart-8a4b4b8c-1dd9-4535-bec0-091387fce1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938080198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.938080198
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.77661649
Short name T673
Test name
Test status
Simulation time 40365629210 ps
CPU time 45.4 seconds
Started Jun 10 07:18:48 PM PDT 24
Finished Jun 10 07:19:35 PM PDT 24
Peak memory 201564 kb
Host smart-25b47fdf-28a6-4eca-8a59-5ea664999a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77661649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.77661649
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.2495964864
Short name T370
Test name
Test status
Simulation time 4719196909 ps
CPU time 3.36 seconds
Started Jun 10 07:18:48 PM PDT 24
Finished Jun 10 07:18:53 PM PDT 24
Peak memory 201624 kb
Host smart-1d59144e-a6fd-489e-9195-c2b0eb966bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495964864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.2495964864
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.3012096652
Short name T518
Test name
Test status
Simulation time 6063325992 ps
CPU time 4.88 seconds
Started Jun 10 07:18:32 PM PDT 24
Finished Jun 10 07:18:39 PM PDT 24
Peak memory 201644 kb
Host smart-ac0ca637-d4a2-43a4-9ab6-dd57d7d239e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012096652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.3012096652
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.940139297
Short name T289
Test name
Test status
Simulation time 341425862827 ps
CPU time 57.47 seconds
Started Jun 10 07:18:49 PM PDT 24
Finished Jun 10 07:19:48 PM PDT 24
Peak memory 201904 kb
Host smart-ce1b1500-528b-420e-86f0-163c72cf4098
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940139297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all.
940139297
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.1797499058
Short name T41
Test name
Test status
Simulation time 541943284 ps
CPU time 0.94 seconds
Started Jun 10 07:19:04 PM PDT 24
Finished Jun 10 07:19:08 PM PDT 24
Peak memory 201484 kb
Host smart-efd103f8-1f25-4ad4-b3b6-430d9abe4f6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797499058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.1797499058
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.638807005
Short name T341
Test name
Test status
Simulation time 537242276168 ps
CPU time 1360.3 seconds
Started Jun 10 07:18:57 PM PDT 24
Finished Jun 10 07:41:39 PM PDT 24
Peak memory 201796 kb
Host smart-ad4f3d44-227e-418f-9360-4fcceee14184
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638807005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gati
ng.638807005
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.3127724072
Short name T290
Test name
Test status
Simulation time 167214843379 ps
CPU time 408.44 seconds
Started Jun 10 07:18:57 PM PDT 24
Finished Jun 10 07:25:47 PM PDT 24
Peak memory 201820 kb
Host smart-0a6396c2-cbb0-4654-85b2-09e606e3c884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127724072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.3127724072
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.325473197
Short name T514
Test name
Test status
Simulation time 159105112880 ps
CPU time 101.49 seconds
Started Jun 10 07:18:57 PM PDT 24
Finished Jun 10 07:20:40 PM PDT 24
Peak memory 201744 kb
Host smart-855537fd-e23b-472c-b632-e76d53ddcfc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325473197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.325473197
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.877156619
Short name T714
Test name
Test status
Simulation time 166058625261 ps
CPU time 331.84 seconds
Started Jun 10 07:18:58 PM PDT 24
Finished Jun 10 07:24:32 PM PDT 24
Peak memory 201800 kb
Host smart-a827d5f6-e677-499a-9ebf-f135c7288ed5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=877156619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrup
t_fixed.877156619
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.1219092043
Short name T195
Test name
Test status
Simulation time 325012876438 ps
CPU time 122.28 seconds
Started Jun 10 07:18:56 PM PDT 24
Finished Jun 10 07:21:00 PM PDT 24
Peak memory 201812 kb
Host smart-288d082c-2205-474e-b6c4-666f8a5987e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219092043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.1219092043
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.334235887
Short name T728
Test name
Test status
Simulation time 163476149688 ps
CPU time 94.56 seconds
Started Jun 10 07:18:56 PM PDT 24
Finished Jun 10 07:20:33 PM PDT 24
Peak memory 201792 kb
Host smart-3dd8dc62-0aff-4b89-851a-ecc7bac3e41c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=334235887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fixe
d.334235887
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.3495951884
Short name T184
Test name
Test status
Simulation time 366562557481 ps
CPU time 113.73 seconds
Started Jun 10 07:18:57 PM PDT 24
Finished Jun 10 07:20:52 PM PDT 24
Peak memory 201764 kb
Host smart-033ef2e1-26bc-4d2a-ac1e-afdbdb08b5ad
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495951884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.3495951884
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.1079855865
Short name T193
Test name
Test status
Simulation time 604804227148 ps
CPU time 404.57 seconds
Started Jun 10 07:18:57 PM PDT 24
Finished Jun 10 07:25:43 PM PDT 24
Peak memory 201784 kb
Host smart-5564973d-5d80-4435-9172-7bb9216dfc34
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079855865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.1079855865
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.3876026641
Short name T679
Test name
Test status
Simulation time 83044342436 ps
CPU time 343.54 seconds
Started Jun 10 07:19:05 PM PDT 24
Finished Jun 10 07:24:52 PM PDT 24
Peak memory 202084 kb
Host smart-41cfe52a-5ef0-41ef-8d5f-509a445abc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876026641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.3876026641
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.3937095405
Short name T469
Test name
Test status
Simulation time 44664570144 ps
CPU time 20.71 seconds
Started Jun 10 07:19:05 PM PDT 24
Finished Jun 10 07:19:28 PM PDT 24
Peak memory 201592 kb
Host smart-e10f217a-2dbc-49a8-bce2-8aa6ef19616c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937095405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.3937095405
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.631051185
Short name T682
Test name
Test status
Simulation time 4064143118 ps
CPU time 3.27 seconds
Started Jun 10 07:19:06 PM PDT 24
Finished Jun 10 07:19:12 PM PDT 24
Peak memory 201580 kb
Host smart-899c5727-e048-4cb5-a6d8-3fff62c05c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631051185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.631051185
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.1527620088
Short name T654
Test name
Test status
Simulation time 5668942067 ps
CPU time 3.04 seconds
Started Jun 10 07:18:48 PM PDT 24
Finished Jun 10 07:18:52 PM PDT 24
Peak memory 201632 kb
Host smart-1dcbfdc9-6dd0-4c67-b0c1-18f08c2bfd6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527620088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.1527620088
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.3668691833
Short name T721
Test name
Test status
Simulation time 364021980887 ps
CPU time 908.69 seconds
Started Jun 10 07:19:06 PM PDT 24
Finished Jun 10 07:34:18 PM PDT 24
Peak memory 201820 kb
Host smart-56c8acad-d777-4e7e-8054-4ac728229206
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668691833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.3668691833
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.1177912772
Short name T710
Test name
Test status
Simulation time 216120157437 ps
CPU time 220.76 seconds
Started Jun 10 07:19:03 PM PDT 24
Finished Jun 10 07:22:46 PM PDT 24
Peak memory 210416 kb
Host smart-79729f5f-dafa-4f43-a9b2-adc2822a0795
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177912772 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.1177912772
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.817531196
Short name T575
Test name
Test status
Simulation time 502148543 ps
CPU time 0.93 seconds
Started Jun 10 07:19:29 PM PDT 24
Finished Jun 10 07:19:32 PM PDT 24
Peak memory 201484 kb
Host smart-70995cd0-616c-4e60-9703-dc508fade3fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817531196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.817531196
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.4026985707
Short name T354
Test name
Test status
Simulation time 514254993014 ps
CPU time 1266.2 seconds
Started Jun 10 07:19:22 PM PDT 24
Finished Jun 10 07:40:31 PM PDT 24
Peak memory 201820 kb
Host smart-646921a8-c9dd-448a-8e30-f51f57d373db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026985707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.4026985707
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.2916750734
Short name T271
Test name
Test status
Simulation time 332899759853 ps
CPU time 411.6 seconds
Started Jun 10 07:19:04 PM PDT 24
Finished Jun 10 07:25:59 PM PDT 24
Peak memory 201868 kb
Host smart-7e43e9c4-74f2-43e3-8fb0-0d63de5d519a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916750734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.2916750734
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.1815351591
Short name T772
Test name
Test status
Simulation time 163698263058 ps
CPU time 374.04 seconds
Started Jun 10 07:19:05 PM PDT 24
Finished Jun 10 07:25:22 PM PDT 24
Peak memory 201792 kb
Host smart-a6669464-b2cb-41ca-8d6d-e70c109d8e28
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815351591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.1815351591
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.387966616
Short name T550
Test name
Test status
Simulation time 488777496808 ps
CPU time 396.88 seconds
Started Jun 10 07:19:04 PM PDT 24
Finished Jun 10 07:25:44 PM PDT 24
Peak memory 201888 kb
Host smart-9687b557-f546-48ba-a6bb-d3e722742e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387966616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.387966616
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.38675612
Short name T185
Test name
Test status
Simulation time 501953140284 ps
CPU time 98.66 seconds
Started Jun 10 07:19:07 PM PDT 24
Finished Jun 10 07:20:49 PM PDT 24
Peak memory 201772 kb
Host smart-0defe7a6-c2eb-4516-99a1-cd975d3a7bf5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=38675612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fixed
.38675612
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.200239247
Short name T720
Test name
Test status
Simulation time 487213635105 ps
CPU time 1109.63 seconds
Started Jun 10 07:19:27 PM PDT 24
Finished Jun 10 07:37:58 PM PDT 24
Peak memory 201760 kb
Host smart-f62c8fb0-71e7-4eaf-a9a3-5fe3c936a6b6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200239247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_
wakeup.200239247
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.728045857
Short name T29
Test name
Test status
Simulation time 199191588190 ps
CPU time 50.48 seconds
Started Jun 10 07:19:20 PM PDT 24
Finished Jun 10 07:20:14 PM PDT 24
Peak memory 201796 kb
Host smart-db0b28f1-181d-4b16-a3f4-ef5ccaceadbc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728045857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
adc_ctrl_filters_wakeup_fixed.728045857
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.2939630525
Short name T229
Test name
Test status
Simulation time 87441206501 ps
CPU time 439.99 seconds
Started Jun 10 07:19:22 PM PDT 24
Finished Jun 10 07:26:44 PM PDT 24
Peak memory 202120 kb
Host smart-de8ad603-0d6a-4f70-8935-d9321355940e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939630525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.2939630525
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.1055301407
Short name T440
Test name
Test status
Simulation time 32211360347 ps
CPU time 38.18 seconds
Started Jun 10 07:19:23 PM PDT 24
Finished Jun 10 07:20:04 PM PDT 24
Peak memory 201604 kb
Host smart-7da29f0e-7f96-47b0-9f65-9d65db516ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055301407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.1055301407
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.633709937
Short name T439
Test name
Test status
Simulation time 5124701579 ps
CPU time 11.75 seconds
Started Jun 10 07:19:21 PM PDT 24
Finished Jun 10 07:19:36 PM PDT 24
Peak memory 201620 kb
Host smart-7dab91a2-ea51-40f0-b5c0-875c323dfe9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633709937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.633709937
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.473265328
Short name T500
Test name
Test status
Simulation time 5785633831 ps
CPU time 12.91 seconds
Started Jun 10 07:19:05 PM PDT 24
Finished Jun 10 07:19:20 PM PDT 24
Peak memory 201464 kb
Host smart-555efd58-9da5-41f8-bd5a-f2aa3055dc9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473265328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.473265328
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.404190180
Short name T34
Test name
Test status
Simulation time 231890652720 ps
CPU time 478.23 seconds
Started Jun 10 07:19:22 PM PDT 24
Finished Jun 10 07:27:23 PM PDT 24
Peak memory 201852 kb
Host smart-94383081-3fb0-48f0-b403-46ca74783b32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404190180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all.
404190180
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.2679736388
Short name T114
Test name
Test status
Simulation time 505310499 ps
CPU time 0.9 seconds
Started Jun 10 07:19:38 PM PDT 24
Finished Jun 10 07:19:40 PM PDT 24
Peak memory 201484 kb
Host smart-8e148fd8-6a26-4abe-b2ef-5b15fd7ee02a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679736388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.2679736388
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.3040681767
Short name T66
Test name
Test status
Simulation time 162611549994 ps
CPU time 93.9 seconds
Started Jun 10 07:19:31 PM PDT 24
Finished Jun 10 07:21:07 PM PDT 24
Peak memory 201804 kb
Host smart-ca840fd1-0e12-429a-8e22-efed774324d7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040681767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.3040681767
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.1730875099
Short name T194
Test name
Test status
Simulation time 344319504934 ps
CPU time 163.33 seconds
Started Jun 10 07:19:34 PM PDT 24
Finished Jun 10 07:22:20 PM PDT 24
Peak memory 201860 kb
Host smart-96d3b16b-3b02-415e-baf7-53afa4acc435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730875099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.1730875099
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.3005141746
Short name T309
Test name
Test status
Simulation time 327655823408 ps
CPU time 779.29 seconds
Started Jun 10 07:19:30 PM PDT 24
Finished Jun 10 07:32:32 PM PDT 24
Peak memory 201792 kb
Host smart-6aac61c2-2acb-4898-8839-2ab1441a0124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005141746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.3005141746
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.3176846281
Short name T466
Test name
Test status
Simulation time 161945545095 ps
CPU time 31.78 seconds
Started Jun 10 07:19:31 PM PDT 24
Finished Jun 10 07:20:05 PM PDT 24
Peak memory 201908 kb
Host smart-d9c3461b-df0c-4a78-988b-3f199ee432c7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176846281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.3176846281
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.1896835912
Short name T747
Test name
Test status
Simulation time 165357169116 ps
CPU time 91.44 seconds
Started Jun 10 07:19:31 PM PDT 24
Finished Jun 10 07:21:05 PM PDT 24
Peak memory 201804 kb
Host smart-0fd92e5d-a328-4024-8ad8-0487626dc345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896835912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.1896835912
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.175910404
Short name T702
Test name
Test status
Simulation time 324288687725 ps
CPU time 193.26 seconds
Started Jun 10 07:19:30 PM PDT 24
Finished Jun 10 07:22:46 PM PDT 24
Peak memory 201820 kb
Host smart-54def5be-3670-4f7f-9362-71c41d9c5cbe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=175910404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fixe
d.175910404
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.1474453081
Short name T216
Test name
Test status
Simulation time 373803000930 ps
CPU time 209.23 seconds
Started Jun 10 07:19:31 PM PDT 24
Finished Jun 10 07:23:03 PM PDT 24
Peak memory 201760 kb
Host smart-0382ee2c-24e5-4d60-b871-ae41f2886840
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474453081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.1474453081
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.1196639009
Short name T692
Test name
Test status
Simulation time 602160248005 ps
CPU time 681.14 seconds
Started Jun 10 07:19:31 PM PDT 24
Finished Jun 10 07:30:55 PM PDT 24
Peak memory 201828 kb
Host smart-ea8e78df-deef-48ef-be31-7cd228e99107
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196639009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.1196639009
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.1770278364
Short name T213
Test name
Test status
Simulation time 141940861230 ps
CPU time 735.15 seconds
Started Jun 10 07:19:40 PM PDT 24
Finished Jun 10 07:31:57 PM PDT 24
Peak memory 202176 kb
Host smart-1b34fc2e-8179-4773-bc31-5cd4029436da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770278364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.1770278364
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.2872230839
Short name T722
Test name
Test status
Simulation time 36421675355 ps
CPU time 41.97 seconds
Started Jun 10 07:19:39 PM PDT 24
Finished Jun 10 07:20:23 PM PDT 24
Peak memory 201644 kb
Host smart-8bdce02b-11a3-4b88-8258-1959036ccf7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872230839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.2872230839
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.2203190737
Short name T494
Test name
Test status
Simulation time 5175109995 ps
CPU time 7 seconds
Started Jun 10 07:19:32 PM PDT 24
Finished Jun 10 07:19:41 PM PDT 24
Peak memory 201628 kb
Host smart-c28d3c49-abcd-46fa-91fc-86390e9f1168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203190737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.2203190737
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.2753036745
Short name T678
Test name
Test status
Simulation time 5965879476 ps
CPU time 14.32 seconds
Started Jun 10 07:19:30 PM PDT 24
Finished Jun 10 07:19:47 PM PDT 24
Peak memory 201624 kb
Host smart-2df4d32d-8047-4005-89e7-1c6bc3db98c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753036745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.2753036745
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.2240766362
Short name T648
Test name
Test status
Simulation time 177279282658 ps
CPU time 352.8 seconds
Started Jun 10 07:19:40 PM PDT 24
Finished Jun 10 07:25:36 PM PDT 24
Peak memory 201784 kb
Host smart-e20e2253-4c34-4fec-b1cf-60d062c287a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240766362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.2240766362
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.1694022030
Short name T333
Test name
Test status
Simulation time 27495300275 ps
CPU time 62.33 seconds
Started Jun 10 07:19:37 PM PDT 24
Finished Jun 10 07:20:41 PM PDT 24
Peak memory 210412 kb
Host smart-4a78e1ce-76de-4761-a56c-6c4f1411f4ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694022030 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.1694022030
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.2052471599
Short name T553
Test name
Test status
Simulation time 372609026 ps
CPU time 1.52 seconds
Started Jun 10 07:19:55 PM PDT 24
Finished Jun 10 07:19:58 PM PDT 24
Peak memory 201468 kb
Host smart-5a606e84-62c5-4bda-a05c-0a797b1f85cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052471599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.2052471599
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.2592489959
Short name T285
Test name
Test status
Simulation time 160274404603 ps
CPU time 380.45 seconds
Started Jun 10 07:19:51 PM PDT 24
Finished Jun 10 07:26:13 PM PDT 24
Peak memory 201884 kb
Host smart-4f728fbc-70f8-4cad-9518-42562bfa9256
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592489959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.2592489959
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.3261898184
Short name T625
Test name
Test status
Simulation time 191766847587 ps
CPU time 116.87 seconds
Started Jun 10 07:19:51 PM PDT 24
Finished Jun 10 07:21:49 PM PDT 24
Peak memory 201824 kb
Host smart-53eee3b0-02c1-4f97-8bcb-60867c67bf23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261898184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.3261898184
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.933764651
Short name T525
Test name
Test status
Simulation time 166451835462 ps
CPU time 90.7 seconds
Started Jun 10 07:19:40 PM PDT 24
Finished Jun 10 07:21:13 PM PDT 24
Peak memory 201780 kb
Host smart-5febdd9a-41da-4b00-8181-10824face9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933764651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.933764651
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.2997844569
Short name T571
Test name
Test status
Simulation time 165952511555 ps
CPU time 370.3 seconds
Started Jun 10 07:19:36 PM PDT 24
Finished Jun 10 07:25:48 PM PDT 24
Peak memory 201736 kb
Host smart-179e18ac-c12c-4f0f-8184-66888dba6027
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997844569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.2997844569
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.3387927133
Short name T170
Test name
Test status
Simulation time 487065617052 ps
CPU time 579.61 seconds
Started Jun 10 07:19:39 PM PDT 24
Finished Jun 10 07:29:20 PM PDT 24
Peak memory 201888 kb
Host smart-4605ffdd-f80a-431b-9984-7b4480e36a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387927133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.3387927133
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.4071737839
Short name T716
Test name
Test status
Simulation time 162353181831 ps
CPU time 382.14 seconds
Started Jun 10 07:19:39 PM PDT 24
Finished Jun 10 07:26:03 PM PDT 24
Peak memory 201756 kb
Host smart-7baf820d-f5c8-409f-a9c4-9f6c591fe2c5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071737839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.4071737839
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.684317097
Short name T689
Test name
Test status
Simulation time 193366425008 ps
CPU time 403.58 seconds
Started Jun 10 07:19:51 PM PDT 24
Finished Jun 10 07:26:36 PM PDT 24
Peak memory 201984 kb
Host smart-32682c71-162c-4da0-a19f-e6cfb0758ad8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684317097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_
wakeup.684317097
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.2755098051
Short name T658
Test name
Test status
Simulation time 202596457630 ps
CPU time 258.78 seconds
Started Jun 10 07:19:51 PM PDT 24
Finished Jun 10 07:24:11 PM PDT 24
Peak memory 201792 kb
Host smart-c3a885bd-a38b-4e1b-b910-a0adcfe0fe99
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755098051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.2755098051
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.1560683509
Short name T783
Test name
Test status
Simulation time 133086696777 ps
CPU time 721.73 seconds
Started Jun 10 07:19:51 PM PDT 24
Finished Jun 10 07:31:54 PM PDT 24
Peak memory 202168 kb
Host smart-62cb3db3-e7b1-43e4-acd9-c122d5f3c285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560683509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.1560683509
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.2953061344
Short name T168
Test name
Test status
Simulation time 28445071497 ps
CPU time 69.49 seconds
Started Jun 10 07:19:51 PM PDT 24
Finished Jun 10 07:21:02 PM PDT 24
Peak memory 201656 kb
Host smart-f242e26d-725d-478c-9302-4ca45bff1397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953061344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.2953061344
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.3781429190
Short name T662
Test name
Test status
Simulation time 3709756961 ps
CPU time 2.95 seconds
Started Jun 10 07:19:49 PM PDT 24
Finished Jun 10 07:19:54 PM PDT 24
Peak memory 201616 kb
Host smart-2dba1f87-8e11-4f54-85f6-82f85a9b7f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781429190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.3781429190
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.3692454630
Short name T401
Test name
Test status
Simulation time 5613356335 ps
CPU time 5.45 seconds
Started Jun 10 07:19:38 PM PDT 24
Finished Jun 10 07:19:45 PM PDT 24
Peak memory 201724 kb
Host smart-875d2ab7-0768-494d-b1b5-453011676093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692454630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.3692454630
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.694579964
Short name T431
Test name
Test status
Simulation time 6479384478 ps
CPU time 16.62 seconds
Started Jun 10 07:20:04 PM PDT 24
Finished Jun 10 07:20:22 PM PDT 24
Peak memory 201608 kb
Host smart-91b94350-ab80-4ffe-b072-7e88171b154b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694579964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all.
694579964
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.3800440505
Short name T572
Test name
Test status
Simulation time 549178229 ps
CPU time 1.16 seconds
Started Jun 10 07:20:26 PM PDT 24
Finished Jun 10 07:20:29 PM PDT 24
Peak memory 201464 kb
Host smart-85cd6d44-318f-4848-adee-e843a0a61207
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800440505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.3800440505
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.2973740689
Short name T166
Test name
Test status
Simulation time 337832342283 ps
CPU time 87.34 seconds
Started Jun 10 07:20:03 PM PDT 24
Finished Jun 10 07:21:32 PM PDT 24
Peak memory 201856 kb
Host smart-53ec2cb5-92c4-442c-a712-1a5cef9d5722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973740689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.2973740689
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.1399666608
Short name T207
Test name
Test status
Simulation time 322164365957 ps
CPU time 169.66 seconds
Started Jun 10 07:20:09 PM PDT 24
Finished Jun 10 07:22:59 PM PDT 24
Peak memory 201896 kb
Host smart-ced76093-0716-4f83-b207-25b71edb5dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399666608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.1399666608
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.1725475959
Short name T774
Test name
Test status
Simulation time 318209608528 ps
CPU time 387.7 seconds
Started Jun 10 07:20:03 PM PDT 24
Finished Jun 10 07:26:32 PM PDT 24
Peak memory 201968 kb
Host smart-d8bbf357-12ed-4e85-8cc6-519a66b81417
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725475959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.1725475959
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.1265210810
Short name T487
Test name
Test status
Simulation time 164947351481 ps
CPU time 59.76 seconds
Started Jun 10 07:20:02 PM PDT 24
Finished Jun 10 07:21:03 PM PDT 24
Peak memory 201832 kb
Host smart-b2986bae-9fb7-49eb-8ce2-96076216675a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265210810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.1265210810
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.3888906431
Short name T374
Test name
Test status
Simulation time 161234912729 ps
CPU time 54.32 seconds
Started Jun 10 07:20:03 PM PDT 24
Finished Jun 10 07:20:59 PM PDT 24
Peak memory 201772 kb
Host smart-dd73cc49-9498-46d7-828f-e8893a833a97
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888906431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.3888906431
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.3824621924
Short name T108
Test name
Test status
Simulation time 459965798982 ps
CPU time 224.1 seconds
Started Jun 10 07:20:02 PM PDT 24
Finished Jun 10 07:23:47 PM PDT 24
Peak memory 201756 kb
Host smart-80de0be8-8b76-4f92-bf5e-0b0be3222125
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824621924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.3824621924
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.1146856515
Short name T620
Test name
Test status
Simulation time 206661406000 ps
CPU time 122.81 seconds
Started Jun 10 07:20:02 PM PDT 24
Finished Jun 10 07:22:06 PM PDT 24
Peak memory 201792 kb
Host smart-25c0e4a8-55a9-422b-a6c1-792abe131571
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146856515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.1146856515
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.1719119825
Short name T417
Test name
Test status
Simulation time 74701962451 ps
CPU time 399.56 seconds
Started Jun 10 07:20:08 PM PDT 24
Finished Jun 10 07:26:49 PM PDT 24
Peak memory 202128 kb
Host smart-51bff64f-7bf2-4da4-b281-82ac4d935d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719119825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.1719119825
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.2047515796
Short name T448
Test name
Test status
Simulation time 35483636622 ps
CPU time 22.95 seconds
Started Jun 10 07:20:04 PM PDT 24
Finished Jun 10 07:20:28 PM PDT 24
Peak memory 201572 kb
Host smart-56cd9d20-c62b-4f9a-ae54-351a76925714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047515796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.2047515796
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.670771101
Short name T379
Test name
Test status
Simulation time 2945722479 ps
CPU time 7.14 seconds
Started Jun 10 07:20:04 PM PDT 24
Finished Jun 10 07:20:12 PM PDT 24
Peak memory 201452 kb
Host smart-68e8d5d1-44e9-4100-96d2-b4843f359e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670771101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.670771101
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.3472917100
Short name T617
Test name
Test status
Simulation time 5762483425 ps
CPU time 4.55 seconds
Started Jun 10 07:20:08 PM PDT 24
Finished Jun 10 07:20:14 PM PDT 24
Peak memory 201648 kb
Host smart-cde76d85-b085-4454-883b-f9cb4bdf96ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472917100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.3472917100
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.762865180
Short name T279
Test name
Test status
Simulation time 178343708970 ps
CPU time 109.81 seconds
Started Jun 10 07:20:25 PM PDT 24
Finished Jun 10 07:22:17 PM PDT 24
Peak memory 201804 kb
Host smart-6717c0be-9b22-4768-9dc0-243bc5d21940
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762865180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all.
762865180
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.1693740485
Short name T700
Test name
Test status
Simulation time 49603335600 ps
CPU time 108.22 seconds
Started Jun 10 07:20:26 PM PDT 24
Finished Jun 10 07:22:16 PM PDT 24
Peak memory 201888 kb
Host smart-600cdfc8-8dc1-4cf1-8c9c-d9c0438ca105
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693740485 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.1693740485
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.2022141142
Short name T652
Test name
Test status
Simulation time 477674441 ps
CPU time 0.73 seconds
Started Jun 10 07:20:34 PM PDT 24
Finished Jun 10 07:20:37 PM PDT 24
Peak memory 201496 kb
Host smart-28370804-cd67-4c84-804e-e6b8e457f01e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022141142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.2022141142
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.1740757700
Short name T546
Test name
Test status
Simulation time 176454020218 ps
CPU time 99.22 seconds
Started Jun 10 07:20:27 PM PDT 24
Finished Jun 10 07:22:07 PM PDT 24
Peak memory 201900 kb
Host smart-5d885a02-3911-41bc-98ac-3271e4975d61
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740757700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.1740757700
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.294831675
Short name T198
Test name
Test status
Simulation time 325871861486 ps
CPU time 408.63 seconds
Started Jun 10 07:20:27 PM PDT 24
Finished Jun 10 07:27:17 PM PDT 24
Peak memory 201796 kb
Host smart-718b9d78-04bc-445a-934d-9f097b63037a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294831675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.294831675
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.3692586695
Short name T432
Test name
Test status
Simulation time 158896832984 ps
CPU time 103.68 seconds
Started Jun 10 07:20:27 PM PDT 24
Finished Jun 10 07:22:12 PM PDT 24
Peak memory 201896 kb
Host smart-ce30d84c-dad3-4dae-a913-7386863d6458
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692586695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.3692586695
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.223433359
Short name T402
Test name
Test status
Simulation time 166230966626 ps
CPU time 101.64 seconds
Started Jun 10 07:20:26 PM PDT 24
Finished Jun 10 07:22:09 PM PDT 24
Peak memory 201828 kb
Host smart-8f59dab5-e18f-4c54-82fd-7f6852c4da01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223433359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.223433359
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.3334946072
Short name T666
Test name
Test status
Simulation time 328878747930 ps
CPU time 213.43 seconds
Started Jun 10 07:20:26 PM PDT 24
Finished Jun 10 07:24:01 PM PDT 24
Peak memory 201780 kb
Host smart-d52738b5-a2fe-4355-8779-2b5f93e03257
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334946072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.3334946072
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.3832562422
Short name T685
Test name
Test status
Simulation time 615000177639 ps
CPU time 705.25 seconds
Started Jun 10 07:20:25 PM PDT 24
Finished Jun 10 07:32:13 PM PDT 24
Peak memory 201868 kb
Host smart-aac13871-ee4f-4e33-9163-a16bba30062f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832562422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.3832562422
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.3892367586
Short name T11
Test name
Test status
Simulation time 118803606697 ps
CPU time 661.55 seconds
Started Jun 10 07:20:36 PM PDT 24
Finished Jun 10 07:31:39 PM PDT 24
Peak memory 202124 kb
Host smart-355ef7d5-9658-4c35-bd27-f002d0e420c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892367586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.3892367586
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.3051705148
Short name T492
Test name
Test status
Simulation time 33253125290 ps
CPU time 18.86 seconds
Started Jun 10 07:20:34 PM PDT 24
Finished Jun 10 07:20:55 PM PDT 24
Peak memory 201612 kb
Host smart-564491d1-9c51-47a4-a93f-e3a2a2dc1a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051705148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.3051705148
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.2614291025
Short name T371
Test name
Test status
Simulation time 2720293954 ps
CPU time 2.4 seconds
Started Jun 10 07:20:37 PM PDT 24
Finished Jun 10 07:20:41 PM PDT 24
Peak memory 201544 kb
Host smart-8c8096ce-563a-4128-a49f-ae3f991a1078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614291025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.2614291025
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.897050114
Short name T456
Test name
Test status
Simulation time 6091333498 ps
CPU time 4.47 seconds
Started Jun 10 07:20:25 PM PDT 24
Finished Jun 10 07:20:31 PM PDT 24
Peak memory 201648 kb
Host smart-d7b301f1-4b92-4ef2-8bf8-945a3d904e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897050114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.897050114
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.1470899589
Short name T750
Test name
Test status
Simulation time 442167760855 ps
CPU time 693.41 seconds
Started Jun 10 07:20:35 PM PDT 24
Finished Jun 10 07:32:10 PM PDT 24
Peak memory 210480 kb
Host smart-09a1705d-29c9-4dbb-b3ff-4814a2c52c6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470899589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.1470899589
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.2668944742
Short name T398
Test name
Test status
Simulation time 390072693 ps
CPU time 1.39 seconds
Started Jun 10 07:20:44 PM PDT 24
Finished Jun 10 07:20:47 PM PDT 24
Peak memory 201464 kb
Host smart-32589f20-6c16-4780-b861-adc321b35234
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668944742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.2668944742
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.381663975
Short name T299
Test name
Test status
Simulation time 166632002184 ps
CPU time 59.39 seconds
Started Jun 10 07:20:34 PM PDT 24
Finished Jun 10 07:21:36 PM PDT 24
Peak memory 201928 kb
Host smart-9a560d16-2718-49f1-9bdf-0c56e8f59f93
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381663975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gati
ng.381663975
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.849521394
Short name T340
Test name
Test status
Simulation time 498789397159 ps
CPU time 1139.76 seconds
Started Jun 10 07:20:36 PM PDT 24
Finished Jun 10 07:39:38 PM PDT 24
Peak memory 201784 kb
Host smart-0b84e6ec-ba87-41b7-baad-e0628386c8c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849521394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.849521394
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.157356111
Short name T726
Test name
Test status
Simulation time 327211678415 ps
CPU time 381.76 seconds
Started Jun 10 07:20:35 PM PDT 24
Finished Jun 10 07:26:59 PM PDT 24
Peak memory 201860 kb
Host smart-d4527fcc-8717-4719-99ed-1735d2c48e18
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=157356111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrup
t_fixed.157356111
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.2173817156
Short name T262
Test name
Test status
Simulation time 162732259102 ps
CPU time 97.43 seconds
Started Jun 10 07:20:39 PM PDT 24
Finished Jun 10 07:22:18 PM PDT 24
Peak memory 201724 kb
Host smart-6813d0b9-1fc3-41e8-9f6a-6f317177d0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173817156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.2173817156
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.3460407948
Short name T135
Test name
Test status
Simulation time 173964838259 ps
CPU time 383.2 seconds
Started Jun 10 07:20:37 PM PDT 24
Finished Jun 10 07:27:02 PM PDT 24
Peak memory 201792 kb
Host smart-ed7771c6-465d-46b8-a3da-10705adfc452
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460407948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.3460407948
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.70406356
Short name T803
Test name
Test status
Simulation time 350735753036 ps
CPU time 402.39 seconds
Started Jun 10 07:20:35 PM PDT 24
Finished Jun 10 07:27:20 PM PDT 24
Peak memory 201796 kb
Host smart-6c7743af-608b-4110-9793-619e3801ba3e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70406356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_w
akeup.70406356
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.3543444354
Short name T127
Test name
Test status
Simulation time 201415044412 ps
CPU time 129 seconds
Started Jun 10 07:20:43 PM PDT 24
Finished Jun 10 07:22:53 PM PDT 24
Peak memory 201776 kb
Host smart-a387d07b-d798-4454-bc37-a44f51d9ce5e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543444354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.3543444354
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.2960621586
Short name T793
Test name
Test status
Simulation time 85459986831 ps
CPU time 321.35 seconds
Started Jun 10 07:20:38 PM PDT 24
Finished Jun 10 07:26:01 PM PDT 24
Peak memory 202148 kb
Host smart-66397040-46d1-4ab3-8509-ed4aade69741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960621586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.2960621586
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.4207009630
Short name T558
Test name
Test status
Simulation time 35680104510 ps
CPU time 9.66 seconds
Started Jun 10 07:20:36 PM PDT 24
Finished Jun 10 07:20:48 PM PDT 24
Peak memory 201624 kb
Host smart-7c27515b-1c67-4d50-b3a3-0ee8de1a20c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207009630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.4207009630
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.3181146089
Short name T111
Test name
Test status
Simulation time 2781873066 ps
CPU time 7.71 seconds
Started Jun 10 07:20:34 PM PDT 24
Finished Jun 10 07:20:44 PM PDT 24
Peak memory 201624 kb
Host smart-207c9741-b34c-432d-9e78-047a8e236f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181146089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.3181146089
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.1404291274
Short name T25
Test name
Test status
Simulation time 5724156247 ps
CPU time 15.16 seconds
Started Jun 10 07:20:35 PM PDT 24
Finished Jun 10 07:20:52 PM PDT 24
Peak memory 201612 kb
Host smart-b37906f0-e598-4406-8a48-6dfad96e67ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404291274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.1404291274
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.2748371230
Short name T183
Test name
Test status
Simulation time 485187437325 ps
CPU time 472.44 seconds
Started Jun 10 07:20:36 PM PDT 24
Finished Jun 10 07:28:30 PM PDT 24
Peak memory 210304 kb
Host smart-0c258b7e-2ef3-44c0-b921-77e338c184e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748371230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.2748371230
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.1088636464
Short name T23
Test name
Test status
Simulation time 338654227373 ps
CPU time 192.24 seconds
Started Jun 10 07:20:44 PM PDT 24
Finished Jun 10 07:23:57 PM PDT 24
Peak memory 218076 kb
Host smart-b6c14f10-ab12-4475-88ed-243a88a7ac22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088636464 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.1088636464
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.1573847595
Short name T366
Test name
Test status
Simulation time 448955498 ps
CPU time 1.57 seconds
Started Jun 10 07:16:28 PM PDT 24
Finished Jun 10 07:16:35 PM PDT 24
Peak memory 201472 kb
Host smart-48873cd9-305f-4873-9287-5f5072deccba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573847595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.1573847595
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.917185968
Short name T642
Test name
Test status
Simulation time 165122014799 ps
CPU time 223.44 seconds
Started Jun 10 07:16:27 PM PDT 24
Finished Jun 10 07:20:16 PM PDT 24
Peak memory 201868 kb
Host smart-8de930ca-6882-4ab9-817d-8fee22b7e98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917185968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.917185968
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.2157148930
Short name T786
Test name
Test status
Simulation time 326451970256 ps
CPU time 809.75 seconds
Started Jun 10 07:16:29 PM PDT 24
Finished Jun 10 07:30:04 PM PDT 24
Peak memory 201784 kb
Host smart-cbe501cb-1217-47f6-b633-f02c3e56c741
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157148930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.2157148930
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.3527172985
Short name T797
Test name
Test status
Simulation time 326447716203 ps
CPU time 211.98 seconds
Started Jun 10 07:16:27 PM PDT 24
Finished Jun 10 07:20:04 PM PDT 24
Peak memory 201736 kb
Host smart-8d391f9b-ceb1-4d3a-92d0-e2008cef0646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527172985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.3527172985
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.1546708718
Short name T790
Test name
Test status
Simulation time 323593434025 ps
CPU time 355.93 seconds
Started Jun 10 07:16:27 PM PDT 24
Finished Jun 10 07:22:28 PM PDT 24
Peak memory 201836 kb
Host smart-89495b79-8a0b-49b3-8121-1f55bd3a2743
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546708718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.1546708718
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.3931016356
Short name T173
Test name
Test status
Simulation time 619884459357 ps
CPU time 379.9 seconds
Started Jun 10 07:16:27 PM PDT 24
Finished Jun 10 07:22:52 PM PDT 24
Peak memory 201804 kb
Host smart-5d44edcd-fcf9-45d7-9a4d-39ea242170f4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931016356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.3931016356
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.1419638814
Short name T369
Test name
Test status
Simulation time 199987369697 ps
CPU time 447.23 seconds
Started Jun 10 07:16:27 PM PDT 24
Finished Jun 10 07:23:59 PM PDT 24
Peak memory 201868 kb
Host smart-6df3212e-4389-4273-8fa6-9216a68b620e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419638814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.1419638814
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.1627149095
Short name T363
Test name
Test status
Simulation time 100220596835 ps
CPU time 399.59 seconds
Started Jun 10 07:16:26 PM PDT 24
Finished Jun 10 07:23:10 PM PDT 24
Peak memory 202064 kb
Host smart-42bb9bb1-e374-4d94-a645-4012574d46c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627149095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.1627149095
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.2862982491
Short name T26
Test name
Test status
Simulation time 32580607835 ps
CPU time 14.38 seconds
Started Jun 10 07:16:27 PM PDT 24
Finished Jun 10 07:16:46 PM PDT 24
Peak memory 201600 kb
Host smart-928b1e08-0223-4d25-8a3c-d7bfe15abd3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862982491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.2862982491
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.857086824
Short name T129
Test name
Test status
Simulation time 4751857764 ps
CPU time 12.71 seconds
Started Jun 10 07:16:29 PM PDT 24
Finished Jun 10 07:16:46 PM PDT 24
Peak memory 201636 kb
Host smart-f54f4480-b2fb-462f-baca-77d67430eed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857086824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.857086824
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.1651200553
Short name T85
Test name
Test status
Simulation time 8304986106 ps
CPU time 5.52 seconds
Started Jun 10 07:16:26 PM PDT 24
Finished Jun 10 07:16:37 PM PDT 24
Peak memory 218352 kb
Host smart-63cf09ce-0ceb-4377-8a5d-92faf0174530
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651200553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.1651200553
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.3732335470
Short name T561
Test name
Test status
Simulation time 6152395924 ps
CPU time 5.27 seconds
Started Jun 10 07:16:27 PM PDT 24
Finished Jun 10 07:16:38 PM PDT 24
Peak memory 201612 kb
Host smart-5344db73-23d2-4bb0-b978-eedf167fbc27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732335470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.3732335470
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.3713547913
Short name T602
Test name
Test status
Simulation time 330915368659 ps
CPU time 744.28 seconds
Started Jun 10 07:16:27 PM PDT 24
Finished Jun 10 07:28:56 PM PDT 24
Peak memory 201780 kb
Host smart-c548d6f6-f744-4eb3-924a-d2822dfe5191
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713547913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
3713547913
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.4011514635
Short name T61
Test name
Test status
Simulation time 57004655158 ps
CPU time 146.44 seconds
Started Jun 10 07:16:27 PM PDT 24
Finished Jun 10 07:18:58 PM PDT 24
Peak memory 210500 kb
Host smart-9ef03876-81fc-498c-8390-d869bda3f88d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011514635 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.4011514635
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.1527040086
Short name T467
Test name
Test status
Simulation time 452068005 ps
CPU time 0.69 seconds
Started Jun 10 07:20:46 PM PDT 24
Finished Jun 10 07:20:48 PM PDT 24
Peak memory 201464 kb
Host smart-49f2dbca-c0da-41d4-80ea-6b5030502c3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527040086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.1527040086
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.3582247041
Short name T254
Test name
Test status
Simulation time 362185000592 ps
CPU time 134.01 seconds
Started Jun 10 07:20:45 PM PDT 24
Finished Jun 10 07:23:00 PM PDT 24
Peak memory 201748 kb
Host smart-25100d0e-55b1-4bec-8f0e-5d67bff745c9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582247041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.3582247041
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.1466144967
Short name T649
Test name
Test status
Simulation time 171442586384 ps
CPU time 105.6 seconds
Started Jun 10 07:20:46 PM PDT 24
Finished Jun 10 07:22:33 PM PDT 24
Peak memory 201812 kb
Host smart-185c63a0-0e8a-4c17-b7c3-a71857edce37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466144967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.1466144967
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.3112714663
Short name T246
Test name
Test status
Simulation time 161680560802 ps
CPU time 59.05 seconds
Started Jun 10 07:20:34 PM PDT 24
Finished Jun 10 07:21:35 PM PDT 24
Peak memory 201784 kb
Host smart-f86bf217-942e-47a9-82f8-b8ebb61c55b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112714663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.3112714663
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.577709265
Short name T601
Test name
Test status
Simulation time 495713668980 ps
CPU time 280.14 seconds
Started Jun 10 07:20:38 PM PDT 24
Finished Jun 10 07:25:20 PM PDT 24
Peak memory 201700 kb
Host smart-74ae12a4-79a1-4ff0-ba17-7f43565eaa4f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=577709265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrup
t_fixed.577709265
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.237289543
Short name T739
Test name
Test status
Simulation time 162133013337 ps
CPU time 198.61 seconds
Started Jun 10 07:20:36 PM PDT 24
Finished Jun 10 07:23:57 PM PDT 24
Peak memory 201868 kb
Host smart-6013e5fb-e24d-4015-b8b1-50656ceed7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237289543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.237289543
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.2985051186
Short name T7
Test name
Test status
Simulation time 484901205048 ps
CPU time 1208.12 seconds
Started Jun 10 07:20:43 PM PDT 24
Finished Jun 10 07:40:52 PM PDT 24
Peak memory 201764 kb
Host smart-2feff3a1-43b9-4165-8d84-1bd60486da2b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985051186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.2985051186
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.1391418819
Short name T336
Test name
Test status
Simulation time 188532274950 ps
CPU time 108.35 seconds
Started Jun 10 07:20:34 PM PDT 24
Finished Jun 10 07:22:24 PM PDT 24
Peak memory 201836 kb
Host smart-22f373da-6093-4a35-ba41-fd831f4e6b4f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391418819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.1391418819
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.3950671961
Short name T697
Test name
Test status
Simulation time 628023361045 ps
CPU time 360.22 seconds
Started Jun 10 07:20:34 PM PDT 24
Finished Jun 10 07:26:36 PM PDT 24
Peak memory 201744 kb
Host smart-20bb0490-db50-4441-918f-4c8bc08af1ff
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950671961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.3950671961
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.2731854813
Short name T740
Test name
Test status
Simulation time 67985723451 ps
CPU time 347.16 seconds
Started Jun 10 07:20:45 PM PDT 24
Finished Jun 10 07:26:34 PM PDT 24
Peak memory 202040 kb
Host smart-2174a4f5-f7a0-46bc-86fa-34771db310cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731854813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.2731854813
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.2537155793
Short name T560
Test name
Test status
Simulation time 41575837024 ps
CPU time 28.09 seconds
Started Jun 10 07:20:43 PM PDT 24
Finished Jun 10 07:21:12 PM PDT 24
Peak memory 201648 kb
Host smart-dc79a592-a5ba-4e89-9c6a-a4141d80e72d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537155793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.2537155793
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.4220032210
Short name T547
Test name
Test status
Simulation time 5167209300 ps
CPU time 12.82 seconds
Started Jun 10 07:20:46 PM PDT 24
Finished Jun 10 07:21:00 PM PDT 24
Peak memory 201632 kb
Host smart-458a533b-201d-4d23-80f5-5c0f30074f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220032210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.4220032210
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.2771256893
Short name T437
Test name
Test status
Simulation time 5733001836 ps
CPU time 5.82 seconds
Started Jun 10 07:20:35 PM PDT 24
Finished Jun 10 07:20:43 PM PDT 24
Peak memory 201564 kb
Host smart-952946d3-7e54-4baa-b8c3-745ffad20772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771256893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.2771256893
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.1349198579
Short name T272
Test name
Test status
Simulation time 407250821476 ps
CPU time 1129.48 seconds
Started Jun 10 07:20:46 PM PDT 24
Finished Jun 10 07:39:37 PM PDT 24
Peak memory 202068 kb
Host smart-c4252faf-6f82-4f0d-8981-653766ca5b9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349198579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.1349198579
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.2634342032
Short name T14
Test name
Test status
Simulation time 132476753766 ps
CPU time 562.8 seconds
Started Jun 10 07:20:45 PM PDT 24
Finished Jun 10 07:30:09 PM PDT 24
Peak memory 210396 kb
Host smart-243e71f2-e506-4d7b-b519-ea55d21fe4c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634342032 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.2634342032
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.2588457551
Short name T699
Test name
Test status
Simulation time 313177863 ps
CPU time 0.79 seconds
Started Jun 10 07:21:05 PM PDT 24
Finished Jun 10 07:21:07 PM PDT 24
Peak memory 201440 kb
Host smart-d48bd23e-054d-40b6-b9b0-6f6dfcd0a015
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588457551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.2588457551
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.302426531
Short name T559
Test name
Test status
Simulation time 347773161883 ps
CPU time 209.97 seconds
Started Jun 10 07:20:54 PM PDT 24
Finished Jun 10 07:24:25 PM PDT 24
Peak memory 201788 kb
Host smart-2f8de7dc-179d-4652-904d-aa36e15e5166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302426531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.302426531
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.1152959370
Short name T265
Test name
Test status
Simulation time 326513937221 ps
CPU time 204.48 seconds
Started Jun 10 07:20:54 PM PDT 24
Finished Jun 10 07:24:19 PM PDT 24
Peak memory 201704 kb
Host smart-eefdff78-8f01-4eda-9e1f-a935c2274ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152959370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.1152959370
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.3617169787
Short name T585
Test name
Test status
Simulation time 504560929253 ps
CPU time 741.57 seconds
Started Jun 10 07:20:54 PM PDT 24
Finished Jun 10 07:33:17 PM PDT 24
Peak memory 201772 kb
Host smart-6c29b2b9-f52e-4f32-aa0d-0f82fbc415a6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617169787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.3617169787
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.24459494
Short name T412
Test name
Test status
Simulation time 171052008110 ps
CPU time 57.35 seconds
Started Jun 10 07:20:44 PM PDT 24
Finished Jun 10 07:21:42 PM PDT 24
Peak memory 201856 kb
Host smart-d40df9ac-a2a2-4e3b-a4c1-e3b24f3a8f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24459494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.24459494
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.897333546
Short name T471
Test name
Test status
Simulation time 335296870862 ps
CPU time 375.86 seconds
Started Jun 10 07:20:43 PM PDT 24
Finished Jun 10 07:27:01 PM PDT 24
Peak memory 201956 kb
Host smart-854f1003-d973-455f-8d85-f7b1c6f6541b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=897333546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fixe
d.897333546
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.1591983270
Short name T321
Test name
Test status
Simulation time 191006793137 ps
CPU time 450.4 seconds
Started Jun 10 07:20:54 PM PDT 24
Finished Jun 10 07:28:26 PM PDT 24
Peak memory 201844 kb
Host smart-f709e759-8c6b-4fac-847c-afd5fb805d4e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591983270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.1591983270
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.2822813731
Short name T485
Test name
Test status
Simulation time 197083367162 ps
CPU time 237.31 seconds
Started Jun 10 07:20:54 PM PDT 24
Finished Jun 10 07:24:52 PM PDT 24
Peak memory 201728 kb
Host smart-c4fd20b6-3328-416c-854c-b536a5692442
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822813731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.2822813731
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.3008974733
Short name T528
Test name
Test status
Simulation time 111569989098 ps
CPU time 459.87 seconds
Started Jun 10 07:20:55 PM PDT 24
Finished Jun 10 07:28:36 PM PDT 24
Peak memory 202188 kb
Host smart-203e2142-1ad0-4a45-8ce3-d6e4eb86ae8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008974733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.3008974733
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.1080942172
Short name T505
Test name
Test status
Simulation time 41769401160 ps
CPU time 44.27 seconds
Started Jun 10 07:20:54 PM PDT 24
Finished Jun 10 07:21:40 PM PDT 24
Peak memory 201656 kb
Host smart-c9976fc9-540f-41e6-9288-cc4619e159c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080942172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.1080942172
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.1495110542
Short name T801
Test name
Test status
Simulation time 3427092282 ps
CPU time 2.77 seconds
Started Jun 10 07:20:55 PM PDT 24
Finished Jun 10 07:20:59 PM PDT 24
Peak memory 201616 kb
Host smart-90e1a00c-5905-40f4-9113-378b82378ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495110542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.1495110542
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.3663716440
Short name T385
Test name
Test status
Simulation time 5704104970 ps
CPU time 2.31 seconds
Started Jun 10 07:20:45 PM PDT 24
Finished Jun 10 07:20:49 PM PDT 24
Peak memory 201640 kb
Host smart-14976f34-aa55-406e-a1b3-d2c5cb5b4f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663716440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.3663716440
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.1717275758
Short name T465
Test name
Test status
Simulation time 307648017193 ps
CPU time 462.33 seconds
Started Jun 10 07:20:54 PM PDT 24
Finished Jun 10 07:28:38 PM PDT 24
Peak memory 202088 kb
Host smart-f7c74d91-8619-4b94-bb71-aabc43bf64bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717275758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.1717275758
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.1412560064
Short name T420
Test name
Test status
Simulation time 384623407 ps
CPU time 1.03 seconds
Started Jun 10 07:21:15 PM PDT 24
Finished Jun 10 07:21:17 PM PDT 24
Peak memory 201500 kb
Host smart-f0e39475-bac2-478e-9c69-9adc86f13b30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412560064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.1412560064
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.4037028095
Short name T261
Test name
Test status
Simulation time 205125365099 ps
CPU time 119.59 seconds
Started Jun 10 07:21:05 PM PDT 24
Finished Jun 10 07:23:06 PM PDT 24
Peak memory 201796 kb
Host smart-45ccb66d-7ad7-4f9e-a26d-e4957b75ea03
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037028095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.4037028095
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.409933627
Short name T255
Test name
Test status
Simulation time 492189107970 ps
CPU time 1220.8 seconds
Started Jun 10 07:21:03 PM PDT 24
Finished Jun 10 07:41:25 PM PDT 24
Peak memory 201796 kb
Host smart-2dd1f479-32c2-455f-aeb2-f730dcf4f269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409933627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.409933627
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.1206141212
Short name T513
Test name
Test status
Simulation time 325498532629 ps
CPU time 720.81 seconds
Started Jun 10 07:21:03 PM PDT 24
Finished Jun 10 07:33:05 PM PDT 24
Peak memory 201772 kb
Host smart-baa343ff-eff8-43ef-ae5f-3b774d9151d1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206141212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.1206141212
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.3350225508
Short name T583
Test name
Test status
Simulation time 494113281551 ps
CPU time 376.8 seconds
Started Jun 10 07:21:03 PM PDT 24
Finished Jun 10 07:27:20 PM PDT 24
Peak memory 201884 kb
Host smart-38539101-03a3-4b78-bbe2-399f3065bf03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350225508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.3350225508
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.1614394176
Short name T395
Test name
Test status
Simulation time 483732122718 ps
CPU time 1181.18 seconds
Started Jun 10 07:21:05 PM PDT 24
Finished Jun 10 07:40:47 PM PDT 24
Peak memory 201716 kb
Host smart-02c00afd-905a-4a62-9870-f82eb6b2e7de
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614394176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.1614394176
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.3022581523
Short name T746
Test name
Test status
Simulation time 587070495250 ps
CPU time 202.24 seconds
Started Jun 10 07:21:03 PM PDT 24
Finished Jun 10 07:24:27 PM PDT 24
Peak memory 201784 kb
Host smart-c608385c-c4a3-437d-a3a9-9ce6463755a4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022581523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.3022581523
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.1335054283
Short name T454
Test name
Test status
Simulation time 125418601185 ps
CPU time 422.56 seconds
Started Jun 10 07:21:14 PM PDT 24
Finished Jun 10 07:28:18 PM PDT 24
Peak memory 202104 kb
Host smart-3a84a90f-c912-4801-85f1-ecc87ef2905e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335054283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.1335054283
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.1639361639
Short name T497
Test name
Test status
Simulation time 47448518514 ps
CPU time 118.55 seconds
Started Jun 10 07:21:16 PM PDT 24
Finished Jun 10 07:23:16 PM PDT 24
Peak memory 201628 kb
Host smart-b8307856-0eb4-4f06-9805-3558f38d7860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639361639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.1639361639
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.2754233801
Short name T451
Test name
Test status
Simulation time 3304095150 ps
CPU time 2.68 seconds
Started Jun 10 07:21:13 PM PDT 24
Finished Jun 10 07:21:18 PM PDT 24
Peak memory 201596 kb
Host smart-306159f7-ebe0-44c4-a9f6-95834c626a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754233801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.2754233801
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.3259780451
Short name T118
Test name
Test status
Simulation time 5923610233 ps
CPU time 2.77 seconds
Started Jun 10 07:21:03 PM PDT 24
Finished Jun 10 07:21:07 PM PDT 24
Peak memory 201644 kb
Host smart-f0925090-dc12-49dc-97d7-9c64da9b54c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259780451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.3259780451
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.3982174514
Short name T305
Test name
Test status
Simulation time 662274284721 ps
CPU time 1435.9 seconds
Started Jun 10 07:21:12 PM PDT 24
Finished Jun 10 07:45:10 PM PDT 24
Peak memory 201780 kb
Host smart-13f85959-f082-4167-9930-e97b4938306f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982174514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.3982174514
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.1626922701
Short name T350
Test name
Test status
Simulation time 139682193870 ps
CPU time 167.66 seconds
Started Jun 10 07:21:16 PM PDT 24
Finished Jun 10 07:24:05 PM PDT 24
Peak memory 210172 kb
Host smart-68d688e5-9bf4-41fa-8a70-3ef29f045cd9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626922701 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.1626922701
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.1635171783
Short name T380
Test name
Test status
Simulation time 426254911 ps
CPU time 1.55 seconds
Started Jun 10 07:21:23 PM PDT 24
Finished Jun 10 07:21:26 PM PDT 24
Peak memory 201488 kb
Host smart-c329b485-057c-488a-b214-98e3c7dd57bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635171783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.1635171783
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.2429035837
Short name T640
Test name
Test status
Simulation time 504977679610 ps
CPU time 246.26 seconds
Started Jun 10 07:21:27 PM PDT 24
Finished Jun 10 07:25:34 PM PDT 24
Peak memory 201804 kb
Host smart-08570d01-7311-4d6b-9cc2-b7e691c58488
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429035837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.2429035837
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.4254474412
Short name T646
Test name
Test status
Simulation time 159457874505 ps
CPU time 99.08 seconds
Started Jun 10 07:21:14 PM PDT 24
Finished Jun 10 07:22:54 PM PDT 24
Peak memory 201864 kb
Host smart-b05a7b86-af71-4bd5-b15e-4208b05a7fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254474412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.4254474412
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.3921624800
Short name T409
Test name
Test status
Simulation time 163212067401 ps
CPU time 179.13 seconds
Started Jun 10 07:21:16 PM PDT 24
Finished Jun 10 07:24:16 PM PDT 24
Peak memory 201804 kb
Host smart-5fd6f238-fe5d-402b-af58-9e005bdfc03e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921624800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.3921624800
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.1566489439
Short name T574
Test name
Test status
Simulation time 160433152773 ps
CPU time 89.42 seconds
Started Jun 10 07:21:12 PM PDT 24
Finished Jun 10 07:22:43 PM PDT 24
Peak memory 201796 kb
Host smart-aaeac611-4742-4fe0-9fd1-94329e62f232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566489439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.1566489439
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.2461044344
Short name T535
Test name
Test status
Simulation time 335066457240 ps
CPU time 806.03 seconds
Started Jun 10 07:21:15 PM PDT 24
Finished Jun 10 07:34:43 PM PDT 24
Peak memory 201776 kb
Host smart-701a1447-0e2f-4c42-bf4b-3c76e3e62950
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461044344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.2461044344
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.818842778
Short name T315
Test name
Test status
Simulation time 608930217995 ps
CPU time 1450 seconds
Started Jun 10 07:21:14 PM PDT 24
Finished Jun 10 07:45:25 PM PDT 24
Peak memory 201900 kb
Host smart-bcc05921-752c-489f-bc72-0f9cde3ffbc7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818842778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_
wakeup.818842778
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.18067839
Short name T493
Test name
Test status
Simulation time 399957246306 ps
CPU time 248.07 seconds
Started Jun 10 07:21:13 PM PDT 24
Finished Jun 10 07:25:23 PM PDT 24
Peak memory 201824 kb
Host smart-da9cde1f-d65f-4fe0-a0f4-dabe2775b41e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18067839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.a
dc_ctrl_filters_wakeup_fixed.18067839
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.1252197631
Short name T651
Test name
Test status
Simulation time 110281141672 ps
CPU time 425.6 seconds
Started Jun 10 07:21:21 PM PDT 24
Finished Jun 10 07:28:28 PM PDT 24
Peak memory 202120 kb
Host smart-442f0271-b20e-4c39-968e-10e6c301752f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252197631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.1252197631
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.338742474
Short name T377
Test name
Test status
Simulation time 29526171346 ps
CPU time 21.93 seconds
Started Jun 10 07:21:24 PM PDT 24
Finished Jun 10 07:21:47 PM PDT 24
Peak memory 201560 kb
Host smart-04d78c1a-5ba8-47d5-b6b1-a45f9be8e952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338742474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.338742474
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.454207933
Short name T554
Test name
Test status
Simulation time 5263852852 ps
CPU time 3.98 seconds
Started Jun 10 07:21:23 PM PDT 24
Finished Jun 10 07:21:28 PM PDT 24
Peak memory 201624 kb
Host smart-e488d817-4d16-446c-8598-6730debd1692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454207933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.454207933
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.3208637917
Short name T508
Test name
Test status
Simulation time 6144905979 ps
CPU time 8.37 seconds
Started Jun 10 07:21:13 PM PDT 24
Finished Jun 10 07:21:23 PM PDT 24
Peak memory 201688 kb
Host smart-9d9b37cf-9ad9-491e-826d-46183bb7a1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208637917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.3208637917
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.2921941159
Short name T314
Test name
Test status
Simulation time 136467767494 ps
CPU time 49.35 seconds
Started Jun 10 07:21:24 PM PDT 24
Finished Jun 10 07:22:14 PM PDT 24
Peak memory 201996 kb
Host smart-f8030a59-590b-4a18-acf2-2900fe7d31b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921941159 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.2921941159
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.1577642988
Short name T619
Test name
Test status
Simulation time 397678849 ps
CPU time 1.57 seconds
Started Jun 10 07:21:33 PM PDT 24
Finished Jun 10 07:21:36 PM PDT 24
Peak memory 201556 kb
Host smart-6457de22-d048-4cde-8a1b-a6d0492b75ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577642988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.1577642988
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.3883166361
Short name T785
Test name
Test status
Simulation time 173212357381 ps
CPU time 120.36 seconds
Started Jun 10 07:21:34 PM PDT 24
Finished Jun 10 07:23:35 PM PDT 24
Peak memory 201908 kb
Host smart-4cb55721-c659-4e80-beba-7624f34949e2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883166361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.3883166361
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.402306151
Short name T484
Test name
Test status
Simulation time 178933886334 ps
CPU time 426.83 seconds
Started Jun 10 07:21:30 PM PDT 24
Finished Jun 10 07:28:37 PM PDT 24
Peak memory 201776 kb
Host smart-6d000d7d-c2e0-4d4b-88d4-d27ad3ac45f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402306151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.402306151
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.669670729
Short name T310
Test name
Test status
Simulation time 325239446149 ps
CPU time 369.65 seconds
Started Jun 10 07:21:32 PM PDT 24
Finished Jun 10 07:27:43 PM PDT 24
Peak memory 201804 kb
Host smart-b6cfbe48-f612-4292-b753-a8171d6d5a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669670729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.669670729
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.3857635425
Short name T676
Test name
Test status
Simulation time 484477994362 ps
CPU time 553.59 seconds
Started Jun 10 07:21:33 PM PDT 24
Finished Jun 10 07:30:47 PM PDT 24
Peak memory 201776 kb
Host smart-1eb08093-7155-4399-9ec2-c61a413011e2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857635425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.3857635425
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.936028782
Short name T284
Test name
Test status
Simulation time 166036877405 ps
CPU time 96.93 seconds
Started Jun 10 07:21:24 PM PDT 24
Finished Jun 10 07:23:02 PM PDT 24
Peak memory 201820 kb
Host smart-20f4c601-c9a2-4ac5-b062-b5b528e03ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936028782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.936028782
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.3383891690
Short name T491
Test name
Test status
Simulation time 486860482575 ps
CPU time 280.5 seconds
Started Jun 10 07:21:24 PM PDT 24
Finished Jun 10 07:26:05 PM PDT 24
Peak memory 201744 kb
Host smart-1acd96b2-a475-4cd1-b311-777587fee561
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383891690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.3383891690
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.1066869227
Short name T353
Test name
Test status
Simulation time 452253607697 ps
CPU time 984.97 seconds
Started Jun 10 07:21:35 PM PDT 24
Finished Jun 10 07:38:01 PM PDT 24
Peak memory 201776 kb
Host smart-0ffdbd56-49f6-4245-8219-152582c90c1e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066869227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.1066869227
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.1924261674
Short name T499
Test name
Test status
Simulation time 395589034454 ps
CPU time 509.69 seconds
Started Jun 10 07:21:31 PM PDT 24
Finished Jun 10 07:30:01 PM PDT 24
Peak memory 201776 kb
Host smart-3cf3f25a-aebd-4c29-a35a-636732c53a25
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924261674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.1924261674
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.2701116179
Short name T695
Test name
Test status
Simulation time 81760031980 ps
CPU time 336.07 seconds
Started Jun 10 07:21:31 PM PDT 24
Finished Jun 10 07:27:08 PM PDT 24
Peak memory 202228 kb
Host smart-3ca59d16-3eb9-432e-9814-0a838e82187b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701116179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.2701116179
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.2493480603
Short name T677
Test name
Test status
Simulation time 31625072473 ps
CPU time 17.85 seconds
Started Jun 10 07:21:32 PM PDT 24
Finished Jun 10 07:21:50 PM PDT 24
Peak memory 201604 kb
Host smart-3334f08d-5d28-4fba-aaf6-97abe35d0f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493480603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.2493480603
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.958292004
Short name T531
Test name
Test status
Simulation time 4269805132 ps
CPU time 10.11 seconds
Started Jun 10 07:21:30 PM PDT 24
Finished Jun 10 07:21:41 PM PDT 24
Peak memory 201608 kb
Host smart-42688015-5904-41fe-9351-ae40527154f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958292004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.958292004
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.2569971551
Short name T719
Test name
Test status
Simulation time 6029454350 ps
CPU time 15.38 seconds
Started Jun 10 07:21:21 PM PDT 24
Finished Jun 10 07:21:38 PM PDT 24
Peak memory 201552 kb
Host smart-74bef15a-755a-4e9e-9a52-7fc92c5df7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569971551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.2569971551
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.3734518514
Short name T446
Test name
Test status
Simulation time 202376180224 ps
CPU time 469.99 seconds
Started Jun 10 07:21:33 PM PDT 24
Finished Jun 10 07:29:24 PM PDT 24
Peak memory 201948 kb
Host smart-ce1b86ad-f9ef-4457-9a41-7e216578bb57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734518514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.3734518514
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.1556030868
Short name T301
Test name
Test status
Simulation time 51099086617 ps
CPU time 65.34 seconds
Started Jun 10 07:21:35 PM PDT 24
Finished Jun 10 07:22:41 PM PDT 24
Peak memory 210472 kb
Host smart-c6ef1765-d41f-4458-8826-a7625d2afdcb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556030868 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.1556030868
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.1900815572
Short name T782
Test name
Test status
Simulation time 462144530 ps
CPU time 0.88 seconds
Started Jun 10 07:21:49 PM PDT 24
Finished Jun 10 07:21:51 PM PDT 24
Peak memory 201312 kb
Host smart-6e8fd89f-8dea-49aa-a481-932252e8da98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900815572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.1900815572
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.988430988
Short name T4
Test name
Test status
Simulation time 257170968912 ps
CPU time 13.32 seconds
Started Jun 10 07:21:38 PM PDT 24
Finished Jun 10 07:21:52 PM PDT 24
Peak memory 201808 kb
Host smart-e632fd87-d455-4186-b2f4-68f1c39f4b67
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988430988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gati
ng.988430988
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.583132266
Short name T190
Test name
Test status
Simulation time 490668820157 ps
CPU time 158.97 seconds
Started Jun 10 07:21:40 PM PDT 24
Finished Jun 10 07:24:20 PM PDT 24
Peak memory 201820 kb
Host smart-f914c013-9382-4c19-a381-dbf591683cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583132266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.583132266
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.1029092764
Short name T27
Test name
Test status
Simulation time 482895188569 ps
CPU time 1160.3 seconds
Started Jun 10 07:21:39 PM PDT 24
Finished Jun 10 07:41:00 PM PDT 24
Peak memory 201908 kb
Host smart-f0e12209-436d-4d27-af99-70fc2086052f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029092764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.1029092764
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.676906868
Short name T50
Test name
Test status
Simulation time 332052285276 ps
CPU time 438.22 seconds
Started Jun 10 07:21:39 PM PDT 24
Finished Jun 10 07:28:58 PM PDT 24
Peak memory 201876 kb
Host smart-8ebd3774-ba26-4476-a468-24d69a1788cf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=676906868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrup
t_fixed.676906868
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.3407372679
Short name T707
Test name
Test status
Simulation time 158655742749 ps
CPU time 371 seconds
Started Jun 10 07:21:39 PM PDT 24
Finished Jun 10 07:27:51 PM PDT 24
Peak memory 201792 kb
Host smart-56ba8106-4c74-453d-88d5-e56b69266a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407372679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.3407372679
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.485112183
Short name T424
Test name
Test status
Simulation time 501062268355 ps
CPU time 217.49 seconds
Started Jun 10 07:21:39 PM PDT 24
Finished Jun 10 07:25:17 PM PDT 24
Peak memory 201760 kb
Host smart-76c1411d-1260-46e3-9257-333494599bbd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=485112183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fixe
d.485112183
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.3283146023
Short name T327
Test name
Test status
Simulation time 365708848432 ps
CPU time 878.73 seconds
Started Jun 10 07:21:41 PM PDT 24
Finished Jun 10 07:36:20 PM PDT 24
Peak memory 201836 kb
Host smart-d145442e-8a22-43cd-a473-fd20df66fa53
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283146023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.3283146023
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.2623756128
Short name T107
Test name
Test status
Simulation time 424528808172 ps
CPU time 254.47 seconds
Started Jun 10 07:21:39 PM PDT 24
Finished Jun 10 07:25:54 PM PDT 24
Peak memory 201804 kb
Host smart-68236678-8193-4c80-9698-e2f5525360ab
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623756128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.2623756128
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.926377777
Short name T623
Test name
Test status
Simulation time 65054309664 ps
CPU time 319.73 seconds
Started Jun 10 07:21:41 PM PDT 24
Finished Jun 10 07:27:02 PM PDT 24
Peak memory 202172 kb
Host smart-5ab864e7-a234-476d-8af5-b3ac9729f15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926377777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.926377777
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.3737803794
Short name T589
Test name
Test status
Simulation time 30650888115 ps
CPU time 38.21 seconds
Started Jun 10 07:21:41 PM PDT 24
Finished Jun 10 07:22:21 PM PDT 24
Peak memory 201700 kb
Host smart-a15e2bea-11d9-4c53-abca-f9e2ef581951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737803794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.3737803794
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.2013456842
Short name T532
Test name
Test status
Simulation time 4663397815 ps
CPU time 11.9 seconds
Started Jun 10 07:21:38 PM PDT 24
Finished Jun 10 07:21:51 PM PDT 24
Peak memory 201568 kb
Host smart-8f50660d-a250-47c0-90c1-deef34451dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013456842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.2013456842
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.474027418
Short name T717
Test name
Test status
Simulation time 5752967165 ps
CPU time 4.26 seconds
Started Jun 10 07:21:40 PM PDT 24
Finished Jun 10 07:21:45 PM PDT 24
Peak memory 201612 kb
Host smart-0a8c7270-b4ff-4e8d-a508-cf02dfe7c272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474027418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.474027418
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.2656482820
Short name T174
Test name
Test status
Simulation time 721599647495 ps
CPU time 1426.51 seconds
Started Jun 10 07:21:49 PM PDT 24
Finished Jun 10 07:45:37 PM PDT 24
Peak memory 201800 kb
Host smart-a6dfa000-66e8-4281-9416-40c62dfd5881
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656482820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.2656482820
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.3242251157
Short name T80
Test name
Test status
Simulation time 298618531065 ps
CPU time 114.69 seconds
Started Jun 10 07:21:48 PM PDT 24
Finished Jun 10 07:23:44 PM PDT 24
Peak memory 210480 kb
Host smart-8b6c0ac6-49ef-420e-9fc4-3595c8407d2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242251157 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.3242251157
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.2528567163
Short name T433
Test name
Test status
Simulation time 423272406 ps
CPU time 1.54 seconds
Started Jun 10 07:22:00 PM PDT 24
Finished Jun 10 07:22:03 PM PDT 24
Peak memory 201468 kb
Host smart-98037cab-b44a-4544-b460-65c1bb8d3a15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528567163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.2528567163
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.2058013419
Short name T332
Test name
Test status
Simulation time 516543601011 ps
CPU time 321.52 seconds
Started Jun 10 07:21:50 PM PDT 24
Finished Jun 10 07:27:12 PM PDT 24
Peak memory 201816 kb
Host smart-96944324-9d20-4b41-8902-e07d9507708a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058013419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.2058013419
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.3871000790
Short name T618
Test name
Test status
Simulation time 516344548892 ps
CPU time 319.97 seconds
Started Jun 10 07:21:59 PM PDT 24
Finished Jun 10 07:27:20 PM PDT 24
Peak memory 201976 kb
Host smart-50f740ec-6819-468b-b1fc-1e52cf669b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871000790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.3871000790
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.1469089574
Short name T204
Test name
Test status
Simulation time 329360019050 ps
CPU time 213.69 seconds
Started Jun 10 07:21:49 PM PDT 24
Finished Jun 10 07:25:25 PM PDT 24
Peak memory 201780 kb
Host smart-88eeef21-547e-4896-9ad8-3033751a2095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469089574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.1469089574
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.2433737659
Short name T680
Test name
Test status
Simulation time 166188942792 ps
CPU time 201.57 seconds
Started Jun 10 07:21:50 PM PDT 24
Finished Jun 10 07:25:13 PM PDT 24
Peak memory 201896 kb
Host smart-3b0cd913-bced-46e9-92b0-9e1ae5d470bf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433737659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.2433737659
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.1743467428
Short name T134
Test name
Test status
Simulation time 162734055372 ps
CPU time 419.54 seconds
Started Jun 10 07:21:49 PM PDT 24
Finished Jun 10 07:28:49 PM PDT 24
Peak memory 201800 kb
Host smart-7ddbfda0-f3d9-4fa6-9f0a-3adcd93dd7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743467428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.1743467428
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.1861972309
Short name T430
Test name
Test status
Simulation time 323644017978 ps
CPU time 800.17 seconds
Started Jun 10 07:21:49 PM PDT 24
Finished Jun 10 07:35:11 PM PDT 24
Peak memory 201784 kb
Host smart-63739db4-c95f-4088-8620-1de45a7f2dba
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861972309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.1861972309
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.1379955047
Short name T39
Test name
Test status
Simulation time 177658383421 ps
CPU time 398.22 seconds
Started Jun 10 07:21:48 PM PDT 24
Finished Jun 10 07:28:27 PM PDT 24
Peak memory 201732 kb
Host smart-cad6a767-b33d-426e-bbc0-524f6ae14d27
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379955047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.1379955047
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.2545818823
Short name T472
Test name
Test status
Simulation time 387566435957 ps
CPU time 435.75 seconds
Started Jun 10 07:21:49 PM PDT 24
Finished Jun 10 07:29:06 PM PDT 24
Peak memory 201748 kb
Host smart-da928a61-8a5d-46f0-8fc3-fccecaec8ef1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545818823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.2545818823
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.1064212847
Short name T650
Test name
Test status
Simulation time 116535363589 ps
CPU time 486.54 seconds
Started Jun 10 07:21:58 PM PDT 24
Finished Jun 10 07:30:06 PM PDT 24
Peak memory 202068 kb
Host smart-3f493820-1597-44c8-80ef-a953c5e3e6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064212847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.1064212847
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.2973139900
Short name T568
Test name
Test status
Simulation time 31244577190 ps
CPU time 12.7 seconds
Started Jun 10 07:21:59 PM PDT 24
Finished Jun 10 07:22:12 PM PDT 24
Peak memory 201576 kb
Host smart-18bbae12-f49c-414e-bddb-3bccc7825121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973139900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.2973139900
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.2999217061
Short name T800
Test name
Test status
Simulation time 5323592386 ps
CPU time 13.6 seconds
Started Jun 10 07:21:57 PM PDT 24
Finished Jun 10 07:22:11 PM PDT 24
Peak memory 201588 kb
Host smart-18a3969d-2b25-4e09-874f-9b2bc433b026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999217061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.2999217061
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.1626134023
Short name T734
Test name
Test status
Simulation time 5588900282 ps
CPU time 4.56 seconds
Started Jun 10 07:21:48 PM PDT 24
Finished Jun 10 07:21:54 PM PDT 24
Peak memory 201632 kb
Host smart-58c97ccf-a620-42d2-adab-f68aa27eda7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626134023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.1626134023
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.430503468
Short name T442
Test name
Test status
Simulation time 464373071 ps
CPU time 1.2 seconds
Started Jun 10 07:22:08 PM PDT 24
Finished Jun 10 07:22:10 PM PDT 24
Peak memory 201480 kb
Host smart-d586a20a-d32c-4589-b329-a3a780bf8f1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430503468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.430503468
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.2591831686
Short name T199
Test name
Test status
Simulation time 501888367839 ps
CPU time 321.77 seconds
Started Jun 10 07:22:09 PM PDT 24
Finished Jun 10 07:27:32 PM PDT 24
Peak memory 201812 kb
Host smart-5690de5c-aacf-4e21-b297-baa7aee6052c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591831686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.2591831686
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.3894649501
Short name T510
Test name
Test status
Simulation time 321633770628 ps
CPU time 406.14 seconds
Started Jun 10 07:21:59 PM PDT 24
Finished Jun 10 07:28:46 PM PDT 24
Peak memory 201828 kb
Host smart-ac39d772-c828-4403-9c95-095bbe0fafb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894649501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.3894649501
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.71657975
Short name T59
Test name
Test status
Simulation time 325780343077 ps
CPU time 405.74 seconds
Started Jun 10 07:21:58 PM PDT 24
Finished Jun 10 07:28:45 PM PDT 24
Peak memory 201760 kb
Host smart-530d1e66-f725-452c-b2d4-8e6c160c0009
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=71657975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt
_fixed.71657975
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.2326366992
Short name T12
Test name
Test status
Simulation time 328839922232 ps
CPU time 178.54 seconds
Started Jun 10 07:21:58 PM PDT 24
Finished Jun 10 07:24:57 PM PDT 24
Peak memory 201852 kb
Host smart-c55bd4f2-5462-4388-ac39-04aa914991c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326366992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.2326366992
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.833700784
Short name T117
Test name
Test status
Simulation time 493475094033 ps
CPU time 287.61 seconds
Started Jun 10 07:22:01 PM PDT 24
Finished Jun 10 07:26:49 PM PDT 24
Peak memory 201840 kb
Host smart-226e26db-a121-421a-96a9-2a80f6549d0d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=833700784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fixe
d.833700784
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.2971774309
Short name T330
Test name
Test status
Simulation time 441955132649 ps
CPU time 268.44 seconds
Started Jun 10 07:22:00 PM PDT 24
Finished Jun 10 07:26:29 PM PDT 24
Peak memory 201780 kb
Host smart-f930807f-52d9-410c-a900-d13cb1a1d878
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971774309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.2971774309
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.212632389
Short name T616
Test name
Test status
Simulation time 213526704874 ps
CPU time 491.83 seconds
Started Jun 10 07:22:09 PM PDT 24
Finished Jun 10 07:30:22 PM PDT 24
Peak memory 201800 kb
Host smart-9d907dad-935a-473d-98b7-e15910f54331
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212632389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
adc_ctrl_filters_wakeup_fixed.212632389
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.2284678452
Short name T397
Test name
Test status
Simulation time 105441245368 ps
CPU time 407.56 seconds
Started Jun 10 07:22:08 PM PDT 24
Finished Jun 10 07:28:57 PM PDT 24
Peak memory 202120 kb
Host smart-b9c48330-6803-47a3-a913-0e52634d36cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284678452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.2284678452
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.2804372546
Short name T393
Test name
Test status
Simulation time 21652368681 ps
CPU time 13.26 seconds
Started Jun 10 07:22:09 PM PDT 24
Finished Jun 10 07:22:23 PM PDT 24
Peak memory 201580 kb
Host smart-91e77c8a-09d5-4f45-92fd-1616ba056603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804372546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.2804372546
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.1651788026
Short name T595
Test name
Test status
Simulation time 3636187543 ps
CPU time 9.83 seconds
Started Jun 10 07:22:09 PM PDT 24
Finished Jun 10 07:22:20 PM PDT 24
Peak memory 201600 kb
Host smart-9c72b3e4-e9fc-41ea-8889-387f69882309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651788026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.1651788026
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.226024940
Short name T413
Test name
Test status
Simulation time 5567370152 ps
CPU time 13.41 seconds
Started Jun 10 07:21:59 PM PDT 24
Finished Jun 10 07:22:14 PM PDT 24
Peak memory 201616 kb
Host smart-ffb531e4-753c-4803-aee3-fe4628f5f385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226024940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.226024940
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.2284052491
Short name T498
Test name
Test status
Simulation time 36660109899 ps
CPU time 42.98 seconds
Started Jun 10 07:22:10 PM PDT 24
Finished Jun 10 07:22:54 PM PDT 24
Peak memory 201724 kb
Host smart-48727f64-54e2-4c47-9311-2109b1cb7147
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284052491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.2284052491
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.1034749040
Short name T293
Test name
Test status
Simulation time 13883490934 ps
CPU time 37.81 seconds
Started Jun 10 07:22:09 PM PDT 24
Finished Jun 10 07:22:48 PM PDT 24
Peak memory 210404 kb
Host smart-6560408c-2148-4c61-a140-72b06ed22ffc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034749040 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.1034749040
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.4073505657
Short name T534
Test name
Test status
Simulation time 308139021 ps
CPU time 1.27 seconds
Started Jun 10 07:22:19 PM PDT 24
Finished Jun 10 07:22:22 PM PDT 24
Peak memory 201488 kb
Host smart-891c59a8-3fc8-4a19-a515-b7c9c6f06f17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073505657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.4073505657
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.3754683479
Short name T269
Test name
Test status
Simulation time 354409631185 ps
CPU time 765.5 seconds
Started Jun 10 07:22:20 PM PDT 24
Finished Jun 10 07:35:06 PM PDT 24
Peak memory 201840 kb
Host smart-484b8771-7311-40f8-9504-677c154f484f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754683479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.3754683479
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.2666913068
Short name T200
Test name
Test status
Simulation time 513784346133 ps
CPU time 222.9 seconds
Started Jun 10 07:22:20 PM PDT 24
Finished Jun 10 07:26:04 PM PDT 24
Peak memory 201872 kb
Host smart-738c8745-32b1-40e5-91cb-8c970d9caf53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666913068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.2666913068
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.1676520904
Short name T189
Test name
Test status
Simulation time 491124189679 ps
CPU time 633.5 seconds
Started Jun 10 07:22:21 PM PDT 24
Finished Jun 10 07:32:56 PM PDT 24
Peak memory 201788 kb
Host smart-59c565a7-88ee-4efb-b5ec-7c51868099c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676520904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.1676520904
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.160578886
Short name T210
Test name
Test status
Simulation time 163229012759 ps
CPU time 369.95 seconds
Started Jun 10 07:22:17 PM PDT 24
Finished Jun 10 07:28:28 PM PDT 24
Peak memory 201756 kb
Host smart-22cba9e9-ca83-4322-bde5-9c0bcfcc84f7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=160578886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrup
t_fixed.160578886
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.2633550204
Short name T348
Test name
Test status
Simulation time 162503106531 ps
CPU time 393.25 seconds
Started Jun 10 07:22:19 PM PDT 24
Finished Jun 10 07:28:54 PM PDT 24
Peak memory 201872 kb
Host smart-56950148-d8ad-4f53-9e7c-496cf02897eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633550204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.2633550204
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.2835183571
Short name T796
Test name
Test status
Simulation time 482457082903 ps
CPU time 359.77 seconds
Started Jun 10 07:22:19 PM PDT 24
Finished Jun 10 07:28:20 PM PDT 24
Peak memory 201828 kb
Host smart-f38ad18a-8c84-45c4-b4d0-cfbb387e7422
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835183571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.2835183571
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.2846755891
Short name T669
Test name
Test status
Simulation time 583528429536 ps
CPU time 1049.27 seconds
Started Jun 10 07:22:18 PM PDT 24
Finished Jun 10 07:39:48 PM PDT 24
Peak memory 201796 kb
Host smart-fc61d9a9-0291-4102-95cf-531e9e0b0b34
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846755891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.2846755891
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.274953086
Short name T112
Test name
Test status
Simulation time 83176080625 ps
CPU time 275.32 seconds
Started Jun 10 07:22:18 PM PDT 24
Finished Jun 10 07:26:54 PM PDT 24
Peak memory 202172 kb
Host smart-d7e8c9af-2074-4460-bd69-2e5dccf3a2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274953086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.274953086
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.4075172184
Short name T675
Test name
Test status
Simulation time 32111434292 ps
CPU time 37.87 seconds
Started Jun 10 07:22:19 PM PDT 24
Finished Jun 10 07:22:58 PM PDT 24
Peak memory 201612 kb
Host smart-187327b4-d36b-45c8-8693-cedf4961b4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075172184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.4075172184
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.1091839031
Short name T517
Test name
Test status
Simulation time 5130105349 ps
CPU time 6.84 seconds
Started Jun 10 07:22:21 PM PDT 24
Finished Jun 10 07:22:29 PM PDT 24
Peak memory 201600 kb
Host smart-e0b83319-601a-4cb2-b222-a006c60abe93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091839031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.1091839031
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.181825638
Short name T56
Test name
Test status
Simulation time 5556602738 ps
CPU time 1.81 seconds
Started Jun 10 07:22:10 PM PDT 24
Finished Jun 10 07:22:13 PM PDT 24
Peak memory 201692 kb
Host smart-c16d6ea0-058a-45b3-82d8-99720434651f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181825638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.181825638
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.1853344735
Short name T506
Test name
Test status
Simulation time 7960629805 ps
CPU time 5.92 seconds
Started Jun 10 07:22:21 PM PDT 24
Finished Jun 10 07:22:28 PM PDT 24
Peak memory 201552 kb
Host smart-2db3c8ca-dd82-4196-8caf-7992c4547c2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853344735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.1853344735
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.3187205787
Short name T565
Test name
Test status
Simulation time 36636168057 ps
CPU time 90.29 seconds
Started Jun 10 07:22:18 PM PDT 24
Finished Jun 10 07:23:50 PM PDT 24
Peak memory 218548 kb
Host smart-defbdacf-107a-44fc-b4c9-f2b0d4ae893f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187205787 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.3187205787
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.1815147777
Short name T741
Test name
Test status
Simulation time 335084952 ps
CPU time 1.02 seconds
Started Jun 10 07:22:29 PM PDT 24
Finished Jun 10 07:22:31 PM PDT 24
Peak memory 201472 kb
Host smart-d54d54b7-a78a-4266-8a3f-3094facfcf27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815147777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.1815147777
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.2927737307
Short name T167
Test name
Test status
Simulation time 178772513480 ps
CPU time 112.88 seconds
Started Jun 10 07:22:29 PM PDT 24
Finished Jun 10 07:24:23 PM PDT 24
Peak memory 201728 kb
Host smart-423b3274-55ed-4819-ae74-60794e2fdeaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927737307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.2927737307
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.293060348
Short name T222
Test name
Test status
Simulation time 496823446067 ps
CPU time 135.11 seconds
Started Jun 10 07:22:28 PM PDT 24
Finished Jun 10 07:24:44 PM PDT 24
Peak memory 201804 kb
Host smart-f6d7239e-a4d5-4ab9-9c28-bc3085090b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293060348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.293060348
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.833241644
Short name T633
Test name
Test status
Simulation time 490657834582 ps
CPU time 290.44 seconds
Started Jun 10 07:22:30 PM PDT 24
Finished Jun 10 07:27:22 PM PDT 24
Peak memory 201732 kb
Host smart-9bfad66b-a1cb-4162-af5c-85872e1e6e67
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=833241644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrup
t_fixed.833241644
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.2393726707
Short name T806
Test name
Test status
Simulation time 324273094333 ps
CPU time 798.62 seconds
Started Jun 10 07:22:20 PM PDT 24
Finished Jun 10 07:35:40 PM PDT 24
Peak memory 201924 kb
Host smart-3d9a63e6-8308-4c60-8f38-c8178057ccf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393726707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.2393726707
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.1248342738
Short name T748
Test name
Test status
Simulation time 165028071926 ps
CPU time 196.21 seconds
Started Jun 10 07:22:19 PM PDT 24
Finished Jun 10 07:25:37 PM PDT 24
Peak memory 201828 kb
Host smart-93864c30-801f-4179-8bcd-0b40266ab7a8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248342738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.1248342738
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.873443696
Short name T308
Test name
Test status
Simulation time 174853122314 ps
CPU time 104.01 seconds
Started Jun 10 07:22:28 PM PDT 24
Finished Jun 10 07:24:12 PM PDT 24
Peak memory 201864 kb
Host smart-3ba7acd6-2c89-4d65-9e2e-13b211fc842e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873443696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_
wakeup.873443696
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.3986090027
Short name T599
Test name
Test status
Simulation time 395700253229 ps
CPU time 258.79 seconds
Started Jun 10 07:22:30 PM PDT 24
Finished Jun 10 07:26:50 PM PDT 24
Peak memory 201908 kb
Host smart-9e7dcc90-4f49-42df-b6ed-8d521501ef8b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986090027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.3986090027
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.1955273277
Short name T416
Test name
Test status
Simulation time 74966846631 ps
CPU time 440.9 seconds
Started Jun 10 07:22:30 PM PDT 24
Finished Jun 10 07:29:52 PM PDT 24
Peak memory 202096 kb
Host smart-d4e3fa74-e623-4770-b6f2-9162c9aa3028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955273277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.1955273277
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.2610950265
Short name T392
Test name
Test status
Simulation time 36175960239 ps
CPU time 9.41 seconds
Started Jun 10 07:22:28 PM PDT 24
Finished Jun 10 07:22:38 PM PDT 24
Peak memory 201624 kb
Host smart-57272642-ff39-4c56-85ba-6eb979af0c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610950265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.2610950265
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.2391275951
Short name T744
Test name
Test status
Simulation time 3552262816 ps
CPU time 1.41 seconds
Started Jun 10 07:22:29 PM PDT 24
Finished Jun 10 07:22:31 PM PDT 24
Peak memory 201444 kb
Host smart-36b805a6-92a8-45d2-99d7-47f0a403fe36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391275951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.2391275951
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.814289489
Short name T629
Test name
Test status
Simulation time 5649468501 ps
CPU time 12.93 seconds
Started Jun 10 07:22:20 PM PDT 24
Finished Jun 10 07:22:34 PM PDT 24
Peak memory 201556 kb
Host smart-11aa89a9-7734-4819-9cb3-33ef415305a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814289489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.814289489
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.2659819793
Short name T655
Test name
Test status
Simulation time 399243974 ps
CPU time 1.56 seconds
Started Jun 10 07:16:27 PM PDT 24
Finished Jun 10 07:16:34 PM PDT 24
Peak memory 201488 kb
Host smart-e7213150-841f-4557-bf6a-ba2459a923b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659819793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.2659819793
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.909137073
Short name T563
Test name
Test status
Simulation time 366555723391 ps
CPU time 731.09 seconds
Started Jun 10 07:16:26 PM PDT 24
Finished Jun 10 07:28:42 PM PDT 24
Peak memory 201728 kb
Host smart-a1bfad7e-24da-4e1d-b9b8-53039436e7e0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909137073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gatin
g.909137073
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.266011560
Short name T180
Test name
Test status
Simulation time 169039924645 ps
CPU time 99.8 seconds
Started Jun 10 07:16:29 PM PDT 24
Finished Jun 10 07:18:14 PM PDT 24
Peak memory 201800 kb
Host smart-1a136606-10e2-4541-9b63-12e4fb41f946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266011560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.266011560
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.4039539620
Short name T411
Test name
Test status
Simulation time 156676311632 ps
CPU time 166.85 seconds
Started Jun 10 07:16:29 PM PDT 24
Finished Jun 10 07:19:21 PM PDT 24
Peak memory 201780 kb
Host smart-81a91be4-6a36-4bc4-823d-4c96ccfdba32
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039539620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.4039539620
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.66620636
Short name T449
Test name
Test status
Simulation time 163249615211 ps
CPU time 56.92 seconds
Started Jun 10 07:16:29 PM PDT 24
Finished Jun 10 07:17:31 PM PDT 24
Peak memory 201800 kb
Host smart-9bf075bd-a03e-4f80-aa26-fec9d7f6db92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66620636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.66620636
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.4275196819
Short name T688
Test name
Test status
Simulation time 494328490341 ps
CPU time 322.98 seconds
Started Jun 10 07:16:27 PM PDT 24
Finished Jun 10 07:21:55 PM PDT 24
Peak memory 201792 kb
Host smart-2b79bf68-ddc8-418d-95d8-0deb1c80a61e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275196819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.4275196819
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.2203071705
Short name T163
Test name
Test status
Simulation time 334270740781 ps
CPU time 209.36 seconds
Started Jun 10 07:16:27 PM PDT 24
Finished Jun 10 07:20:01 PM PDT 24
Peak memory 201728 kb
Host smart-8357a27a-d7f6-4cce-a6c9-d79da0003993
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203071705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.2203071705
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.503090880
Short name T438
Test name
Test status
Simulation time 583214563509 ps
CPU time 265.84 seconds
Started Jun 10 07:16:27 PM PDT 24
Finished Jun 10 07:20:58 PM PDT 24
Peak memory 201812 kb
Host smart-effbdf26-59ba-4fe8-bc70-3fb082a73f05
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503090880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.a
dc_ctrl_filters_wakeup_fixed.503090880
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.1052774844
Short name T659
Test name
Test status
Simulation time 109003977662 ps
CPU time 596.67 seconds
Started Jun 10 07:16:29 PM PDT 24
Finished Jun 10 07:26:31 PM PDT 24
Peak memory 202072 kb
Host smart-b6d6fdea-4c20-46fa-b4a1-3048ef97361e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052774844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.1052774844
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.2882300525
Short name T1
Test name
Test status
Simulation time 44399295414 ps
CPU time 100.16 seconds
Started Jun 10 07:16:27 PM PDT 24
Finished Jun 10 07:18:12 PM PDT 24
Peak memory 201572 kb
Host smart-c68a061c-d5e2-4da0-84ec-66e24e4221d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882300525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.2882300525
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.1344852758
Short name T460
Test name
Test status
Simulation time 4206096240 ps
CPU time 5.22 seconds
Started Jun 10 07:16:26 PM PDT 24
Finished Jun 10 07:16:35 PM PDT 24
Peak memory 201592 kb
Host smart-c9b12044-13d0-4b03-8dca-1197c88fa744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344852758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.1344852758
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.3949217751
Short name T86
Test name
Test status
Simulation time 4487249902 ps
CPU time 8.68 seconds
Started Jun 10 07:16:28 PM PDT 24
Finished Jun 10 07:16:42 PM PDT 24
Peak memory 217296 kb
Host smart-a5641363-3431-4215-bc33-0f2616deb5ec
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949217751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.3949217751
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.1148233064
Short name T125
Test name
Test status
Simulation time 5904598217 ps
CPU time 15.53 seconds
Started Jun 10 07:16:29 PM PDT 24
Finished Jun 10 07:16:50 PM PDT 24
Peak memory 201624 kb
Host smart-4b2c08bf-0955-41a0-99c5-15369be76357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148233064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.1148233064
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.3884102465
Short name T627
Test name
Test status
Simulation time 443969464859 ps
CPU time 1291.14 seconds
Started Jun 10 07:16:26 PM PDT 24
Finished Jun 10 07:38:02 PM PDT 24
Peak memory 202044 kb
Host smart-4a0c047c-f1e4-40bd-8ea0-77d2f2c37c76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884102465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
3884102465
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.3564392235
Short name T64
Test name
Test status
Simulation time 288697982863 ps
CPU time 375.02 seconds
Started Jun 10 07:16:29 PM PDT 24
Finished Jun 10 07:22:49 PM PDT 24
Peak memory 218336 kb
Host smart-8a787ba0-eb6f-4508-9120-c696dd2a8bf4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564392235 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.3564392235
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.4255236279
Short name T519
Test name
Test status
Simulation time 533458402 ps
CPU time 1.3 seconds
Started Jun 10 07:22:49 PM PDT 24
Finished Jun 10 07:22:51 PM PDT 24
Peak memory 201500 kb
Host smart-fcbea6cf-585f-440d-a12e-340d32c6ef86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255236279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.4255236279
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.407461010
Short name T171
Test name
Test status
Simulation time 342302413913 ps
CPU time 786.17 seconds
Started Jun 10 07:22:38 PM PDT 24
Finished Jun 10 07:35:45 PM PDT 24
Peak memory 201844 kb
Host smart-2b5a2e18-29e8-4941-89e4-15ec52052ecd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407461010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gati
ng.407461010
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.1574189757
Short name T548
Test name
Test status
Simulation time 168028059188 ps
CPU time 101.47 seconds
Started Jun 10 07:22:38 PM PDT 24
Finished Jun 10 07:24:20 PM PDT 24
Peak memory 201780 kb
Host smart-211227ca-e601-4d52-b651-0473680bf556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574189757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.1574189757
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.1455335749
Short name T441
Test name
Test status
Simulation time 485625973154 ps
CPU time 277.39 seconds
Started Jun 10 07:22:40 PM PDT 24
Finished Jun 10 07:27:18 PM PDT 24
Peak memory 201788 kb
Host smart-73fbb534-eb76-4851-a804-56e5234b9664
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455335749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.1455335749
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.2491930438
Short name T569
Test name
Test status
Simulation time 165613560113 ps
CPU time 31.22 seconds
Started Jun 10 07:22:27 PM PDT 24
Finished Jun 10 07:22:59 PM PDT 24
Peak memory 201820 kb
Host smart-6e69088d-1622-419e-ba55-a294212ec393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491930438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.2491930438
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.2021123000
Short name T779
Test name
Test status
Simulation time 160319602007 ps
CPU time 91.79 seconds
Started Jun 10 07:22:36 PM PDT 24
Finished Jun 10 07:24:09 PM PDT 24
Peak memory 201764 kb
Host smart-614fb235-c510-413a-aff2-e7e7c2db0d76
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021123000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.2021123000
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.1072226726
Short name T342
Test name
Test status
Simulation time 350816876340 ps
CPU time 223 seconds
Started Jun 10 07:22:38 PM PDT 24
Finished Jun 10 07:26:22 PM PDT 24
Peak memory 201796 kb
Host smart-94643255-5297-49f4-8153-e22ffc154c50
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072226726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.1072226726
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.1783247824
Short name T536
Test name
Test status
Simulation time 208560639779 ps
CPU time 463.26 seconds
Started Jun 10 07:22:37 PM PDT 24
Finished Jun 10 07:30:22 PM PDT 24
Peak memory 201812 kb
Host smart-9a3a558a-c914-4424-90e7-a1c6137ddce5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783247824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.1783247824
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.218335693
Short name T68
Test name
Test status
Simulation time 71045084607 ps
CPU time 254.59 seconds
Started Jun 10 07:22:38 PM PDT 24
Finished Jun 10 07:26:54 PM PDT 24
Peak memory 202292 kb
Host smart-a663072b-8b9e-48b5-8555-112aae5100db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218335693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.218335693
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.3566325489
Short name T52
Test name
Test status
Simulation time 31739837113 ps
CPU time 18.96 seconds
Started Jun 10 07:22:36 PM PDT 24
Finished Jun 10 07:22:56 PM PDT 24
Peak memory 201588 kb
Host smart-5eb0ad40-3e30-4b0e-81f5-3a528730d1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566325489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.3566325489
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.3003610351
Short name T653
Test name
Test status
Simulation time 5092358423 ps
CPU time 11.8 seconds
Started Jun 10 07:22:40 PM PDT 24
Finished Jun 10 07:22:52 PM PDT 24
Peak memory 201592 kb
Host smart-fbfcb217-55f8-46f1-a5ff-c322ee931dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003610351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.3003610351
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.190725949
Short name T42
Test name
Test status
Simulation time 5650890403 ps
CPU time 4.21 seconds
Started Jun 10 07:22:29 PM PDT 24
Finished Jun 10 07:22:34 PM PDT 24
Peak memory 201656 kb
Host smart-e15f92c9-403d-4590-87b6-0bb306f09cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190725949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.190725949
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.527399057
Short name T318
Test name
Test status
Simulation time 26026794306 ps
CPU time 56.21 seconds
Started Jun 10 07:22:37 PM PDT 24
Finished Jun 10 07:23:34 PM PDT 24
Peak memory 210104 kb
Host smart-b8242a28-0173-4122-bc85-0579f16529a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527399057 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.527399057
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.3511816937
Short name T202
Test name
Test status
Simulation time 298540818 ps
CPU time 1.18 seconds
Started Jun 10 07:22:59 PM PDT 24
Finished Jun 10 07:23:03 PM PDT 24
Peak memory 201404 kb
Host smart-0fcd8ba3-476b-4950-a9f8-4a324edf7524
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511816937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.3511816937
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.3195413665
Short name T303
Test name
Test status
Simulation time 342235424564 ps
CPU time 208.1 seconds
Started Jun 10 07:22:48 PM PDT 24
Finished Jun 10 07:26:17 PM PDT 24
Peak memory 201800 kb
Host smart-76d635bd-b9b0-4caa-be3b-0e925da6cb60
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195413665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.3195413665
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.3752782910
Short name T287
Test name
Test status
Simulation time 415941225903 ps
CPU time 990.26 seconds
Started Jun 10 07:22:57 PM PDT 24
Finished Jun 10 07:39:29 PM PDT 24
Peak memory 201896 kb
Host smart-520bf168-856e-4fee-b2e0-638f028c42fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752782910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.3752782910
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.2849709462
Short name T581
Test name
Test status
Simulation time 499553296925 ps
CPU time 287.82 seconds
Started Jun 10 07:22:47 PM PDT 24
Finished Jun 10 07:27:36 PM PDT 24
Peak memory 201760 kb
Host smart-49dcc258-b102-4012-baab-8ea817708fe6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849709462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.2849709462
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.1335086509
Short name T584
Test name
Test status
Simulation time 498143281028 ps
CPU time 726.36 seconds
Started Jun 10 07:22:48 PM PDT 24
Finished Jun 10 07:34:56 PM PDT 24
Peak memory 201756 kb
Host smart-b33503b0-e949-4026-a9af-a555fd006ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335086509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.1335086509
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.1137524972
Short name T381
Test name
Test status
Simulation time 491045728403 ps
CPU time 1160.1 seconds
Started Jun 10 07:22:47 PM PDT 24
Finished Jun 10 07:42:09 PM PDT 24
Peak memory 201768 kb
Host smart-9a90de42-c4d8-479d-a053-9bb87e6a52f9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137524972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.1137524972
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.2500821294
Short name T612
Test name
Test status
Simulation time 204277119921 ps
CPU time 193.34 seconds
Started Jun 10 07:22:48 PM PDT 24
Finished Jun 10 07:26:03 PM PDT 24
Peak memory 201800 kb
Host smart-2e91053b-416c-46b9-8465-a17eb9b1a6f4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500821294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.2500821294
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.2595278013
Short name T731
Test name
Test status
Simulation time 109773902468 ps
CPU time 383.66 seconds
Started Jun 10 07:22:57 PM PDT 24
Finished Jun 10 07:29:22 PM PDT 24
Peak memory 202196 kb
Host smart-a503cb93-da35-4318-b644-ea7f311e689b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595278013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.2595278013
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.925266034
Short name T523
Test name
Test status
Simulation time 37867080101 ps
CPU time 22.41 seconds
Started Jun 10 07:22:57 PM PDT 24
Finished Jun 10 07:23:20 PM PDT 24
Peak memory 201604 kb
Host smart-ce78df1d-69c7-4975-b1f3-2aa6e8622f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925266034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.925266034
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.560459773
Short name T387
Test name
Test status
Simulation time 5655691585 ps
CPU time 4.1 seconds
Started Jun 10 07:22:58 PM PDT 24
Finished Jun 10 07:23:05 PM PDT 24
Peak memory 201668 kb
Host smart-5a552a90-8e5e-4890-adf6-04d52398e33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560459773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.560459773
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.1738017750
Short name T37
Test name
Test status
Simulation time 5817395801 ps
CPU time 14.64 seconds
Started Jun 10 07:22:48 PM PDT 24
Finished Jun 10 07:23:04 PM PDT 24
Peak memory 201608 kb
Host smart-291d5c90-3adc-4995-9a10-6ee30539ccf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738017750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.1738017750
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.2550170017
Short name T552
Test name
Test status
Simulation time 189721774010 ps
CPU time 213.11 seconds
Started Jun 10 07:22:56 PM PDT 24
Finished Jun 10 07:26:30 PM PDT 24
Peak memory 201832 kb
Host smart-c1e19d93-d6d2-4fe6-81e6-65b1f20326df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550170017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.2550170017
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.1723787866
Short name T17
Test name
Test status
Simulation time 32304205064 ps
CPU time 81.75 seconds
Started Jun 10 07:22:59 PM PDT 24
Finished Jun 10 07:24:23 PM PDT 24
Peak memory 210464 kb
Host smart-c1a857b8-c963-4b22-939d-837e2e347218
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723787866 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.1723787866
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.2989850257
Short name T781
Test name
Test status
Simulation time 367430497 ps
CPU time 1.48 seconds
Started Jun 10 07:23:05 PM PDT 24
Finished Jun 10 07:23:08 PM PDT 24
Peak memory 201576 kb
Host smart-d769f7e5-bf18-410b-a676-6f9a8cfdd6b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989850257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.2989850257
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.2279074693
Short name T124
Test name
Test status
Simulation time 526583560686 ps
CPU time 328.79 seconds
Started Jun 10 07:23:06 PM PDT 24
Finished Jun 10 07:28:37 PM PDT 24
Peak memory 201808 kb
Host smart-f8d6f98a-b0ce-4a1f-899c-d824716eee8d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279074693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.2279074693
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.1946394282
Short name T724
Test name
Test status
Simulation time 329339378846 ps
CPU time 208.64 seconds
Started Jun 10 07:23:05 PM PDT 24
Finished Jun 10 07:26:35 PM PDT 24
Peak memory 201784 kb
Host smart-d3d58d88-39e7-44f0-8eef-23b43ce3ac3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946394282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.1946394282
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.1308851230
Short name T768
Test name
Test status
Simulation time 163241256757 ps
CPU time 134.93 seconds
Started Jun 10 07:22:57 PM PDT 24
Finished Jun 10 07:25:13 PM PDT 24
Peak memory 201804 kb
Host smart-7afdf316-0f12-4879-be94-5c9daf2330dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308851230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.1308851230
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.747919048
Short name T661
Test name
Test status
Simulation time 327963872938 ps
CPU time 197.95 seconds
Started Jun 10 07:23:06 PM PDT 24
Finished Jun 10 07:26:26 PM PDT 24
Peak memory 201756 kb
Host smart-7554ce57-04e0-424a-b96a-42cb295ea0d2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=747919048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrup
t_fixed.747919048
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.2399917144
Short name T215
Test name
Test status
Simulation time 500330956511 ps
CPU time 257.48 seconds
Started Jun 10 07:22:58 PM PDT 24
Finished Jun 10 07:27:17 PM PDT 24
Peak memory 201872 kb
Host smart-f3b52ab9-aea1-46ad-9bee-663ba481dbb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399917144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.2399917144
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.2913594888
Short name T706
Test name
Test status
Simulation time 492826410547 ps
CPU time 1219.87 seconds
Started Jun 10 07:22:57 PM PDT 24
Finished Jun 10 07:43:19 PM PDT 24
Peak memory 201756 kb
Host smart-38d2ad2c-464a-4c7c-a4e2-09464da3a3b5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913594888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.2913594888
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.3268651631
Short name T234
Test name
Test status
Simulation time 120638439638 ps
CPU time 428.08 seconds
Started Jun 10 07:23:06 PM PDT 24
Finished Jun 10 07:30:16 PM PDT 24
Peak memory 202184 kb
Host smart-97aee604-8f51-4099-a2ab-e4bb474c806c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268651631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.3268651631
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.1665417882
Short name T368
Test name
Test status
Simulation time 39529575807 ps
CPU time 98 seconds
Started Jun 10 07:23:06 PM PDT 24
Finished Jun 10 07:24:45 PM PDT 24
Peak memory 201604 kb
Host smart-f5e62fbf-8fa0-4d15-b586-12cc524da6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665417882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.1665417882
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.282129092
Short name T458
Test name
Test status
Simulation time 3462724790 ps
CPU time 2.89 seconds
Started Jun 10 07:23:07 PM PDT 24
Finished Jun 10 07:23:12 PM PDT 24
Peak memory 201532 kb
Host smart-cd9f33a7-02aa-495a-bdea-e01ad90220aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282129092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.282129092
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.2218332894
Short name T53
Test name
Test status
Simulation time 5685728914 ps
CPU time 5.48 seconds
Started Jun 10 07:22:57 PM PDT 24
Finished Jun 10 07:23:05 PM PDT 24
Peak memory 201608 kb
Host smart-fa27ed8a-ccb3-4f96-9628-497fae60971a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218332894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.2218332894
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.3869867117
Short name T324
Test name
Test status
Simulation time 454444375745 ps
CPU time 863.8 seconds
Started Jun 10 07:23:07 PM PDT 24
Finished Jun 10 07:37:32 PM PDT 24
Peak memory 202196 kb
Host smart-0a2afa8a-b78d-48f1-8e9b-08250a4499ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869867117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.3869867117
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.1503718573
Short name T45
Test name
Test status
Simulation time 51570181905 ps
CPU time 65.45 seconds
Started Jun 10 07:23:05 PM PDT 24
Finished Jun 10 07:24:12 PM PDT 24
Peak memory 210388 kb
Host smart-c6ff9f38-ced0-44c8-914a-70b60c46953a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503718573 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.1503718573
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.1071755052
Short name T450
Test name
Test status
Simulation time 487834431 ps
CPU time 0.7 seconds
Started Jun 10 07:23:25 PM PDT 24
Finished Jun 10 07:23:27 PM PDT 24
Peak memory 201460 kb
Host smart-c285d7c7-7b1c-4f4b-a183-7fb311ee60c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071755052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.1071755052
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.924503386
Short name T352
Test name
Test status
Simulation time 217702141688 ps
CPU time 146.18 seconds
Started Jun 10 07:23:17 PM PDT 24
Finished Jun 10 07:25:45 PM PDT 24
Peak memory 201880 kb
Host smart-118692f6-9249-4fe8-9181-d7a19a1cf6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924503386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.924503386
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.214854604
Short name T481
Test name
Test status
Simulation time 167159216431 ps
CPU time 412.64 seconds
Started Jun 10 07:23:15 PM PDT 24
Finished Jun 10 07:30:09 PM PDT 24
Peak memory 201884 kb
Host smart-3f7c14df-ada7-4706-97b9-2d0cec25b792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214854604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.214854604
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.2007479507
Short name T698
Test name
Test status
Simulation time 495017549861 ps
CPU time 1205.3 seconds
Started Jun 10 07:23:17 PM PDT 24
Finished Jun 10 07:43:25 PM PDT 24
Peak memory 201776 kb
Host smart-9400bd66-ab41-4aae-ba52-1dd07a4b4479
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007479507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.2007479507
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.218670429
Short name T593
Test name
Test status
Simulation time 161476541812 ps
CPU time 74.11 seconds
Started Jun 10 07:23:17 PM PDT 24
Finished Jun 10 07:24:33 PM PDT 24
Peak memory 201864 kb
Host smart-6a44f36a-ae42-43f9-8d77-9de4d3e28311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218670429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.218670429
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.888124123
Short name T406
Test name
Test status
Simulation time 166157643700 ps
CPU time 385.63 seconds
Started Jun 10 07:23:18 PM PDT 24
Finished Jun 10 07:29:45 PM PDT 24
Peak memory 201852 kb
Host smart-d07abf6c-d3a6-4a51-9e9f-f5bad84afcf7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=888124123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fixe
d.888124123
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.335396174
Short name T63
Test name
Test status
Simulation time 166536178297 ps
CPU time 167.15 seconds
Started Jun 10 07:23:16 PM PDT 24
Finished Jun 10 07:26:04 PM PDT 24
Peak memory 201904 kb
Host smart-212a5830-f99a-49a0-901c-2c7b981c0b74
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335396174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_
wakeup.335396174
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.1928680836
Short name T463
Test name
Test status
Simulation time 208206441209 ps
CPU time 132.85 seconds
Started Jun 10 07:23:16 PM PDT 24
Finished Jun 10 07:25:31 PM PDT 24
Peak memory 201868 kb
Host smart-faec05d3-eba4-4633-b966-6a6ed75d6e55
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928680836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.1928680836
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.574593032
Short name T233
Test name
Test status
Simulation time 104550973296 ps
CPU time 442.3 seconds
Started Jun 10 07:23:17 PM PDT 24
Finished Jun 10 07:30:42 PM PDT 24
Peak memory 202164 kb
Host smart-326e5917-3eec-44b8-b685-6e6a14ff300f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574593032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.574593032
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.3207890102
Short name T761
Test name
Test status
Simulation time 43246354430 ps
CPU time 95.82 seconds
Started Jun 10 07:23:17 PM PDT 24
Finished Jun 10 07:24:54 PM PDT 24
Peak memory 201544 kb
Host smart-de520f72-45a7-471a-a246-7767e2f62103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207890102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.3207890102
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.1205066501
Short name T373
Test name
Test status
Simulation time 4603051993 ps
CPU time 11.39 seconds
Started Jun 10 07:23:17 PM PDT 24
Finished Jun 10 07:23:31 PM PDT 24
Peak memory 201616 kb
Host smart-0227bf4b-806e-4d5f-b21b-a197c660b447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205066501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.1205066501
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.3919479873
Short name T586
Test name
Test status
Simulation time 5786528644 ps
CPU time 7.01 seconds
Started Jun 10 07:23:06 PM PDT 24
Finished Jun 10 07:23:15 PM PDT 24
Peak memory 201700 kb
Host smart-594a751a-43cf-41d1-9d87-61589d05fefd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919479873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.3919479873
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.2226590097
Short name T331
Test name
Test status
Simulation time 40160826536 ps
CPU time 68.32 seconds
Started Jun 10 07:23:28 PM PDT 24
Finished Jun 10 07:24:38 PM PDT 24
Peak memory 216264 kb
Host smart-ec27b5e9-8f93-4606-8592-83c15282178f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226590097 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.2226590097
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.2358149679
Short name T94
Test name
Test status
Simulation time 330854905 ps
CPU time 0.79 seconds
Started Jun 10 07:23:36 PM PDT 24
Finished Jun 10 07:23:38 PM PDT 24
Peak memory 201484 kb
Host smart-e1f016f0-847c-4628-9000-0f7bc509fda6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358149679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.2358149679
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.3894937655
Short name T609
Test name
Test status
Simulation time 340850296934 ps
CPU time 790.62 seconds
Started Jun 10 07:23:27 PM PDT 24
Finished Jun 10 07:36:40 PM PDT 24
Peak memory 201864 kb
Host smart-06a58499-385d-46a9-a3fc-3a9b48c07bbf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894937655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.3894937655
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.2789521242
Short name T326
Test name
Test status
Simulation time 343298488058 ps
CPU time 778.1 seconds
Started Jun 10 07:23:25 PM PDT 24
Finished Jun 10 07:36:26 PM PDT 24
Peak memory 201780 kb
Host smart-db88d231-98c7-417a-8b05-54135d19fd2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789521242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.2789521242
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.3784964179
Short name T759
Test name
Test status
Simulation time 325144303466 ps
CPU time 574.01 seconds
Started Jun 10 07:23:27 PM PDT 24
Finished Jun 10 07:33:03 PM PDT 24
Peak memory 201804 kb
Host smart-1cacd7d5-507d-4045-8366-5318295d85c0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784964179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.3784964179
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.2073969060
Short name T477
Test name
Test status
Simulation time 328065400841 ps
CPU time 68.64 seconds
Started Jun 10 07:23:26 PM PDT 24
Finished Jun 10 07:24:37 PM PDT 24
Peak memory 201864 kb
Host smart-f4d00261-32b5-414c-8762-9c144b5fae84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073969060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.2073969060
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.1916164888
Short name T405
Test name
Test status
Simulation time 332987410986 ps
CPU time 220.64 seconds
Started Jun 10 07:23:25 PM PDT 24
Finished Jun 10 07:27:08 PM PDT 24
Peak memory 201764 kb
Host smart-3de002e9-fdf4-4898-b87c-2bc9bb80cee8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916164888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.1916164888
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.3024880678
Short name T247
Test name
Test status
Simulation time 413562686029 ps
CPU time 647.14 seconds
Started Jun 10 07:23:27 PM PDT 24
Finished Jun 10 07:34:17 PM PDT 24
Peak memory 201824 kb
Host smart-b229d4df-2de0-409a-9254-f48acd132000
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024880678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.3024880678
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.4166814979
Short name T538
Test name
Test status
Simulation time 191594655773 ps
CPU time 228.35 seconds
Started Jun 10 07:23:25 PM PDT 24
Finished Jun 10 07:27:16 PM PDT 24
Peak memory 201816 kb
Host smart-3471ec2f-0bcd-4faa-83b6-1697faac4fc7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166814979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.4166814979
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.3574848629
Short name T423
Test name
Test status
Simulation time 81643655390 ps
CPU time 349.16 seconds
Started Jun 10 07:23:26 PM PDT 24
Finished Jun 10 07:29:17 PM PDT 24
Peak memory 202100 kb
Host smart-4bae3ce3-318e-4deb-9512-946ad1c4e991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574848629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.3574848629
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.2097763280
Short name T435
Test name
Test status
Simulation time 38257037413 ps
CPU time 71.53 seconds
Started Jun 10 07:23:26 PM PDT 24
Finished Jun 10 07:24:39 PM PDT 24
Peak memory 201612 kb
Host smart-29a20e05-f7b7-4369-8f85-1a9ce8d2835f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097763280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.2097763280
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.2198344570
Short name T771
Test name
Test status
Simulation time 5123200837 ps
CPU time 12.19 seconds
Started Jun 10 07:23:26 PM PDT 24
Finished Jun 10 07:23:41 PM PDT 24
Peak memory 201560 kb
Host smart-a886a48f-f40d-4a27-af0a-0f067c7783af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198344570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.2198344570
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.4249075139
Short name T459
Test name
Test status
Simulation time 6000350194 ps
CPU time 15.66 seconds
Started Jun 10 07:23:29 PM PDT 24
Finished Jun 10 07:23:47 PM PDT 24
Peak memory 201632 kb
Host smart-8a2a168c-fda3-4d8b-84aa-561f8a6b7f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249075139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.4249075139
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.1503546392
Short name T544
Test name
Test status
Simulation time 36402937351 ps
CPU time 22.28 seconds
Started Jun 10 07:23:36 PM PDT 24
Finished Jun 10 07:23:59 PM PDT 24
Peak memory 201688 kb
Host smart-cfb9cfe4-0995-4b00-a5b5-a01789448267
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503546392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.1503546392
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.1755485979
Short name T16
Test name
Test status
Simulation time 22296886404 ps
CPU time 60.05 seconds
Started Jun 10 07:23:27 PM PDT 24
Finished Jun 10 07:24:30 PM PDT 24
Peak memory 210408 kb
Host smart-de6191b6-2617-42bc-ba1c-7157c4229e1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755485979 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.1755485979
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.557374321
Short name T745
Test name
Test status
Simulation time 431874937 ps
CPU time 0.84 seconds
Started Jun 10 07:23:46 PM PDT 24
Finished Jun 10 07:23:48 PM PDT 24
Peak memory 201580 kb
Host smart-fbf89b24-8f90-4344-b255-8305ccc7f37e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557374321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.557374321
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.3663694460
Short name T770
Test name
Test status
Simulation time 165652097085 ps
CPU time 85.68 seconds
Started Jun 10 07:23:36 PM PDT 24
Finished Jun 10 07:25:03 PM PDT 24
Peak memory 201804 kb
Host smart-e6d94ae5-eef5-408c-816e-f706d0a09d16
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663694460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.3663694460
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.647666284
Short name T304
Test name
Test status
Simulation time 164160645812 ps
CPU time 385.61 seconds
Started Jun 10 07:23:38 PM PDT 24
Finished Jun 10 07:30:05 PM PDT 24
Peak memory 201824 kb
Host smart-8cf9fe84-7956-4808-866b-c92e5bd022fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647666284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.647666284
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.1516380591
Short name T626
Test name
Test status
Simulation time 326255114042 ps
CPU time 846.1 seconds
Started Jun 10 07:23:36 PM PDT 24
Finished Jun 10 07:37:43 PM PDT 24
Peak memory 201892 kb
Host smart-a86a7959-ad1f-4e06-bce7-2c2b507b931e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516380591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.1516380591
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.1817376380
Short name T530
Test name
Test status
Simulation time 318199655500 ps
CPU time 805.99 seconds
Started Jun 10 07:23:35 PM PDT 24
Finished Jun 10 07:37:03 PM PDT 24
Peak memory 201784 kb
Host smart-0bf37619-a54d-41d9-8574-9015e89c5e0f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817376380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.1817376380
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.2712386922
Short name T337
Test name
Test status
Simulation time 330349348080 ps
CPU time 138.78 seconds
Started Jun 10 07:23:35 PM PDT 24
Finished Jun 10 07:25:55 PM PDT 24
Peak memory 201796 kb
Host smart-d945c24b-4c04-48ce-a39a-1bb83b987331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712386922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.2712386922
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.2876032193
Short name T386
Test name
Test status
Simulation time 498112149163 ps
CPU time 1165.42 seconds
Started Jun 10 07:23:38 PM PDT 24
Finished Jun 10 07:43:05 PM PDT 24
Peak memory 201856 kb
Host smart-2d6472a3-821c-4618-9950-b4aa055bce3b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876032193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.2876032193
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.4260766020
Short name T562
Test name
Test status
Simulation time 355892258205 ps
CPU time 236.69 seconds
Started Jun 10 07:23:36 PM PDT 24
Finished Jun 10 07:27:34 PM PDT 24
Peak memory 201768 kb
Host smart-fc1e97bb-451b-49a4-8b2b-ad6c232fb4d6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260766020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.4260766020
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.1372052438
Short name T621
Test name
Test status
Simulation time 405875142902 ps
CPU time 893.94 seconds
Started Jun 10 07:23:36 PM PDT 24
Finished Jun 10 07:38:31 PM PDT 24
Peak memory 201852 kb
Host smart-d830d26f-6470-418f-8bba-a9269a92e879
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372052438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.1372052438
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.3951374685
Short name T776
Test name
Test status
Simulation time 87130536490 ps
CPU time 406.09 seconds
Started Jun 10 07:23:36 PM PDT 24
Finished Jun 10 07:30:23 PM PDT 24
Peak memory 202092 kb
Host smart-92774fe9-ce42-4319-9d0c-70e79c289239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951374685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.3951374685
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.633773807
Short name T754
Test name
Test status
Simulation time 28767902820 ps
CPU time 61.96 seconds
Started Jun 10 07:23:37 PM PDT 24
Finished Jun 10 07:24:40 PM PDT 24
Peak memory 201636 kb
Host smart-26a0f9b9-b756-4e77-ad3f-379010ab767e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633773807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.633773807
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.2206815595
Short name T394
Test name
Test status
Simulation time 4041316978 ps
CPU time 4.43 seconds
Started Jun 10 07:23:36 PM PDT 24
Finished Jun 10 07:23:42 PM PDT 24
Peak memory 201632 kb
Host smart-a87cc12c-01fe-49ae-8a4e-a27f483f8186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206815595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.2206815595
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.3438779416
Short name T634
Test name
Test status
Simulation time 5952839261 ps
CPU time 4.54 seconds
Started Jun 10 07:23:36 PM PDT 24
Finished Jun 10 07:23:42 PM PDT 24
Peak memory 201640 kb
Host smart-8bc69983-cca2-4f00-b162-afab22a508cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438779416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.3438779416
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.3961918261
Short name T647
Test name
Test status
Simulation time 132705756439 ps
CPU time 733.3 seconds
Started Jun 10 07:23:46 PM PDT 24
Finished Jun 10 07:36:01 PM PDT 24
Peak memory 210368 kb
Host smart-a1acf11a-08ca-4d24-bf0f-0c9db644690f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961918261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.3961918261
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.2783241929
Short name T522
Test name
Test status
Simulation time 218994757016 ps
CPU time 128.94 seconds
Started Jun 10 07:23:44 PM PDT 24
Finished Jun 10 07:25:54 PM PDT 24
Peak memory 210112 kb
Host smart-1217bbfc-b227-47fb-a22d-6547d73309e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783241929 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.2783241929
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.3586840292
Short name T591
Test name
Test status
Simulation time 446752614 ps
CPU time 1.71 seconds
Started Jun 10 07:23:46 PM PDT 24
Finished Jun 10 07:23:49 PM PDT 24
Peak memory 201440 kb
Host smart-a4ba129c-1ba1-4572-a7bd-41dfeffdd749
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586840292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.3586840292
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.1351876473
Short name T221
Test name
Test status
Simulation time 514888004371 ps
CPU time 279.77 seconds
Started Jun 10 07:23:45 PM PDT 24
Finished Jun 10 07:28:26 PM PDT 24
Peak memory 201780 kb
Host smart-d5c2f15c-bc32-4f42-b3f5-381ce8f9038e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351876473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.1351876473
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.3771344957
Short name T757
Test name
Test status
Simulation time 164493430736 ps
CPU time 102.25 seconds
Started Jun 10 07:23:45 PM PDT 24
Finished Jun 10 07:25:28 PM PDT 24
Peak memory 201796 kb
Host smart-1134ad61-4883-4d2e-992a-2f979586d66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771344957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.3771344957
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.718821340
Short name T253
Test name
Test status
Simulation time 484749423193 ps
CPU time 590.52 seconds
Started Jun 10 07:23:47 PM PDT 24
Finished Jun 10 07:33:39 PM PDT 24
Peak memory 201728 kb
Host smart-d80ff780-4f37-4d11-a210-a3afea0c4e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718821340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.718821340
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.2680616590
Short name T791
Test name
Test status
Simulation time 326116841708 ps
CPU time 187.28 seconds
Started Jun 10 07:23:48 PM PDT 24
Finished Jun 10 07:26:57 PM PDT 24
Peak memory 201808 kb
Host smart-afbb5263-8746-4fc5-8c05-1453c2d57b18
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680616590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.2680616590
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.4269932549
Short name T347
Test name
Test status
Simulation time 483057416863 ps
CPU time 297.4 seconds
Started Jun 10 07:23:45 PM PDT 24
Finished Jun 10 07:28:43 PM PDT 24
Peak memory 201840 kb
Host smart-809893e6-10ad-43ae-9dac-e7d06535462c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269932549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.4269932549
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.4002823529
Short name T524
Test name
Test status
Simulation time 174250073832 ps
CPU time 192.3 seconds
Started Jun 10 07:23:46 PM PDT 24
Finished Jun 10 07:26:59 PM PDT 24
Peak memory 201764 kb
Host smart-0df74c00-b5ce-4f53-8790-2e655fc08bac
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002823529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.4002823529
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.258294590
Short name T667
Test name
Test status
Simulation time 558926712188 ps
CPU time 144.71 seconds
Started Jun 10 07:23:48 PM PDT 24
Finished Jun 10 07:26:14 PM PDT 24
Peak memory 201912 kb
Host smart-ea25feef-b5bc-4640-b2ec-93c38a236365
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258294590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_
wakeup.258294590
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.3658427826
Short name T638
Test name
Test status
Simulation time 618460167677 ps
CPU time 1449.36 seconds
Started Jun 10 07:23:46 PM PDT 24
Finished Jun 10 07:47:57 PM PDT 24
Peak memory 201748 kb
Host smart-056d8383-9c00-4624-bb97-197ef97b3960
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658427826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.3658427826
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.2234830973
Short name T592
Test name
Test status
Simulation time 115098715720 ps
CPU time 603.39 seconds
Started Jun 10 07:23:46 PM PDT 24
Finished Jun 10 07:33:51 PM PDT 24
Peak memory 202144 kb
Host smart-2449c006-bd6a-40d0-a642-f92ad40d2404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234830973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.2234830973
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.3265186403
Short name T428
Test name
Test status
Simulation time 40701538519 ps
CPU time 90.53 seconds
Started Jun 10 07:23:47 PM PDT 24
Finished Jun 10 07:25:19 PM PDT 24
Peak memory 201564 kb
Host smart-8e9f75a4-1d02-48cc-b9c2-af2366e650cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265186403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.3265186403
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.1728673176
Short name T705
Test name
Test status
Simulation time 3567340683 ps
CPU time 9.32 seconds
Started Jun 10 07:23:46 PM PDT 24
Finished Jun 10 07:23:56 PM PDT 24
Peak memory 201536 kb
Host smart-bf13bcdb-f44a-42c4-905f-8a5f970baf29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728673176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.1728673176
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.2612920791
Short name T6
Test name
Test status
Simulation time 5630519192 ps
CPU time 13.84 seconds
Started Jun 10 07:23:45 PM PDT 24
Finished Jun 10 07:24:00 PM PDT 24
Peak memory 201728 kb
Host smart-3431e9c0-3f33-4ec5-bc87-8b96a9e1b551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612920791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.2612920791
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.2851425622
Short name T230
Test name
Test status
Simulation time 196472310338 ps
CPU time 757.48 seconds
Started Jun 10 07:23:48 PM PDT 24
Finished Jun 10 07:36:26 PM PDT 24
Peak memory 202148 kb
Host smart-d63b973b-1609-41ff-a2f2-8faf004fb49c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851425622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.2851425622
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.4087144714
Short name T760
Test name
Test status
Simulation time 72180095979 ps
CPU time 83.27 seconds
Started Jun 10 07:23:48 PM PDT 24
Finished Jun 10 07:25:13 PM PDT 24
Peak memory 210384 kb
Host smart-3e62c16b-1d23-42f2-a9a6-f49adc946378
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087144714 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.4087144714
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.3964346000
Short name T608
Test name
Test status
Simulation time 370070310 ps
CPU time 1.44 seconds
Started Jun 10 07:24:08 PM PDT 24
Finished Jun 10 07:24:13 PM PDT 24
Peak memory 201436 kb
Host smart-051f4590-b01e-48c9-8267-2e88557281aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964346000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.3964346000
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.4073872532
Short name T206
Test name
Test status
Simulation time 161494510550 ps
CPU time 65.38 seconds
Started Jun 10 07:23:59 PM PDT 24
Finished Jun 10 07:25:09 PM PDT 24
Peak memory 201844 kb
Host smart-b739c0b6-05e7-476f-99d0-5b01cbc8a1fc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073872532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.4073872532
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.3741999591
Short name T274
Test name
Test status
Simulation time 324888000005 ps
CPU time 379.41 seconds
Started Jun 10 07:23:58 PM PDT 24
Finished Jun 10 07:30:22 PM PDT 24
Peak memory 201860 kb
Host smart-7c30a3fd-2dd1-4f86-b37f-ee17823a7d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741999591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.3741999591
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.3961943179
Short name T388
Test name
Test status
Simulation time 496703503849 ps
CPU time 327.83 seconds
Started Jun 10 07:23:57 PM PDT 24
Finished Jun 10 07:29:29 PM PDT 24
Peak memory 201864 kb
Host smart-81e69f5c-3a2e-49a7-9de6-3fd3f1dd2258
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961943179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.3961943179
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.1387378806
Short name T631
Test name
Test status
Simulation time 322596015489 ps
CPU time 363.67 seconds
Started Jun 10 07:23:56 PM PDT 24
Finished Jun 10 07:30:04 PM PDT 24
Peak memory 201832 kb
Host smart-548a63e3-f9b3-4e63-b73d-bf52bd26fe89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387378806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.1387378806
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.2824048791
Short name T526
Test name
Test status
Simulation time 331972197760 ps
CPU time 760.55 seconds
Started Jun 10 07:23:57 PM PDT 24
Finished Jun 10 07:36:42 PM PDT 24
Peak memory 201888 kb
Host smart-33ad55b0-58c6-48a9-983a-6ab3df439fe4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824048791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.2824048791
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.628950890
Short name T778
Test name
Test status
Simulation time 393478696666 ps
CPU time 902.35 seconds
Started Jun 10 07:23:56 PM PDT 24
Finished Jun 10 07:39:02 PM PDT 24
Peak memory 201776 kb
Host smart-8bf47a57-0f40-44bb-808f-8689bd0184ed
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628950890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
adc_ctrl_filters_wakeup_fixed.628950890
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.826263954
Short name T696
Test name
Test status
Simulation time 137866774026 ps
CPU time 591 seconds
Started Jun 10 07:23:57 PM PDT 24
Finished Jun 10 07:33:52 PM PDT 24
Peak memory 202172 kb
Host smart-1347fcdb-ba4a-4c79-9d0c-b008f4fdc912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826263954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.826263954
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.1925471425
Short name T123
Test name
Test status
Simulation time 31362606637 ps
CPU time 18.9 seconds
Started Jun 10 07:23:59 PM PDT 24
Finished Jun 10 07:24:22 PM PDT 24
Peak memory 201604 kb
Host smart-17a22030-8f15-48ed-8a93-ff9c26366a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925471425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.1925471425
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.3544890513
Short name T452
Test name
Test status
Simulation time 3287404857 ps
CPU time 2.19 seconds
Started Jun 10 07:23:57 PM PDT 24
Finished Jun 10 07:24:03 PM PDT 24
Peak memory 201616 kb
Host smart-0003efb4-85d1-4199-86b4-bf0382712c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544890513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.3544890513
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.2381705402
Short name T690
Test name
Test status
Simulation time 5610426923 ps
CPU time 14.29 seconds
Started Jun 10 07:23:58 PM PDT 24
Finished Jun 10 07:24:17 PM PDT 24
Peak memory 201616 kb
Host smart-b4b2c1e4-446f-4c37-be18-5fd4c7fd5915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381705402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.2381705402
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.7555687
Short name T297
Test name
Test status
Simulation time 238629712133 ps
CPU time 788.81 seconds
Started Jun 10 07:24:07 PM PDT 24
Finished Jun 10 07:37:20 PM PDT 24
Peak memory 210360 kb
Host smart-c6dfbd5a-ce57-47ff-bb6b-59680a37a787
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7555687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_a
ll_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all.7555687
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.2490848487
Short name T22
Test name
Test status
Simulation time 339419160651 ps
CPU time 433.18 seconds
Started Jun 10 07:24:05 PM PDT 24
Finished Jun 10 07:31:23 PM PDT 24
Peak memory 210464 kb
Host smart-ab17961a-6592-4c71-83f1-95c8ab9d43a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490848487 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.2490848487
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.3136056582
Short name T703
Test name
Test status
Simulation time 342805575 ps
CPU time 0.8 seconds
Started Jun 10 07:24:19 PM PDT 24
Finished Jun 10 07:24:22 PM PDT 24
Peak memory 201468 kb
Host smart-80472e42-7be5-4494-8b75-d41f4f26e2b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136056582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.3136056582
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.172548575
Short name T587
Test name
Test status
Simulation time 158692979076 ps
CPU time 104.07 seconds
Started Jun 10 07:24:08 PM PDT 24
Finished Jun 10 07:25:55 PM PDT 24
Peak memory 201888 kb
Host smart-b21c814b-07ea-4ad6-abd9-0021a353d3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172548575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.172548575
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.1443909614
Short name T551
Test name
Test status
Simulation time 166576199600 ps
CPU time 56.83 seconds
Started Jun 10 07:24:07 PM PDT 24
Finished Jun 10 07:25:08 PM PDT 24
Peak memory 201864 kb
Host smart-49f4546d-68eb-45d7-bcec-8ebf650034fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443909614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.1443909614
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.128077070
Short name T708
Test name
Test status
Simulation time 495867800851 ps
CPU time 282.03 seconds
Started Jun 10 07:24:07 PM PDT 24
Finished Jun 10 07:28:53 PM PDT 24
Peak memory 201784 kb
Host smart-46d00f86-92f3-4728-a56b-0f6202e0f281
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=128077070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrup
t_fixed.128077070
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.2517756826
Short name T486
Test name
Test status
Simulation time 326807185438 ps
CPU time 208.21 seconds
Started Jun 10 07:24:06 PM PDT 24
Finished Jun 10 07:27:38 PM PDT 24
Peak memory 201856 kb
Host smart-4851b756-1d58-4bc9-b44d-b8c687b44b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517756826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.2517756826
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.1881884182
Short name T577
Test name
Test status
Simulation time 500339672524 ps
CPU time 333.22 seconds
Started Jun 10 07:24:07 PM PDT 24
Finished Jun 10 07:29:44 PM PDT 24
Peak memory 201828 kb
Host smart-a9cbe787-7d4f-4d9c-bcc5-1125c13ed4fc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881884182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.1881884182
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.1722329509
Short name T596
Test name
Test status
Simulation time 355216559783 ps
CPU time 442.77 seconds
Started Jun 10 07:24:07 PM PDT 24
Finished Jun 10 07:31:34 PM PDT 24
Peak memory 201808 kb
Host smart-7ee660b5-af43-4374-9d8a-403bc774fa2e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722329509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.1722329509
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.851057121
Short name T224
Test name
Test status
Simulation time 198560633609 ps
CPU time 429.11 seconds
Started Jun 10 07:24:06 PM PDT 24
Finished Jun 10 07:31:19 PM PDT 24
Peak memory 201796 kb
Host smart-11206c79-8bc6-493e-8aaf-1a95cd7bafd8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851057121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
adc_ctrl_filters_wakeup_fixed.851057121
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.1473085614
Short name T749
Test name
Test status
Simulation time 78427644086 ps
CPU time 283.67 seconds
Started Jun 10 07:24:20 PM PDT 24
Finished Jun 10 07:29:05 PM PDT 24
Peak memory 202116 kb
Host smart-073c9c9f-693e-4602-845f-cb413d518a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473085614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.1473085614
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.4175446998
Short name T504
Test name
Test status
Simulation time 23562601112 ps
CPU time 14.62 seconds
Started Jun 10 07:24:18 PM PDT 24
Finished Jun 10 07:24:35 PM PDT 24
Peak memory 201540 kb
Host smart-e9e4b05d-cb9d-40ec-931f-e8f107856746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175446998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.4175446998
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.1871380
Short name T367
Test name
Test status
Simulation time 4607995929 ps
CPU time 2.24 seconds
Started Jun 10 07:24:19 PM PDT 24
Finished Jun 10 07:24:23 PM PDT 24
Peak memory 201604 kb
Host smart-20b2a894-4660-48fe-96bd-9ebd7857e757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.1871380
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.3333407876
Short name T365
Test name
Test status
Simulation time 5707128886 ps
CPU time 14.67 seconds
Started Jun 10 07:24:07 PM PDT 24
Finished Jun 10 07:24:25 PM PDT 24
Peak memory 201632 kb
Host smart-720a0aee-ae1b-4c19-930b-5601bbd96d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333407876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.3333407876
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.1222967076
Short name T33
Test name
Test status
Simulation time 36304272488 ps
CPU time 86.54 seconds
Started Jun 10 07:24:20 PM PDT 24
Finished Jun 10 07:25:49 PM PDT 24
Peak memory 201636 kb
Host smart-86329382-3d70-4e29-812c-7a317d60eba6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222967076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.1222967076
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.3144215649
Short name T396
Test name
Test status
Simulation time 408212206 ps
CPU time 1.42 seconds
Started Jun 10 07:24:32 PM PDT 24
Finished Jun 10 07:24:38 PM PDT 24
Peak memory 201576 kb
Host smart-14459b5c-07c2-4432-837a-59be68498a66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144215649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.3144215649
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.1698411004
Short name T632
Test name
Test status
Simulation time 182441771550 ps
CPU time 203.66 seconds
Started Jun 10 07:24:31 PM PDT 24
Finished Jun 10 07:27:59 PM PDT 24
Peak memory 201624 kb
Host smart-c90b82c7-20b6-4692-9428-c0ce91e58f67
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698411004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.1698411004
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.3010426806
Short name T257
Test name
Test status
Simulation time 318282490527 ps
CPU time 211.04 seconds
Started Jun 10 07:24:30 PM PDT 24
Finished Jun 10 07:28:06 PM PDT 24
Peak memory 201884 kb
Host smart-18b7fdb8-b92f-4a1f-ad40-41241d2b4203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010426806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.3010426806
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.2309449478
Short name T738
Test name
Test status
Simulation time 326693416453 ps
CPU time 779.33 seconds
Started Jun 10 07:24:28 PM PDT 24
Finished Jun 10 07:37:32 PM PDT 24
Peak memory 201812 kb
Host smart-55cc4996-c213-4130-adb5-b73032cba278
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309449478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.2309449478
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.2904771513
Short name T339
Test name
Test status
Simulation time 492109311201 ps
CPU time 1127.73 seconds
Started Jun 10 07:24:17 PM PDT 24
Finished Jun 10 07:43:06 PM PDT 24
Peak memory 201812 kb
Host smart-70ef1cd3-32ce-4d8b-9a02-64a1610e0201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904771513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.2904771513
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.3616475291
Short name T445
Test name
Test status
Simulation time 328082313317 ps
CPU time 311.41 seconds
Started Jun 10 07:24:21 PM PDT 24
Finished Jun 10 07:29:34 PM PDT 24
Peak memory 201776 kb
Host smart-7a4bc57f-1d3f-48b7-8743-3d4201415a26
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616475291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.3616475291
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.3899746286
Short name T30
Test name
Test status
Simulation time 606262810285 ps
CPU time 1399.52 seconds
Started Jun 10 07:24:27 PM PDT 24
Finished Jun 10 07:47:50 PM PDT 24
Peak memory 201828 kb
Host smart-12622476-8ecc-478f-9de5-8debde849294
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899746286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.3899746286
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.425303168
Short name T425
Test name
Test status
Simulation time 201788686253 ps
CPU time 122.72 seconds
Started Jun 10 07:24:28 PM PDT 24
Finished Jun 10 07:26:34 PM PDT 24
Peak memory 201804 kb
Host smart-946ca80a-0045-4d55-87bd-9cf304d0ac4d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425303168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
adc_ctrl_filters_wakeup_fixed.425303168
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.4270970099
Short name T429
Test name
Test status
Simulation time 104511432540 ps
CPU time 590.85 seconds
Started Jun 10 07:24:29 PM PDT 24
Finished Jun 10 07:34:24 PM PDT 24
Peak memory 202172 kb
Host smart-af795d0b-a599-4a06-b2c4-4deec611e631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270970099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.4270970099
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.3046752556
Short name T556
Test name
Test status
Simulation time 39411049523 ps
CPU time 89.85 seconds
Started Jun 10 07:24:30 PM PDT 24
Finished Jun 10 07:26:04 PM PDT 24
Peak memory 201604 kb
Host smart-11acde8b-c248-4276-b9d5-a27665129d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046752556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.3046752556
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.2487156748
Short name T764
Test name
Test status
Simulation time 4521905019 ps
CPU time 4.39 seconds
Started Jun 10 07:24:28 PM PDT 24
Finished Jun 10 07:24:37 PM PDT 24
Peak memory 201572 kb
Host smart-ff135698-ad59-43e8-ad7e-0c89a37046a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487156748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.2487156748
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.4143374001
Short name T604
Test name
Test status
Simulation time 5671896914 ps
CPU time 3.92 seconds
Started Jun 10 07:24:19 PM PDT 24
Finished Jun 10 07:24:25 PM PDT 24
Peak memory 201608 kb
Host smart-adb659b3-81a7-4098-9622-10aad88c9820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143374001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.4143374001
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.1415820805
Short name T687
Test name
Test status
Simulation time 189301888743 ps
CPU time 98.69 seconds
Started Jun 10 07:24:31 PM PDT 24
Finished Jun 10 07:26:15 PM PDT 24
Peak memory 201632 kb
Host smart-2b4ae708-a60a-4a49-8edb-78884dbceb69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415820805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.1415820805
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.3767816878
Short name T47
Test name
Test status
Simulation time 29290728691 ps
CPU time 35.43 seconds
Started Jun 10 07:24:29 PM PDT 24
Finished Jun 10 07:25:09 PM PDT 24
Peak memory 202120 kb
Host smart-5926d8db-1b5b-41e2-b3b1-5fe25d3649d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767816878 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.3767816878
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.3964781133
Short name T713
Test name
Test status
Simulation time 464507232 ps
CPU time 1.76 seconds
Started Jun 10 07:16:27 PM PDT 24
Finished Jun 10 07:16:33 PM PDT 24
Peak memory 201484 kb
Host smart-8d2b31cc-b338-480f-b794-4a24296900aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964781133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.3964781133
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.734943606
Short name T128
Test name
Test status
Simulation time 197132376753 ps
CPU time 226.31 seconds
Started Jun 10 07:16:29 PM PDT 24
Finished Jun 10 07:20:21 PM PDT 24
Peak memory 201804 kb
Host smart-747fa2f3-f7e3-4a63-9679-b5748c60a291
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734943606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gatin
g.734943606
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.3702876255
Short name T36
Test name
Test status
Simulation time 175931199275 ps
CPU time 440.12 seconds
Started Jun 10 07:16:29 PM PDT 24
Finished Jun 10 07:23:55 PM PDT 24
Peak memory 201764 kb
Host smart-84c6e397-1d29-4b82-a556-76cdd7fcbf9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702876255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.3702876255
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.307927113
Short name T683
Test name
Test status
Simulation time 332813960396 ps
CPU time 526.88 seconds
Started Jun 10 07:16:27 PM PDT 24
Finished Jun 10 07:25:20 PM PDT 24
Peak memory 201892 kb
Host smart-09960e92-b8bd-439d-ad13-2ab17e45d00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307927113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.307927113
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.1433499702
Short name T182
Test name
Test status
Simulation time 484349121241 ps
CPU time 300.47 seconds
Started Jun 10 07:16:26 PM PDT 24
Finished Jun 10 07:21:31 PM PDT 24
Peak memory 201764 kb
Host smart-f0dfac5d-fa68-44b6-8ca7-59fb91802ef3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433499702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.1433499702
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.814106325
Short name T307
Test name
Test status
Simulation time 161990414000 ps
CPU time 399.63 seconds
Started Jun 10 07:16:27 PM PDT 24
Finished Jun 10 07:23:11 PM PDT 24
Peak memory 201796 kb
Host smart-1ff612b9-b0bc-4c3e-8524-d81223b11c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814106325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.814106325
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.1157528942
Short name T637
Test name
Test status
Simulation time 495372029988 ps
CPU time 109.9 seconds
Started Jun 10 07:16:26 PM PDT 24
Finished Jun 10 07:18:21 PM PDT 24
Peak memory 201844 kb
Host smart-8eba134f-ea3b-4e2a-9446-10a21dce144c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157528942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.1157528942
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.223006594
Short name T573
Test name
Test status
Simulation time 358367078579 ps
CPU time 906.9 seconds
Started Jun 10 07:16:28 PM PDT 24
Finished Jun 10 07:31:41 PM PDT 24
Peak memory 201800 kb
Host smart-c4bd60e4-b4cb-418a-b798-3cde762153b0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223006594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_w
akeup.223006594
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.3459728264
Short name T475
Test name
Test status
Simulation time 194585713574 ps
CPU time 62.51 seconds
Started Jun 10 07:16:27 PM PDT 24
Finished Jun 10 07:17:34 PM PDT 24
Peak memory 201788 kb
Host smart-f526e435-aeb5-4f33-93dd-47a0987f150f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459728264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.3459728264
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.2308317211
Short name T473
Test name
Test status
Simulation time 109932915630 ps
CPU time 389.85 seconds
Started Jun 10 07:16:28 PM PDT 24
Finished Jun 10 07:23:03 PM PDT 24
Peak memory 202104 kb
Host smart-c6aef58e-f0b9-48f9-9204-f43905caf005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308317211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.2308317211
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.3428296742
Short name T399
Test name
Test status
Simulation time 35521792795 ps
CPU time 86.07 seconds
Started Jun 10 07:16:28 PM PDT 24
Finished Jun 10 07:17:59 PM PDT 24
Peak memory 201592 kb
Host smart-85eeb602-bd7d-4b7a-9647-8d4a1ac96766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428296742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.3428296742
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.2680014554
Short name T533
Test name
Test status
Simulation time 4565864379 ps
CPU time 5.84 seconds
Started Jun 10 07:16:27 PM PDT 24
Finished Jun 10 07:16:38 PM PDT 24
Peak memory 201648 kb
Host smart-e6178efa-3729-4bc1-b0f7-94bbf1e35687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680014554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.2680014554
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.420772452
Short name T384
Test name
Test status
Simulation time 5878965091 ps
CPU time 16.07 seconds
Started Jun 10 07:16:26 PM PDT 24
Finished Jun 10 07:16:48 PM PDT 24
Peak memory 201676 kb
Host smart-558cf4b3-eecd-4382-90d2-1aeed1ba5fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420772452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.420772452
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.3629850672
Short name T670
Test name
Test status
Simulation time 266219166338 ps
CPU time 302.89 seconds
Started Jun 10 07:16:29 PM PDT 24
Finished Jun 10 07:21:37 PM PDT 24
Peak memory 202168 kb
Host smart-953d6f61-6ced-4d8c-9735-ee2a7a2a5d30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629850672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
3629850672
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.301485411
Short name T60
Test name
Test status
Simulation time 416875007114 ps
CPU time 258.88 seconds
Started Jun 10 07:16:29 PM PDT 24
Finished Jun 10 07:20:53 PM PDT 24
Peak memory 217844 kb
Host smart-8e456655-9063-4a2d-a7c1-9f87213bc81d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301485411 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.301485411
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.4259571684
Short name T434
Test name
Test status
Simulation time 468270233 ps
CPU time 1.68 seconds
Started Jun 10 07:16:26 PM PDT 24
Finished Jun 10 07:16:32 PM PDT 24
Peak memory 201500 kb
Host smart-158e5ef1-c2f9-4cde-94a5-b723e279519d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259571684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.4259571684
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.3070875991
Short name T501
Test name
Test status
Simulation time 173254053684 ps
CPU time 280.29 seconds
Started Jun 10 07:16:28 PM PDT 24
Finished Jun 10 07:21:14 PM PDT 24
Peak memory 201788 kb
Host smart-df0b1c73-ef99-42ad-8e57-58d9301e5d09
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070875991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.3070875991
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.2043557490
Short name T325
Test name
Test status
Simulation time 329598565223 ps
CPU time 757.01 seconds
Started Jun 10 07:16:29 PM PDT 24
Finished Jun 10 07:29:11 PM PDT 24
Peak memory 201944 kb
Host smart-f2ba4731-83db-4612-ae37-8041323de4ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043557490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.2043557490
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.53821042
Short name T364
Test name
Test status
Simulation time 170611882875 ps
CPU time 443.51 seconds
Started Jun 10 07:16:28 PM PDT 24
Finished Jun 10 07:23:57 PM PDT 24
Peak memory 201736 kb
Host smart-18aaa41c-2085-4a0b-9f4a-aad6223aecdf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=53821042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt_
fixed.53821042
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.296635827
Short name T178
Test name
Test status
Simulation time 161797996045 ps
CPU time 370.27 seconds
Started Jun 10 07:16:26 PM PDT 24
Finished Jun 10 07:22:41 PM PDT 24
Peak memory 201780 kb
Host smart-8f9e7043-bc39-42b4-ac5f-8c003aac394a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296635827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.296635827
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.1541913190
Short name T735
Test name
Test status
Simulation time 329651156656 ps
CPU time 770.36 seconds
Started Jun 10 07:16:26 PM PDT 24
Finished Jun 10 07:29:21 PM PDT 24
Peak memory 201816 kb
Host smart-835936d4-9380-4958-a1f2-1c583791686f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541913190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.1541913190
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.2370466299
Short name T358
Test name
Test status
Simulation time 683813821021 ps
CPU time 268.39 seconds
Started Jun 10 07:16:31 PM PDT 24
Finished Jun 10 07:21:04 PM PDT 24
Peak memory 201800 kb
Host smart-ad19a97e-0e3e-4fec-b269-8cafa89be522
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370466299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.2370466299
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.3497918641
Short name T453
Test name
Test status
Simulation time 618260145160 ps
CPU time 348.48 seconds
Started Jun 10 07:16:29 PM PDT 24
Finished Jun 10 07:22:23 PM PDT 24
Peak memory 201864 kb
Host smart-1793a372-9c72-4f7d-9584-6817a5a6f747
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497918641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.3497918641
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.4199567298
Short name T762
Test name
Test status
Simulation time 36293169812 ps
CPU time 85.22 seconds
Started Jun 10 07:16:28 PM PDT 24
Finished Jun 10 07:17:59 PM PDT 24
Peak memory 201572 kb
Host smart-7298d2a8-9cad-4037-bd6b-868407646f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199567298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.4199567298
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.1763981392
Short name T489
Test name
Test status
Simulation time 5186927949 ps
CPU time 3.92 seconds
Started Jun 10 07:16:27 PM PDT 24
Finished Jun 10 07:16:36 PM PDT 24
Peak memory 201616 kb
Host smart-aead496e-5892-45b0-a717-f2a66299d930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763981392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.1763981392
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.3067450539
Short name T543
Test name
Test status
Simulation time 6025752592 ps
CPU time 4.21 seconds
Started Jun 10 07:16:31 PM PDT 24
Finished Jun 10 07:16:40 PM PDT 24
Peak memory 201628 kb
Host smart-1c1ee8cc-ef77-48a4-85fc-d505ccba7dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067450539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.3067450539
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.721917389
Short name T35
Test name
Test status
Simulation time 193407642910 ps
CPU time 221.04 seconds
Started Jun 10 07:16:29 PM PDT 24
Finished Jun 10 07:20:15 PM PDT 24
Peak memory 201940 kb
Host smart-cdb55c75-b94b-4ba2-8eb3-5e1f7b1dcd95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721917389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.721917389
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.181301147
Short name T733
Test name
Test status
Simulation time 371137580 ps
CPU time 1.37 seconds
Started Jun 10 07:16:31 PM PDT 24
Finished Jun 10 07:16:37 PM PDT 24
Peak memory 201308 kb
Host smart-83f97d44-8129-4793-a894-fb690eecfed8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181301147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.181301147
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.3325407826
Short name T316
Test name
Test status
Simulation time 160425477145 ps
CPU time 364.47 seconds
Started Jun 10 07:16:31 PM PDT 24
Finished Jun 10 07:22:40 PM PDT 24
Peak memory 201792 kb
Host smart-35cdc9cb-b3fe-4935-a4aa-216bf60df9db
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325407826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.3325407826
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.418290521
Short name T113
Test name
Test status
Simulation time 199946446928 ps
CPU time 477.57 seconds
Started Jun 10 07:16:30 PM PDT 24
Finished Jun 10 07:24:32 PM PDT 24
Peak memory 201784 kb
Host smart-37497c57-622d-4596-8701-0427b608c4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418290521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.418290521
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.2562812448
Short name T636
Test name
Test status
Simulation time 166545973595 ps
CPU time 79.09 seconds
Started Jun 10 07:16:29 PM PDT 24
Finished Jun 10 07:17:53 PM PDT 24
Peak memory 201928 kb
Host smart-91875f04-7671-40f3-96a7-e564e08056ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562812448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.2562812448
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.1178425741
Short name T511
Test name
Test status
Simulation time 325021204451 ps
CPU time 366.19 seconds
Started Jun 10 07:16:28 PM PDT 24
Finished Jun 10 07:22:40 PM PDT 24
Peak memory 201784 kb
Host smart-adc9255f-057f-4c1d-abe7-0c142320efa3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178425741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.1178425741
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.892626774
Short name T701
Test name
Test status
Simulation time 165233187237 ps
CPU time 176.19 seconds
Started Jun 10 07:16:27 PM PDT 24
Finished Jun 10 07:19:28 PM PDT 24
Peak memory 201824 kb
Host smart-fd0a3062-dabe-40c0-b09f-d95d7ba56b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892626774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.892626774
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.3374960372
Short name T594
Test name
Test status
Simulation time 328742690601 ps
CPU time 65.43 seconds
Started Jun 10 07:16:28 PM PDT 24
Finished Jun 10 07:17:39 PM PDT 24
Peak memory 201800 kb
Host smart-aee4992d-8ec6-4d7c-ad5f-5a6fbc96224a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374960372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.3374960372
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.3630624875
Short name T205
Test name
Test status
Simulation time 179481511999 ps
CPU time 428.46 seconds
Started Jun 10 07:16:29 PM PDT 24
Finished Jun 10 07:23:43 PM PDT 24
Peak memory 201988 kb
Host smart-79a7a16f-7b02-4506-9ea7-0f1f34daa827
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630624875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.3630624875
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.3695128413
Short name T789
Test name
Test status
Simulation time 193110229686 ps
CPU time 122.27 seconds
Started Jun 10 07:16:27 PM PDT 24
Finished Jun 10 07:18:34 PM PDT 24
Peak memory 201900 kb
Host smart-9b47b9a1-674e-4901-a836-46244073c298
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695128413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.3695128413
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.272310850
Short name T236
Test name
Test status
Simulation time 125287772382 ps
CPU time 716.93 seconds
Started Jun 10 07:16:31 PM PDT 24
Finished Jun 10 07:28:33 PM PDT 24
Peak memory 202108 kb
Host smart-eaacf76b-fcdb-4855-a3a3-ecbb0d601427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272310850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.272310850
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.3833913221
Short name T777
Test name
Test status
Simulation time 25999410079 ps
CPU time 33.99 seconds
Started Jun 10 07:16:31 PM PDT 24
Finished Jun 10 07:17:10 PM PDT 24
Peak memory 201600 kb
Host smart-d9b485c8-0eed-49f5-83cb-782c8c958ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833913221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.3833913221
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.1105926641
Short name T372
Test name
Test status
Simulation time 5348970726 ps
CPU time 6.69 seconds
Started Jun 10 07:16:31 PM PDT 24
Finished Jun 10 07:16:43 PM PDT 24
Peak memory 201620 kb
Host smart-67cc1b67-b33b-4e4c-b7b8-75532dd7df25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105926641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.1105926641
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.98149494
Short name T645
Test name
Test status
Simulation time 6227218803 ps
CPU time 1.71 seconds
Started Jun 10 07:16:27 PM PDT 24
Finished Jun 10 07:16:34 PM PDT 24
Peak memory 201748 kb
Host smart-0d68cfc1-5307-4f23-850f-23ffa4138cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98149494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.98149494
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.1084386080
Short name T521
Test name
Test status
Simulation time 335332913632 ps
CPU time 194.98 seconds
Started Jun 10 07:16:32 PM PDT 24
Finished Jun 10 07:19:52 PM PDT 24
Peak memory 201800 kb
Host smart-b849a6b2-aa05-468f-ae6a-7a37669ee3ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084386080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
1084386080
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.3684253722
Short name T232
Test name
Test status
Simulation time 235265919676 ps
CPU time 76.21 seconds
Started Jun 10 07:16:30 PM PDT 24
Finished Jun 10 07:17:51 PM PDT 24
Peak memory 211012 kb
Host smart-86c1b93c-32a5-4e3e-acbc-b8b62954eeec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684253722 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.3684253722
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.2239230665
Short name T480
Test name
Test status
Simulation time 335288426 ps
CPU time 1.43 seconds
Started Jun 10 07:16:37 PM PDT 24
Finished Jun 10 07:16:43 PM PDT 24
Peak memory 201528 kb
Host smart-cd795735-1477-4275-adc9-676bcb1010ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239230665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.2239230665
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.2600170930
Short name T767
Test name
Test status
Simulation time 328910822072 ps
CPU time 184.11 seconds
Started Jun 10 07:16:40 PM PDT 24
Finished Jun 10 07:19:50 PM PDT 24
Peak memory 201792 kb
Host smart-e9cebfc5-d828-47f7-814c-2bea2d9a90e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600170930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.2600170930
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.3597737840
Short name T476
Test name
Test status
Simulation time 486865671231 ps
CPU time 306.39 seconds
Started Jun 10 07:16:37 PM PDT 24
Finished Jun 10 07:21:48 PM PDT 24
Peak memory 201780 kb
Host smart-98c76efc-e369-4694-8111-d9ac05c995b6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597737840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.3597737840
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.2993931733
Short name T223
Test name
Test status
Simulation time 487504375956 ps
CPU time 1061.65 seconds
Started Jun 10 07:16:32 PM PDT 24
Finished Jun 10 07:34:19 PM PDT 24
Peak memory 201812 kb
Host smart-0297e415-5121-47c4-802a-a657190c6404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993931733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.2993931733
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.87461801
Short name T639
Test name
Test status
Simulation time 331456908690 ps
CPU time 802.95 seconds
Started Jun 10 07:16:31 PM PDT 24
Finished Jun 10 07:29:59 PM PDT 24
Peak memory 201620 kb
Host smart-ff1b1167-91f8-4c59-bc60-2423a954372a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=87461801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixed.87461801
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.3112124500
Short name T507
Test name
Test status
Simulation time 178554554066 ps
CPU time 400.14 seconds
Started Jun 10 07:16:40 PM PDT 24
Finished Jun 10 07:23:25 PM PDT 24
Peak memory 201860 kb
Host smart-b478bff7-120d-4cf5-8107-c09bbc89c31d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112124500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.3112124500
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.1680418541
Short name T120
Test name
Test status
Simulation time 207200485136 ps
CPU time 146.62 seconds
Started Jun 10 07:16:38 PM PDT 24
Finished Jun 10 07:19:09 PM PDT 24
Peak memory 201772 kb
Host smart-ae5fa7eb-1599-4da9-876e-903c5cd72f27
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680418541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.1680418541
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.462732185
Short name T67
Test name
Test status
Simulation time 119765557559 ps
CPU time 474.34 seconds
Started Jun 10 07:16:37 PM PDT 24
Finished Jun 10 07:24:35 PM PDT 24
Peak memory 202104 kb
Host smart-2ae4eceb-3b26-45c6-a064-09eea9bed111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462732185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.462732185
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.855762091
Short name T436
Test name
Test status
Simulation time 24535229190 ps
CPU time 35.12 seconds
Started Jun 10 07:16:37 PM PDT 24
Finished Jun 10 07:17:17 PM PDT 24
Peak memory 201624 kb
Host smart-954f1afd-ea07-42f8-bddb-95663c0f22c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855762091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.855762091
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.3659018706
Short name T539
Test name
Test status
Simulation time 4193990809 ps
CPU time 9.81 seconds
Started Jun 10 07:17:04 PM PDT 24
Finished Jun 10 07:17:20 PM PDT 24
Peak memory 201624 kb
Host smart-8d1a417c-130a-4ecc-bebe-ec7366c3ec02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659018706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.3659018706
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.3924039379
Short name T503
Test name
Test status
Simulation time 6002177331 ps
CPU time 4.15 seconds
Started Jun 10 07:16:32 PM PDT 24
Finished Jun 10 07:16:41 PM PDT 24
Peak memory 201620 kb
Host smart-af178909-fd20-47a9-a04a-0892cf677721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924039379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.3924039379
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.1436040214
Short name T555
Test name
Test status
Simulation time 1414175304 ps
CPU time 4.23 seconds
Started Jun 10 07:16:33 PM PDT 24
Finished Jun 10 07:16:42 PM PDT 24
Peak memory 201568 kb
Host smart-1dd31c47-dec4-4239-a428-0756c5712f41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436040214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
1436040214
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.3898492242
Short name T162
Test name
Test status
Simulation time 28076489262 ps
CPU time 89.52 seconds
Started Jun 10 07:16:37 PM PDT 24
Finished Jun 10 07:18:11 PM PDT 24
Peak memory 210488 kb
Host smart-056fd519-6fa3-4717-aae2-5ce9aa8ba9b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898492242 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.3898492242
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.1687170727
Short name T201
Test name
Test status
Simulation time 316605795 ps
CPU time 1.32 seconds
Started Jun 10 07:16:38 PM PDT 24
Finished Jun 10 07:16:44 PM PDT 24
Peak memory 201492 kb
Host smart-ea618f9a-ef1d-4f90-bf88-c8a09e3ce7bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687170727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.1687170727
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.2193076556
Short name T668
Test name
Test status
Simulation time 182432739034 ps
CPU time 432.46 seconds
Started Jun 10 07:16:38 PM PDT 24
Finished Jun 10 07:23:55 PM PDT 24
Peak memory 201880 kb
Host smart-39e44d1f-bf8c-483f-aac3-306ea8d6070a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193076556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.2193076556
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.2670869522
Short name T249
Test name
Test status
Simulation time 181731836649 ps
CPU time 404.98 seconds
Started Jun 10 07:16:38 PM PDT 24
Finished Jun 10 07:23:28 PM PDT 24
Peak memory 201820 kb
Host smart-5b9e5496-154b-4aee-8d6e-bc0e10d11477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670869522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.2670869522
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.1875408742
Short name T338
Test name
Test status
Simulation time 162328032195 ps
CPU time 79.6 seconds
Started Jun 10 07:16:38 PM PDT 24
Finished Jun 10 07:18:02 PM PDT 24
Peak memory 201776 kb
Host smart-3655e584-727d-4c7b-b6e3-fc6d7fc7f9f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875408742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.1875408742
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.3178182903
Short name T725
Test name
Test status
Simulation time 484875829288 ps
CPU time 1079.94 seconds
Started Jun 10 07:16:37 PM PDT 24
Finished Jun 10 07:34:41 PM PDT 24
Peak memory 201816 kb
Host smart-45a20021-1a01-4991-9270-4437f4fb3b1f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178182903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.3178182903
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.2933577128
Short name T614
Test name
Test status
Simulation time 327207571899 ps
CPU time 186.04 seconds
Started Jun 10 07:16:41 PM PDT 24
Finished Jun 10 07:19:52 PM PDT 24
Peak memory 201788 kb
Host smart-46329356-e84d-42a9-aade-908927d540a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933577128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.2933577128
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.1113081455
Short name T54
Test name
Test status
Simulation time 323745378805 ps
CPU time 385.62 seconds
Started Jun 10 07:16:38 PM PDT 24
Finished Jun 10 07:23:08 PM PDT 24
Peak memory 201808 kb
Host smart-c73e7094-b357-4b83-8189-3e6c4cee20fa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113081455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.1113081455
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.913569445
Short name T711
Test name
Test status
Simulation time 566071387281 ps
CPU time 406.13 seconds
Started Jun 10 07:16:36 PM PDT 24
Finished Jun 10 07:23:27 PM PDT 24
Peak memory 201832 kb
Host smart-34edbb5b-2b01-4e0c-a2b8-be19bcc588a1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913569445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_w
akeup.913569445
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.3534115446
Short name T600
Test name
Test status
Simulation time 617232948579 ps
CPU time 271.38 seconds
Started Jun 10 07:16:37 PM PDT 24
Finished Jun 10 07:21:13 PM PDT 24
Peak memory 201832 kb
Host smart-b651512f-b0f1-4e15-aab1-a4a8ce8fff46
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534115446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.3534115446
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.2469402098
Short name T753
Test name
Test status
Simulation time 106476943461 ps
CPU time 443.66 seconds
Started Jun 10 07:16:39 PM PDT 24
Finished Jun 10 07:24:08 PM PDT 24
Peak memory 202180 kb
Host smart-a7b57742-eceb-4c95-bcc7-9b4198a59a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469402098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.2469402098
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.3111759143
Short name T382
Test name
Test status
Simulation time 28417183673 ps
CPU time 15.35 seconds
Started Jun 10 07:16:40 PM PDT 24
Finished Jun 10 07:17:01 PM PDT 24
Peak memory 201608 kb
Host smart-b5a6a6ce-21df-4b0f-b557-975ad8dc4d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111759143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.3111759143
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.254161669
Short name T410
Test name
Test status
Simulation time 3996871705 ps
CPU time 9.26 seconds
Started Jun 10 07:16:37 PM PDT 24
Finished Jun 10 07:16:50 PM PDT 24
Peak memory 201616 kb
Host smart-64be6f20-f304-41a4-b2c4-32a4dc7c39d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254161669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.254161669
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.1458849602
Short name T606
Test name
Test status
Simulation time 5821352703 ps
CPU time 2.91 seconds
Started Jun 10 07:16:37 PM PDT 24
Finished Jun 10 07:16:44 PM PDT 24
Peak memory 201644 kb
Host smart-e7d5d312-cd77-47ac-807e-eb7054461cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458849602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.1458849602
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.770244203
Short name T313
Test name
Test status
Simulation time 173493128560 ps
CPU time 237.91 seconds
Started Jun 10 07:16:38 PM PDT 24
Finished Jun 10 07:20:41 PM PDT 24
Peak memory 218388 kb
Host smart-44bf6c6f-24b6-4c8f-a3d6-e9c91c7d4fd1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770244203 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.770244203
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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