Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7275	1			T1	47		T2	18		T6	20
testmodes[AdcCtrlTestmodeNormal]	5968	1			T1	52		T2	13		T5	1
testmodes[AdcCtrlTestmodeLowpower]	5939	1			T1	48		T2	1		T3	10
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3833	1			T1	11		T2	9		T6	19
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1876	1			T1	18		T2	9		T9	18
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1451	1			T1	17		T9	9		T41	19
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1887	1			T1	17		T2	9		T9	19
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2276	1			T1	17		T2	3		T9	19
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1480	1			T1	18		T5	1		T9	10
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1447	1			T1	19		T9	8		T41	17
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1472	1			T1	17		T2	1		T5	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2762	1			T1	12		T3	9		T4	16