Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27519

1

T1

158

T2

34

T3

10

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23995

1

T1

158

T2

29

T3

10

auto[ADC_CTRL_FILTER_COND_OUT]

3524

1

T2

5

T5

17

T9

25

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21321

1

T1

158

T2

29

T3

10

auto[1]

6198

1

T2

5

T5

17

T7

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23361

1

T1

149

T2

33

T3

10

auto[1]

4158

1

T1

9

T2

1

T5

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	68	1			T104	3		T212	27		T213	20
values[1]	809	1			T11	3		T31	3		T214	10
values[2]	633	1			T9	8		T104	14		T42	10
values[3]	657	1			T13	6		T138	26		T129	7
values[4]	3069	1			T1	12		T2	2		T7	1
values[5]	723	1			T12	1		T13	11		T54	13
values[6]	753	1			T140	1		T16	9		T27	1
values[7]	765	1			T2	3		T5	6		T8	24
values[8]	627	1			T9	16		T12	1		T13	13
values[9]	1181	1			T5	27		T9	1		T39	24
minimum	18234	1			T1	146		T2	29		T3	10

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1039	1			T9	8		T11	3		T104	3
values[1]	610	1			T42	10		T44	1		T141	12
values[2]	745	1			T11	14		T13	6		T48	20
values[3]	3052	1			T1	12		T2	2		T7	1
values[4]	687	1			T54	13		T16	9		T141	5
values[5]	826	1			T8	24		T140	1		T27	1
values[6]	768	1			T2	3		T5	6		T13	13
values[7]	555	1			T12	1		T54	10		T39	12
values[8]	875	1			T5	27		T9	17		T39	12
values[9]	127	1			T100	22		T51	2		T215	14
minimum	18235	1			T1	146		T2	29		T3	10

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23340

1

T1

156

T2

33

T3

10

auto[1]

4179

1

T1

2

T2

1

T5

17

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T31	2		T157	12		T163	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T9	2		T11	1		T104	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T44	1		T141	12		T142	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T42	10		T102	1		T143	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T11	8		T13	6		T104	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T48	11		T138	14		T129	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1612	1			T1	3		T7	1		T12	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T2	2		T48	4		T137	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T49	1		T149	1		T144	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T54	13		T16	6		T141	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T8	12		T140	1		T27	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T49	5		T98	1		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T5	6		T44	1		T214	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T2	2		T13	13		T27	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T42	6		T47	9		T216	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T12	1		T54	10		T39	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T5	5		T61	4		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T5	9		T9	6		T39	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T100	11		T51	1		T215	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T217	2		T147	1		T151	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18098	1			T1	146		T2	29		T3	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T218	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T31	1		T157	4		T138	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T9	6		T11	2		T104	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T142	3		T150	14		T219	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T102	11		T143	10		T220	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T11	6		T104	13		T221	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T48	9		T138	12		T129	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1062	1			T1	9		T14	20		T40	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T48	13		T95	7		T204	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T149	10		T144	7		T201	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T16	3		T222	4		T133	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T8	12		T163	14		T174	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T49	4		T192	5		T183	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T44	14		T214	8		T142	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T2	1		T223	19		T130	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T47	4		T52	5		T224	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T158	9		T130	16		T100	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T5	5		T61	8		T157	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T5	8		T9	11		T214	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T100	11		T51	1		T215	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T217	4		T151	10		T225	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T35	1		T44	3		T47	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T212	13		T213	10		T226	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T104	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T31	2		T157	12		T163	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T11	1		T214	1		T163	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T104	1		T44	1		T141	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T9	2		T42	10		T61	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T13	6		T222	8		T144	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T138	14		T129	6		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1643	1			T1	3		T7	1		T11	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T2	2		T48	15		T131	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T12	1		T13	11		T227	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T54	13		T137	14		T215	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T140	1		T27	1		T174	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T16	6		T141	5		T228	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T5	6		T8	12		T44	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T2	2		T27	1		T130	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T42	6		T214	1		T143	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T9	5		T12	1		T13	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	371	1			T5	5		T61	4		T47	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T5	9		T9	1		T39	24
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18098	1			T1	146		T2	29		T3	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T212	14		T213	10		T226	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T104	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T31	1		T157	4		T138	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T11	2		T214	9		T188	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T104	13		T142	3		T150	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T9	6		T61	1		T102	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T219	4		T221	15		T229	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T138	12		T129	1		T230	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1080	1			T1	9		T11	6		T14	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T48	22		T95	7		T149	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T227	2		T201	11		T221	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T231	6		T224	12		T232	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T174	2		T102	6		T149	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T16	3		T222	4		T133	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T8	12		T44	14		T163	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T2	1		T130	6		T49	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T214	8		T143	18		T52	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T9	11		T158	9		T223	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	306	1			T5	5		T61	8		T47	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T5	8		T214	4		T130	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T35	1		T44	3		T47	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T31	3		T157	5		T163	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T9	7		T11	3		T104	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T44	1		T141	2		T142	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T42	1		T102	12		T143	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T11	7		T13	1		T104	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T48	10		T138	13		T129	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1410	1			T1	10		T7	1		T12	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T2	2		T48	14		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T49	1		T149	11		T144	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T54	1		T16	4		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T8	13		T140	1		T27	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T49	5		T98	1		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T5	1		T44	15		T214	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T2	2		T13	1		T27	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T42	1		T47	7		T216	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T12	1		T54	1		T39	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T5	6		T61	9		T157	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T5	9		T9	13		T39	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T100	12		T51	2		T215	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T217	6		T147	1		T151	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18234	1			T1	146		T2	29		T3	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T218	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T157	11		T163	14		T138	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T9	1		T163	1		T233	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T141	10		T142	3		T137	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T42	9		T143	10		T220	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T11	7		T13	5		T222	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T48	10		T138	13		T129	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1264	1			T1	2		T13	10		T136	43
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T48	3		T137	13		T95	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T144	10		T146	11		T201	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T54	12		T16	5		T141	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T8	11		T163	15		T174	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T49	4		T178	9		T192	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T5	5		T142	2		T49	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T2	1		T13	12		T223	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T42	5		T47	6		T52	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T54	9		T39	11		T130	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T5	4		T61	3		T138	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T5	8		T9	4		T39	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T100	10		T179	12		T234	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T225	6		T235	1		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	8	40	83.33	8

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T212	15		T213	11		T226	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T104	3		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T31	3		T157	5		T163	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T11	3		T214	10		T163	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T104	14		T44	1		T141	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T9	7		T42	1		T61	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T13	1		T222	1		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T138	13		T129	2		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1425	1			T1	10		T7	1		T11	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T2	2		T48	24		T131	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T12	1		T13	1		T227	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T54	1		T137	1		T215	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T140	1		T27	1		T174	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T16	4		T141	1		T228	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T5	1		T8	13		T44	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T2	2		T27	1		T130	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T42	1		T214	9		T143	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T9	12		T12	1		T13	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	375	1			T5	6		T61	9		T47	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T5	9		T9	1		T39	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18234	1			T1	146		T2	29		T3	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T212	12		T213	9		T226	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T157	11		T163	14		T138	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T163	1		T233	7		T228	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T141	10		T142	3		T137	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T9	1		T42	9		T222	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T13	5		T222	7		T144	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T138	13		T129	5		T236	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1298	1			T1	2		T11	7		T136	43
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T48	13		T95	7		T144	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T13	10		T201	11		T237	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T54	12		T137	13		T178	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T174	3		T228	10		T144	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T16	5		T141	4		T228	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T5	5		T8	11		T163	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T2	1		T130	8		T49	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T42	5		T143	12		T52	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T9	4		T13	12		T54	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T5	4		T61	3		T47	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T5	8		T39	22		T130	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23340

1

T1

156

T2

33

T3

10

auto[1]

auto[0]

4179

1

T1

2

T2

1

T5

17

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27519

1

T1

158

T2

34

T3

10

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23873

1

T1

158

T2

31

T3

10

auto[ADC_CTRL_FILTER_COND_OUT]

3646

1

T2

3

T5

16

T8

24

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21313

1

T1

146

T2

31

T3

10

auto[1]

6206

1

T1

12

T2

3

T5

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23361

1

T1

149

T2

33

T3

10

auto[1]

4158

1

T1

9

T2

1

T5

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	33	1			T202	7		T238	8		T239	10
values[0]	45	1			T231	6		T240	7		T90	18
values[1]	682	1			T11	3		T140	1		T44	15
values[2]	713	1			T9	9		T39	12		T44	1
values[3]	786	1			T1	12		T5	10		T8	24
values[4]	496	1			T13	6		T104	3		T42	6
values[5]	645	1			T2	3		T48	20		T54	13
values[6]	713	1			T2	2		T214	15		T157	2
values[7]	692	1			T61	2		T157	16		T138	11
values[8]	3001	1			T7	1		T11	14		T14	22
values[9]	1479	1			T5	23		T12	2		T13	24
minimum	18234	1			T1	146		T2	29		T3	10

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	938	1			T11	3		T140	1		T39	12
values[1]	659	1			T5	10		T8	24		T9	9
values[2]	781	1			T1	12		T9	16		T104	3
values[3]	486	1			T2	3		T13	6		T39	12
values[4]	710	1			T2	2		T48	20		T54	13
values[5]	648	1			T214	10		T157	2		T138	12
values[6]	3145	1			T7	1		T11	14		T14	22
values[7]	632	1			T141	5		T163	15		T98	1
values[8]	1006	1			T5	23		T12	2		T13	11
values[9]	273	1			T13	13		T54	10		T47	13
minimum	18241	1			T1	146		T2	29		T3	10

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23340

1

T1

156

T2

33

T3

10

auto[1]

4179

1

T1

2

T2

1

T5

17

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T140	1		T39	12		T44	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T11	1		T137	12		T130	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T9	3		T61	4		T27	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T5	5		T8	12		T44	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T1	3		T104	1		T141	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T9	5		T42	16		T16	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T13	6		T39	12		T129	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T2	2		T150	1		T132	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T2	2		T48	11		T54	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T27	1		T214	1		T241	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T214	1		T157	1		T97	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T138	10		T158	1		T223	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1710	1			T7	1		T11	8		T14	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T61	1		T138	6		T222	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T163	15		T201	12		T19	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T141	5		T98	1		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T5	9		T12	1		T104	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	354	1			T5	6		T12	1		T13	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T13	13		T214	1		T150	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T54	10		T47	9		T36	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18098	1			T1	146		T2	29		T3	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T240	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T44	14		T163	14		T17	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T11	2		T130	16		T49	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T9	6		T61	8		T142	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T5	5		T8	12		T223	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T1	9		T104	2		T150	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T9	11		T138	12		T102	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T129	1		T95	4		T227	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T2	1		T150	4		T52	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T48	9		T149	8		T222	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T214	4		T241	2		T135	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T214	9		T157	1		T97	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T138	2		T158	9		T223	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1115	1			T11	6		T14	20		T40	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T61	1		T138	5		T222	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T201	11		T220	1		T225	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T135	14		T242	8		T243	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T5	8		T104	13		T16	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T48	13		T129	3		T100	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T214	8		T150	9		T244	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T47	4		T36	3		T245	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T35	1		T44	3		T47	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T240	2		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T202	1		T238	3		T239	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T231	1		T240	5		T90	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T140	1		T44	1		T141	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T11	1		T137	12		T130	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T9	3		T39	12		T27	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T44	1		T223	13		T98	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T1	3		T39	12		T61	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T5	5		T8	12		T9	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T13	6		T104	1		T163	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T42	6		T150	1		T132	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T48	11		T54	13		T129	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T2	2		T27	1		T223	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T2	2		T214	1		T157	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T214	1		T138	10		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T157	12		T49	5		T95	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T61	1		T138	6		T132	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1649	1			T7	1		T11	8		T14	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T141	5		T129	5		T98	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	328	1			T5	9		T12	1		T13	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	515	1			T5	6		T12	1		T13	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18098	1			T1	146		T2	29		T3	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T202	6		T238	5		T235	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T231	5		T240	2		T90	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T44	14		T163	14		T17	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T11	2		T130	16		T49	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T9	6		T142	3		T174	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T223	13		T102	6		T188	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T1	9		T61	8		T150	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T5	5		T8	12		T9	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T104	2		T95	4		T227	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T150	4		T52	5		T246	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T48	9		T129	1		T149	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T2	1		T223	6		T241	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T214	9		T157	1		T174	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T214	4		T138	2		T158	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T157	4		T49	4		T95	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T61	1		T138	5		T133	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1087	1			T11	6		T14	20		T40	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T129	3		T222	2		T215	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T5	8		T104	13		T214	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	363	1			T48	13		T47	4		T100	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T35	1		T44	3		T47	1