Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27519

1

T1

158

T2

34

T3

10

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23865

1

T1

146

T2

34

T3

10

auto[ADC_CTRL_FILTER_COND_OUT]

3654

1

T1

12

T5

6

T9

16

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21472

1

T1

158

T2

34

T3

10

auto[1]

6047

1

T7

1

T8

24

T9

9

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23361

1

T1

149

T2

33

T3

10

auto[1]

4158

1

T1

9

T2

1

T5

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	68	1			T39	12		T247	23		T90	32
values[0]	79	1			T39	12		T129	7		T100	22
values[1]	918	1			T2	3		T13	11		T54	13
values[2]	660	1			T1	12		T5	17		T11	3
values[3]	690	1			T13	19		T104	3		T44	1
values[4]	564	1			T140	1		T54	10		T142	10
values[5]	3016	1			T2	2		T7	1		T9	8
values[6]	656	1			T9	17		T11	14		T48	20
values[7]	670	1			T5	6		T8	24		T48	17
values[8]	659	1			T5	10		T61	2		T214	5
values[9]	1305	1			T42	6		T16	3		T157	2
minimum	18234	1			T1	146		T2	29		T3	10

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1150	1			T1	12		T2	3		T12	1
values[1]	709	1			T5	17		T11	3		T13	6
values[2]	626	1			T44	1		T95	6		T149	9
values[3]	3008	1			T2	2		T7	1		T13	13
values[4]	572	1			T9	8		T12	1		T42	10
values[5]	690	1			T5	6		T9	17		T11	14
values[6]	713	1			T8	24		T48	20		T47	13
values[7]	659	1			T5	10		T61	2		T214	5
values[8]	853	1			T16	3		T157	2		T138	12
values[9]	304	1			T39	12		T42	6		T233	8
minimum	18235	1			T1	146		T2	29		T3	10

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23340

1

T1

156

T2

33

T3

10

auto[1]

4179

1

T1

2

T2

1

T5

17

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	326	1			T2	2		T12	1		T13	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T1	3		T39	12		T61	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T5	9		T11	1		T13	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T97	1		T185	1		T188	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T44	1		T247	1		T248	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T95	3		T149	1		T222	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1605	1			T2	2		T7	1		T14	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T13	13		T137	14		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T9	2		T12	1		T42	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T44	1		T138	14		T223	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T9	1		T11	8		T16	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T5	6		T9	5		T48	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T8	12		T48	11		T163	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T47	9		T214	1		T131	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T5	5		T137	12		T131	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T61	1		T214	1		T157	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T16	3		T130	20		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T157	1		T138	10		T241	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T289	14		T183	10		T209	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T39	12		T42	6		T233	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18098	1			T1	146		T2	29		T3	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T306	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T2	1		T142	3		T174	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T1	9		T61	8		T163	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T5	8		T11	2		T104	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T97	14		T188	11		T51	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T248	3		T20	3		T203	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T95	3		T149	8		T222	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1025	1			T14	20		T104	13		T40	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T158	9		T49	18		T227	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T9	6		T31	1		T174	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T44	14		T138	12		T223	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T11	6		T16	3		T36	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T9	11		T48	13		T214	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T8	12		T48	9		T129	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T47	4		T214	9		T51	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T5	5		T289	15		T225	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T61	1		T214	4		T157	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T130	22		T149	10		T150	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T157	1		T138	2		T241	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T183	11		T209	1		T180	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T159	14		T177	13		T25	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T35	1		T44	3		T47	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T247	14		T239	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T39	12		T90	17		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T100	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T39	12		T129	6		T307	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T2	2		T13	11		T54	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T163	16		T228	11		T100	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T5	9		T11	1		T12	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T1	3		T61	4		T185	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T13	6		T104	1		T44	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T13	13		T95	3		T97	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T140	1		T54	10		T142	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T137	14		T49	23		T98	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1625	1			T2	2		T7	1		T9	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T138	14		T158	1		T52	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T9	1		T11	8		T48	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T9	5		T44	1		T214	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T8	12		T16	6		T163	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T5	6		T48	4		T47	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T5	5		T137	12		T129	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T61	1		T214	1		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	326	1			T16	3		T130	20		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	392	1			T42	6		T157	1		T138	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18098	1			T1	146		T2	29		T3	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T247	9		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T90	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T100	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T129	1		T307	13		T308	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T2	1		T142	3		T174	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T163	14		T100	2		T102	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T5	8		T11	2		T18	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T1	9		T61	8		T17	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T104	2		T52	5		T254	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T95	3		T97	14		T149	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T142	7		T138	5		T133	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T49	18		T227	5		T52	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1086	1			T9	6		T14	20		T104	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T138	12		T158	9		T52	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T11	6		T48	9		T36	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T9	11		T44	14		T214	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T8	12		T16	3		T102	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T48	13		T47	4		T214	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T5	5		T129	3		T95	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T61	1		T214	4		T159	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T130	22		T149	10		T150	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T157	1		T138	2		T241	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T35	1		T44	3		T47	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T2	2		T12	1		T13	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	363	1			T1	10		T39	1		T61	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T5	9		T11	3		T13	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T97	15		T185	1		T188	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T44	1		T247	1		T248	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T95	4		T149	9		T222	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1371	1			T2	2		T7	1		T14	22
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T13	1		T137	1		T158	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T9	7		T12	1		T42	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T44	15		T138	13		T223	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T9	1		T11	7		T16	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T5	1		T9	12		T48	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T8	13		T48	10		T163	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T47	7		T214	10		T131	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T5	6		T137	1		T131	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T61	2		T214	5		T157	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T16	3		T130	24		T149	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T157	2		T138	3		T241	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T289	1		T183	12		T209	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T39	1		T42	1		T233	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18234	1			T1	146		T2	29		T3	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T306	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T2	1		T13	10		T54	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T1	2		T39	11		T61	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T5	8		T13	5		T141	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T178	9		T309	10		T161	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T248	3		T20	1		T310	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T95	2		T222	10		T17	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1259	1			T54	9		T136	43		T26	26
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T13	12		T137	13		T49	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T9	1		T42	9		T174	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T138	13		T223	12		T128	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T11	7		T16	5		T36	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T5	5		T9	4		T48	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T8	11		T48	10		T163	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T47	6		T228	26		T51	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T5	4		T137	11		T144	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T157	11		T159	14		T219	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T130	18		T18	1		T282	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T138	9		T256	8		T164	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T289	13		T183	9		T209	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T39	11		T42	5		T233	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T247	10		T239	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T39	1		T90	16		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T100	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T39	1		T129	2		T307	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T2	2		T13	1		T54	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T163	15		T228	1		T100	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T5	9		T11	3		T12	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T1	10		T61	9		T185	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T13	1		T104	3		T44	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T13	1		T95	4		T97	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T140	1		T54	1		T142	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T137	1		T49	23		T98	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1446	1			T2	2		T7	1		T9	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T138	13		T158	10		T52	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T9	1		T11	7		T48	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T9	12		T44	15		T214	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T8	13		T16	4		T163	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T5	1		T48	14		T47	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T5	6		T137	1		T129	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T61	2		T214	5		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	329	1			T16	3		T130	24		T149	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	389	1			T42	1		T157	2		T138	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18234	1			T1	146		T2	29		T3	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T247	13		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T39	11		T90	16		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T100	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T39	11		T129	5		T307	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T2	1		T13	10		T54	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T163	15		T228	10		T224	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T5	8		T18	2		T146	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T1	2		T61	3		T17	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T13	5		T260	17		T52	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T13	12		T95	2		T222	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T54	9		T142	2		T138	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T137	13		T49	18		T222	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1265	1			T9	1		T136	43		T26	26
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T138	13		T52	4		T176	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T11	7		T48	10		T42	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T9	4		T163	14		T223	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T8	11		T16	5		T163	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T5	5		T48	3		T47	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T5	4		T137	11		T129	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T159	14		T237	6		T221	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T130	18		T18	1		T144	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T42	5		T138	9		T233	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23340

1

T1

156

T2

33

T3

10

auto[1]

auto[0]

4179

1

T1

2

T2

1

T5

17