Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27519

1

T1

158

T2

34

T3

10

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23836

1

T1

158

T2

31

T3

10

auto[ADC_CTRL_FILTER_COND_OUT]

3683

1

T2

3

T5

16

T8

24

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21297

1

T1

146

T2

31

T3

10

auto[1]

6222

1

T1

12

T2

3

T5

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23361

1

T1

149

T2

33

T3

10

auto[1]

4158

1

T1

9

T2

1

T5

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	375	1			T48	17		T47	13		T131	1
values[0]	45	1			T231	6		T240	7		T90	18
values[1]	677	1			T11	3		T140	1		T44	15
values[2]	818	1			T9	9		T39	12		T44	1
values[3]	695	1			T1	12		T5	10		T8	24
values[4]	428	1			T13	6		T104	3		T39	12
values[5]	698	1			T2	3		T48	20		T54	13
values[6]	710	1			T2	2		T214	15		T157	2
values[7]	775	1			T61	2		T31	3		T157	16
values[8]	2885	1			T7	1		T11	14		T14	22
values[9]	1179	1			T5	23		T12	2		T13	24
minimum	18234	1			T1	146		T2	29		T3	10

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	706	1			T11	3		T140	1		T44	15
values[1]	751	1			T5	10		T9	9		T39	12
values[2]	742	1			T1	12		T8	24		T9	16
values[3]	488	1			T2	3		T13	6		T39	12
values[4]	713	1			T2	2		T48	20		T54	13
values[5]	712	1			T214	10		T157	2		T138	23
values[6]	3095	1			T7	1		T14	22		T105	2
values[7]	639	1			T11	14		T141	5		T163	15
values[8]	1024	1			T5	23		T12	2		T13	11
values[9]	246	1			T13	13		T54	10		T150	10
minimum	18403	1			T1	146		T2	29		T3	10

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23340

1

T1

156

T2

33

T3

10

auto[1]

4179

1

T1

2

T2

1

T5

17

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T140	1		T44	1		T141	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T11	1		T137	12		T130	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T9	3		T27	1		T142	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T5	5		T39	12		T44	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T1	3		T104	1		T141	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T8	12		T9	5		T42	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T13	6		T39	12		T163	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T2	2		T42	6		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T2	2		T48	11		T54	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T27	1		T214	1		T241	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T214	1		T157	1		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T138	16		T223	3		T18	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1700	1			T7	1		T14	2		T105	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T61	1		T222	11		T132	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T11	8		T163	15		T201	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T141	5		T98	1		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T5	9		T12	1		T104	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T5	6		T12	1		T13	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T13	13		T150	1		T244	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T54	10		T36	11		T133	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18133	1			T1	146		T2	29		T3	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T131	1		T231	1		T21	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T44	14		T163	14		T17	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T11	2		T130	16		T49	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T9	6		T142	3		T174	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T5	5		T61	8		T223	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T1	9		T104	2		T95	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T8	12		T9	11		T138	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T129	1		T227	5		T164	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T2	1		T150	4		T52	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T48	9		T149	8		T222	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T214	4		T241	2		T135	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T214	9		T157	1		T158	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T138	7		T223	6		T18	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1109	1			T14	20		T40	17		T43	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T61	1		T222	2		T133	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T11	6		T201	11		T220	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T135	14		T242	8		T243	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T5	8		T104	13		T16	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T48	13		T47	4		T129	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T150	9		T244	9		T311	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T36	3		T133	13		T183	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T35	1		T44	3		T47	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T231	5		T179	7		T312	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T227	1		T244	14		T202	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T48	4		T47	9		T131	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T313	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T231	1		T240	5		T90	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T140	1		T44	1		T141	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T11	1		T137	12		T130	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T9	3		T27	1		T142	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T39	12		T44	1		T61	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T1	3		T141	7		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T5	5		T8	12		T9	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T13	6		T104	1		T39	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T42	6		T150	1		T132	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T48	11		T54	13		T129	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T2	2		T27	1		T223	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T2	2		T214	1		T157	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T214	1		T138	16		T18	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T31	2		T157	12		T174	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T61	1		T132	10		T133	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1618	1			T7	1		T11	8		T14	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T98	1		T149	1		T222	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T5	9		T12	1		T13	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	390	1			T5	6		T12	1		T13	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18098	1			T1	146		T2	29		T3	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T227	2		T244	9		T202	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T48	13		T47	4		T36	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T313	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T231	5		T240	2		T90	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T44	14		T163	14		T17	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T11	2		T130	16		T49	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T9	6		T142	3		T174	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T61	8		T223	13		T130	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T1	9		T150	14		T224	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T5	5		T8	12		T9	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T104	2		T95	4		T227	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T150	4		T52	5		T246	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T48	9		T129	1		T149	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T2	1		T223	6		T241	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T214	9		T157	1		T97	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T214	4		T138	7		T18	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T31	1		T157	4		T174	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T61	1		T133	6		T232	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1035	1			T11	6		T14	20		T40	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T222	2		T215	13		T242	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T5	8		T104	13		T16	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T129	3		T100	11		T149	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T35	1		T44	3		T47	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T140	1		T44	15		T141	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T11	3		T137	1		T130	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T9	8		T27	1		T142	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T5	6		T39	1		T44	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T1	10		T104	3		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T8	13		T9	12		T42	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T13	1		T39	1		T163	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T2	2		T42	1		T150	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T2	2		T48	10		T54	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T27	1		T214	5		T241	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T214	10		T157	2		T158	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T138	9		T223	7		T18	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1463	1			T7	1		T14	22		T105	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T61	2		T222	3		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T11	7		T163	1		T201	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T141	1		T98	1		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T5	9		T12	1		T104	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T5	1		T12	1		T13	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T13	1		T150	10		T244	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T54	1		T36	4		T133	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18284	1			T1	146		T2	29		T3	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T131	1		T231	6		T21	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T141	4		T163	15		T17	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T137	11		T130	10		T228	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T9	1		T142	3		T137	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T5	4		T39	11		T61	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T1	2		T141	6		T95	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T8	11		T9	4		T42	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T13	5		T39	11		T163	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T2	1		T42	5		T132	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T48	10		T54	12		T228	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T146	11		T135	11		T247	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T143	12		T256	8		T52	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T138	14		T223	2		T18	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1346	1			T136	43		T26	26		T157	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T222	10		T132	9		T133	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T11	7		T163	14		T201	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T141	4		T135	12		T19	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T5	8		T16	5		T142	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T5	5		T13	10		T48	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T13	12		T244	13		T314	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T54	9		T36	10		T133	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T144	14		T265	11		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T179	7		T312	6		T315	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T227	3		T244	10		T202	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T48	14		T47	7		T131	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T313	14		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T231	6		T240	3		T90	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T140	1		T44	15		T141	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T11	3		T137	1		T130	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T9	8		T27	1		T142	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T39	1		T44	1		T61	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T1	10		T141	1		T150	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T5	6		T8	13		T9	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T13	1		T104	3		T39	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T42	1		T150	5		T132	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T48	10		T54	1		T129	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T2	2		T27	1		T223	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T2	2		T214	10		T157	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T214	5		T138	9		T18	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T31	3		T157	5		T174	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T61	2		T132	1		T133	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1380	1			T7	1		T11	7		T14	22
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T98	1		T149	1		T222	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	319	1			T5	9		T12	1		T13	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T5	1		T12	1		T13	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18234	1			T1	146		T2	29		T3	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T244	13		T246	2		T183	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T48	3		T47	6		T36	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T240	4		T90	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T141	4		T163	15		T17	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T137	11		T130	10		T228	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T9	1		T142	3		T137	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T39	11		T61	3		T223	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T1	2		T141	6		T146	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T5	4		T8	11		T9	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T13	5		T39	11		T163	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T42	5		T132	14		T52	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T48	10		T54	12		T129	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T2	1		T223	2		T146	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T143	10		T256	8		T52	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T138	14		T18	3		T146	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T157	11		T174	3		T233	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T132	9		T133	9		T282	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1273	1			T11	7		T136	43		T26	26
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T222	10		T19	5		T242	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T5	8		T13	12		T16	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T5	5		T13	10		T54	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23340

1

T1

156

T2

33

T3

10

auto[1]

auto[0]

4179

1

T1

2

T2

1

T5

17