Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27519

1

T1

158

T2

34

T3

10

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21456

1

T1

146

T2

34

T3

10

auto[ADC_CTRL_FILTER_COND_OUT]

6063

1

T1

12

T5

23

T7

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21361

1

T1

146

T2

34

T3

10

auto[1]

6158

1

T1

12

T5

10

T7

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23361

1

T1

149

T2

33

T3

10

auto[1]

4158

1

T1

9

T2

1

T5

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	342	1			T42	6		T130	15		T50	6
values[0]	54	1			T5	10		T271	30		T83	12
values[1]	829	1			T13	13		T42	10		T16	3
values[2]	800	1			T9	16		T48	17		T140	1
values[3]	590	1			T2	2		T5	6		T11	3
values[4]	510	1			T9	8		T12	1		T27	1
values[5]	852	1			T2	3		T13	6		T48	20
values[6]	656	1			T1	12		T5	17		T104	3
values[7]	588	1			T11	14		T16	9		T129	7
values[8]	761	1			T8	24		T9	1		T12	1
values[9]	3303	1			T7	1		T14	22		T54	13
minimum	18234	1			T1	146		T2	29		T3	10

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	814	1			T9	16		T13	13		T39	12
values[1]	3138	1			T7	1		T11	3		T14	22
values[2]	552	1			T2	2		T5	6		T39	12
values[3]	509	1			T9	8		T12	1		T163	30
values[4]	933	1			T2	3		T5	17		T13	6
values[5]	697	1			T1	12		T11	14		T104	3
values[6]	568	1			T9	1		T129	7		T49	1
values[7]	648	1			T8	24		T12	1		T13	11
values[8]	974	1			T42	6		T61	12		T31	3
values[9]	206	1			T130	15		T100	22		T50	6
minimum	18480	1			T1	146		T2	29		T3	10

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23340

1

T1

156

T2

33

T3

10

auto[1]

4179

1

T1

2

T2

1

T5

17

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T13	13		T157	1		T158	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T9	5		T39	12		T61	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T11	1		T48	4		T174	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1665	1			T7	1		T14	2		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T2	2		T39	12		T27	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T5	6		T44	1		T138	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T9	2		T163	16		T97	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T12	1		T102	2		T52	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T2	2		T13	6		T104	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T5	9		T48	11		T54	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T11	8		T47	9		T142	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T1	3		T104	1		T16	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T49	1		T98	1		T51	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T9	1		T129	6		T145	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T8	12		T12	1		T13	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T54	13		T27	1		T142	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T42	6		T31	2		T49	23
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T61	4		T214	1		T138	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T100	11		T50	4		T178	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T130	9		T272	1		T274	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18148	1			T1	146		T2	29		T3	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T42	10		T216	1		T164	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T157	1		T158	9		T149	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T9	11		T61	1		T214	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T11	2		T48	13		T174	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1135	1			T14	20		T40	17		T43	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T157	4		T100	2		T144	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T138	2		T95	3		T201	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T9	6		T163	14		T97	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T102	17		T52	5		T220	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T2	1		T104	13		T223	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T5	8		T48	9		T214	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T11	6		T47	4		T142	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T1	9		T104	2		T16	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T51	1		T18	1		T256	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T129	1		T145	2		T176	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T8	12		T222	2		T215	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T142	7		T143	18		T202	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T31	1		T49	18		T144	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T61	8		T214	9		T138	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T100	11		T50	2		T161	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T130	6		T272	13		T274	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T5	5		T35	1		T44	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T164	10		T204	18		T160	15

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T42	6		T50	4		T159	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T130	9		T133	12		T236	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T5	5		T271	15		T83	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T275	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T13	13		T157	1		T131	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T42	10		T16	3		T141	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T48	4		T174	10		T158	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T9	5		T140	1		T39	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T2	2		T11	1		T39	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T5	6		T44	2		T141	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T9	2		T27	1		T97	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T12	1		T102	1		T52	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T2	2		T13	6		T104	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T48	11		T54	10		T163	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T47	9		T142	4		T223	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T1	3		T5	9		T104	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T11	8		T49	1		T98	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T16	6		T129	6		T233	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T8	12		T12	1		T13	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T9	1		T143	13		T144	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T31	2		T49	23		T100	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1678	1			T7	1		T14	2		T54	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18098	1			T1	146		T2	29		T3	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T50	2		T159	14		T161	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T130	6		T133	11		T236	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T5	5		T271	15		T83	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T275	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T157	1		T149	10		T143	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T18	1		T164	10		T204	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T48	13		T174	14		T158	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T9	11		T61	1		T214	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T11	2		T157	4		T95	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T44	14		T138	2		T174	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T9	6		T97	14		T188	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T102	11		T52	5		T220	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T2	1		T104	13		T163	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T48	9		T138	5		T130	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T47	4		T142	3		T223	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T1	9		T5	8		T104	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T11	6		T51	1		T18	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T16	3		T129	1		T145	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T8	12		T222	2		T215	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T143	18		T202	6		T231	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T31	1		T49	18		T100	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1184	1			T14	20		T40	17		T43	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T35	1		T44	3		T47	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T13	1		T157	2		T158	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T9	12		T39	1		T61	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T11	3		T48	14		T174	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1491	1			T7	1		T14	22		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T2	2		T39	1		T27	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T5	1		T44	1		T138	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T9	7		T163	15		T97	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T12	1		T102	19		T52	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T2	2		T13	1		T104	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T5	9		T48	10		T54	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T11	7		T47	7		T142	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T1	10		T104	3		T16	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T49	1		T98	1		T51	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T9	1		T129	2		T145	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T8	13		T12	1		T13	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T54	1		T27	1		T142	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T42	1		T31	3		T49	23
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T61	9		T214	10		T138	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T100	12		T50	4		T178	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T130	7		T272	14		T274	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18293	1			T1	146		T2	29		T3	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T42	1		T216	1		T164	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T13	12		T143	11		T52	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T9	4		T39	11		T141	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T48	3		T174	9		T228	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1309	1			T136	43		T26	26		T141	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T39	11		T141	4		T157	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T5	5		T138	9		T95	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T9	1		T163	15		T204	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T52	4		T220	1		T237	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T2	1		T13	5		T223	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T5	8		T48	10		T54	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T11	7		T47	6		T142	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T1	2		T16	5		T233	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T51	1		T18	1		T256	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T129	5		T146	22		T176	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T8	11		T13	10		T222	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T54	12		T142	2		T143	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T42	5		T49	18		T222	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T61	3		T138	13		T133	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T100	10		T50	2		T178	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T130	8		T277	9		T316	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T5	4		T278	9		T317	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T42	9		T164	12		T204	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T42	1		T50	4		T159	15
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T130	7		T133	12		T236	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T5	6		T271	16		T83	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T275	2		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T13	1		T157	2		T131	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T42	1		T16	3		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T48	14		T174	15		T158	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T9	12		T140	1		T39	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T2	2		T11	3		T39	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T5	1		T44	16		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T9	7		T27	1		T97	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T12	1		T102	12		T52	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T2	2		T13	1		T104	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T48	10		T54	1		T163	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T47	7		T142	4		T223	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T1	10		T5	9		T104	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T11	7		T49	1		T98	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T16	4		T129	2		T233	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T8	13		T12	1		T13	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T9	1		T143	19		T144	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T31	3		T49	23		T100	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1541	1			T7	1		T14	22		T54	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18234	1			T1	146		T2	29		T3	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T42	5		T50	2		T159	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T130	8		T133	11		T236	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T5	4		T271	14		T83	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T13	12		T143	11		T52	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T42	9		T141	6		T18	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T48	3		T174	9		T228	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T9	4		T39	11		T129	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T39	11		T141	4		T157	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T5	5		T141	4		T138	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T9	1		T135	12		T309	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T52	4		T220	1		T237	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T2	1		T13	5		T163	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T48	10		T54	9		T163	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T47	6		T142	3		T223	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T1	2		T5	8		T133	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T11	7		T51	1		T18	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T16	5		T129	5		T233	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T8	11		T13	10		T222	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T143	12		T144	3		T146	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T49	18		T100	10		T222	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1321	1			T54	12		T61	3		T136	43

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23340

1

T1

156

T2

33

T3

10

auto[1]

auto[0]

4179

1

T1

2

T2

1

T5

17