Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27519

1

T1

158

T2

34

T3

10

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23740

1

T1

158

T2

29

T3

10

auto[ADC_CTRL_FILTER_COND_OUT]

3779

1

T2

5

T5

6

T8

24

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21340

1

T1

158

T2

34

T3

10

auto[1]

6179

1

T5

23

T7

1

T8

24

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23361

1

T1

149

T2

33

T3

10

auto[1]

4158

1

T1

9

T2

1

T5

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	38	1			T165	1		T290	12		T93	5
values[0]	103	1			T157	16		T17	8		T227	6
values[1]	637	1			T54	13		T163	2		T233	8
values[2]	3169	1			T2	3		T7	1		T9	1
values[3]	836	1			T8	24		T9	16		T48	20
values[4]	364	1			T54	10		T39	12		T97	15
values[5]	947	1			T5	23		T12	1		T39	12
values[6]	618	1			T2	2		T140	1		T141	5
values[7]	599	1			T13	6		T104	3		T42	6
values[8]	642	1			T12	1		T13	11		T104	14
values[9]	1332	1			T1	12		T5	10		T9	8
minimum	18234	1			T1	146		T2	29		T3	10

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	775	1			T54	13		T157	16		T163	2
values[1]	3353	1			T2	3		T7	1		T9	17
values[2]	621	1			T8	24		T48	20		T39	12
values[3]	609	1			T54	10		T39	12		T61	12
values[4]	801	1			T2	2		T5	23		T12	1
values[5]	735	1			T13	6		T140	1		T104	3
values[6]	496	1			T42	6		T157	2		T137	12
values[7]	704	1			T12	1		T13	11		T104	14
values[8]	949	1			T1	12		T5	10		T9	8
values[9]	212	1			T13	13		T144	4		T146	12
minimum	18264	1			T1	146		T2	29		T3	10

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23340

1

T1

156

T2

33

T3

10

auto[1]

4179

1

T1

2

T2

1

T5

17

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T163	2		T228	9		T102	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T54	13		T157	12		T17	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1725	1			T7	1		T11	1		T14	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T2	2		T9	6		T142	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T48	11		T131	1		T227	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T8	12		T39	12		T49	23
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T39	12		T61	4		T228	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T54	10		T27	1		T31	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T5	9		T12	1		T16	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T2	2		T5	6		T16	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T104	1		T141	5		T163	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T13	6		T140	1		T163	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T42	6		T157	1		T138	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T137	12		T149	1		T188	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T137	14		T223	3		T100	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T12	1		T13	11		T104	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T1	3		T5	5		T9	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T48	4		T44	1		T214	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T144	4		T52	8		T237	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T13	13		T146	12		T159	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18110	1			T1	146		T2	29		T3	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T292	16		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T102	6		T17	3		T227	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T157	4		T150	9		T133	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1069	1			T11	2		T14	20		T40	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T2	1		T9	11		T142	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T48	9		T227	2		T52	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T8	12		T49	18		T164	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T61	8		T97	14		T102	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T31	1		T143	10		T241	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T5	8		T129	4		T100	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T16	3		T143	10		T188	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T104	2		T163	14		T256	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T95	7		T201	11		T204	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T157	1		T138	2		T174	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T149	10		T188	11		T36	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T223	6		T100	2		T18	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T104	13		T158	9		T130	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T1	9		T5	5		T9	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T48	13		T44	14		T214	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T52	5		T246	4		T298	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T159	14		T180	12		T318	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T35	1		T44	3		T47	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T165	1		T290	12		T93	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T319	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T17	5		T227	1		T244	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T157	12		T21	4		T264	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T163	2		T233	8		T228	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T54	13		T17	1		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1655	1			T7	1		T11	1		T14	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T2	2		T9	1		T142	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T48	11		T27	1		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T8	12		T9	5		T49	23
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T97	1		T52	5		T254	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T54	10		T39	12		T143	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T5	9		T12	1		T39	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T5	6		T16	6		T27	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T141	5		T163	16		T131	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T2	2		T140	1		T131	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T104	1		T42	6		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T13	6		T163	15		T137	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T137	14		T138	10		T174	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T12	1		T13	11		T104	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	382	1			T1	3		T5	5		T9	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T13	13		T48	4		T44	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18098	1			T1	146		T2	29		T3	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T93	1		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T319	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T17	3		T227	5		T244	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T157	4		T21	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T102	6		T176	12		T232	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T150	9		T133	13		T52	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1067	1			T11	2		T14	20		T40	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T2	1		T142	3		T223	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T48	9		T50	2		T36	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T8	12		T9	11		T49	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T97	14		T52	4		T254	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T143	10		T241	2		T177	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T5	8		T61	8		T129	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T16	3		T31	1		T143	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T163	14		T100	11		T256	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T95	7		T149	10		T188	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T104	2		T157	1		T174	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T36	14		T204	10		T247	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T138	2		T174	2		T223	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T104	13		T158	9		T130	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T1	9		T5	5		T9	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	334	1			T48	13		T44	14		T214	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T35	1		T44	3		T47	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T163	1		T228	1		T102	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T54	1		T157	5		T17	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1426	1			T7	1		T11	3		T14	22
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T2	2		T9	13		T142	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T48	10		T131	1		T227	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T8	13		T39	1		T49	23
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T39	1		T61	9		T228	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T54	1		T27	1		T31	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T5	9		T12	1		T16	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T2	2		T5	1		T16	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T104	3		T141	1		T163	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T13	1		T140	1		T163	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T42	1		T157	2		T138	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T137	1		T149	11		T188	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T137	1		T223	7		T100	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T12	1		T13	1		T104	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T1	10		T5	6		T9	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T48	14		T44	15		T214	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T144	1		T52	6		T237	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T13	1		T146	1		T159	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18237	1			T1	146		T2	29		T3	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T292	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T163	1		T228	8		T17	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T54	12		T157	11		T133	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1368	1			T136	43		T26	26		T142	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T2	1		T9	4		T142	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T48	10		T52	4		T219	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T8	11		T39	11		T49	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T39	11		T61	3		T228	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T54	9		T143	11		T146	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T5	8		T129	9		T100	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T5	5		T16	5		T143	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T141	4		T163	15		T256	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T13	5		T163	14		T95	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T42	5		T138	9		T174	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T137	11		T133	9		T135	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T137	13		T223	2		T18	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T13	10		T130	8		T204	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T1	2		T5	4		T9	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T48	3		T49	4		T222	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T144	3		T52	7		T237	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T13	12		T146	11		T159	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T320	11		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T292	15		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T165	1		T290	1		T93	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T319	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T17	5		T227	6		T244	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T157	5		T21	7		T264	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T163	1		T233	1		T228	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T54	1		T17	1		T150	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1412	1			T7	1		T11	3		T14	22
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T2	2		T9	1		T142	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T48	10		T27	1		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T8	13		T9	12		T49	23
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T97	15		T52	5		T254	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T54	1		T39	1		T143	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T5	9		T12	1		T39	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T5	1		T16	4		T27	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T141	1		T163	15		T131	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T2	2		T140	1		T131	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T104	3		T42	1		T157	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T13	1		T163	1		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T137	1		T138	3		T174	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T12	1		T13	1		T104	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	379	1			T1	10		T5	6		T9	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	406	1			T13	1		T48	14		T44	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18234	1			T1	146		T2	29		T3	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T290	11		T93	1		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T319	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T17	3		T244	13		T19	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T157	11		T21	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T163	1		T233	7		T228	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T54	12		T133	12		T52	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1310	1			T136	43		T26	26		T142	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T2	1		T142	3		T223	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T48	10		T50	2		T36	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T8	11		T9	4		T49	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T52	4		T135	12		T229	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T54	9		T39	11		T143	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T5	8		T39	11		T61	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T5	5		T16	5		T143	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T141	4		T163	15		T100	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T95	7		T201	11		T164	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T42	5		T174	9		T228	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T13	5		T163	14		T137	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T137	13		T138	9		T174	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T13	10		T130	8		T49	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T1	2		T5	4		T9	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T13	12		T48	3		T222	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23340

1

T1

156

T2

33

T3

10

auto[1]

auto[0]

4179

1

T1

2

T2

1

T5

17