Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27519

1

T1

158

T2

34

T3

10

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24067

1

T1

158

T2

31

T3

10

auto[ADC_CTRL_FILTER_COND_OUT]

3452

1

T2

3

T5

33

T9

25

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21073

1

T1

144

T2

31

T3

10

auto[1]

6446

1

T1

14

T2

3

T5

33

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23361

1

T1

149

T2

33

T3

10

auto[1]

4158

1

T1

9

T2

1

T5

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	702	1			T1	2		T9	12		T104	14
values[0]	90	1			T228	11		T302	26		T303	1
values[1]	666	1			T11	3		T27	1		T141	5
values[2]	2959	1			T5	10		T7	1		T8	24
values[3]	710	1			T9	1		T12	1		T13	11
values[4]	688	1			T2	2		T9	8		T61	2
values[5]	790	1			T9	16		T13	13		T48	17
values[6]	511	1			T5	17		T48	20		T39	24
values[7]	877	1			T2	3		T5	6		T44	15
values[8]	789	1			T11	14		T13	6		T54	10
values[9]	924	1			T1	12		T12	1		T141	5
minimum	17813	1			T1	144		T2	29		T3	10

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	594	1			T8	24		T27	1		T141	5
values[1]	2958	1			T5	10		T7	1		T13	11
values[2]	716	1			T9	1		T12	1		T16	9
values[3]	724	1			T2	2		T9	24		T140	1
values[4]	660	1			T13	13		T48	17		T44	1
values[5]	613	1			T2	3		T5	17		T48	20
values[6]	964	1			T5	6		T13	6		T44	15
values[7]	585	1			T11	14		T54	10		T27	1
values[8]	988	1			T1	12		T12	1		T104	14
values[9]	151	1			T42	10		T321	11		T225	30
minimum	18566	1			T1	146		T2	29		T3	10

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23340

1

T1

156

T2

33

T3

10

auto[1]

4179

1

T1

2

T2

1

T5

17

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T8	12		T141	5		T214	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T27	1		T222	4		T145	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1597	1			T7	1		T14	2		T105	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T5	5		T13	11		T54	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T157	12		T130	11		T228	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T9	1		T12	1		T16	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T2	2		T140	1		T16	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T9	7		T61	1		T47	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T13	13		T48	4		T142	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T44	1		T214	1		T232	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T48	11		T39	12		T138	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T2	2		T5	9		T39	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T13	6		T138	14		T174	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T5	6		T44	1		T141	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T11	8		T54	10		T27	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T223	3		T131	1		T97	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T1	3		T61	4		T214	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T12	1		T104	1		T141	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T42	10		T225	19		T322	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T321	1		T154	1		T301	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18201	1			T1	146		T2	29		T3	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T11	1		T157	1		T228	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T8	12		T214	4		T188	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T222	4		T145	2		T52	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1006	1			T14	20		T40	17		T43	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T5	5		T104	2		T150	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T157	4		T130	16		T149	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T16	3		T31	1		T158	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T142	7		T174	2		T36	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T9	17		T61	1		T47	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T48	13		T142	3		T138	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T214	8		T232	5		T221	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T48	9		T138	5		T36	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T2	1		T5	8		T18	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T138	12		T174	14		T150	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T44	14		T95	4		T100	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T11	6		T223	13		T49	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T223	6		T97	14		T102	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T1	9		T61	8		T214	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T104	13		T100	2		T188	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T225	11		T288	8		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T321	10		T301	17		T323	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T35	1		T44	3		T47	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T11	2		T157	1		T49	18

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	475	1			T1	2		T9	12		T41	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T104	1		T188	1		T230	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T302	13		T324	10		T258	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T228	11		T303	1		T258	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T141	5		T214	1		T137	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T11	1		T27	1		T157	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1622	1			T7	1		T8	12		T14	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T5	5		T54	13		T222	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T157	12		T228	28		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T9	1		T12	1		T13	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T2	2		T142	3		T137	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T9	2		T61	1		T47	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T13	13		T48	4		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T9	5		T44	1		T214	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T48	11		T39	12		T142	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T5	9		T39	12		T163	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T98	1		T150	1		T36	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T2	2		T5	6		T44	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T11	8		T13	6		T54	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T141	7		T223	3		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T1	3		T95	3		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T12	1		T141	5		T98	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17677	1			T1	144		T2	29		T3	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T61	8		T214	9		T224	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T104	13		T188	11		T230	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T302	13		T258	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T258	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T214	4		T188	11		T159	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T11	2		T157	1		T49	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1035	1			T8	12		T14	20		T40	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T5	5		T222	4		T150	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T157	4		T149	10		T143	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T104	2		T31	1		T158	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T142	7		T130	16		T215	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T9	6		T61	1		T47	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T48	13		T138	2		T174	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T9	11		T214	8		T21	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T48	9		T142	3		T138	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T5	8		T18	1		T219	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T150	14		T36	3		T256	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T2	1		T44	14		T95	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T11	6		T138	12		T174	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T223	6		T97	14		T102	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T1	9		T95	3		T149	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T100	2		T144	7		T52	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T35	1		T44	3		T47	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T8	13		T141	1		T214	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T27	1		T222	5		T145	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1343	1			T7	1		T14	22		T105	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T5	6		T13	1		T54	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T157	5		T130	17		T228	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T9	1		T12	1		T16	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T2	2		T140	1		T16	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T9	19		T61	2		T47	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T13	1		T48	14		T142	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T44	1		T214	9		T232	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T48	10		T39	1		T138	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T2	2		T5	9		T39	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T13	1		T138	13		T174	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T5	1		T44	15		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T11	7		T54	1		T27	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T223	7		T131	1		T97	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T1	10		T61	9		T214	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T12	1		T104	14		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T42	1		T225	12		T322	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T321	11		T154	1		T301	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18288	1			T1	146		T2	29		T3	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T11	3		T157	2		T228	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T8	11		T141	4		T137	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T222	3		T52	4		T283	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1260	1			T136	43		T26	26		T173	31
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T5	4		T13	10		T54	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T157	11		T130	10		T228	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T16	5		T178	9		T229	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T142	2		T137	11		T174	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T9	5		T47	6		T163	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T13	12		T48	3		T142	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T232	4		T221	4		T297	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T48	10		T39	11		T138	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T2	1		T5	8		T39	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T13	5		T138	13		T174	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T5	5		T141	6		T163	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T11	7		T54	9		T223	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T223	2		T222	10		T220	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T1	2		T61	3		T95	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T141	4		T144	10		T52	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T42	9		T225	18		T305	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T323	9		T325	7		T326	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T146	11		T159	14		T327	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T228	10		T49	18		T132	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	503	1			T1	2		T9	12		T41	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T104	14		T188	12		T230	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T302	14		T324	1		T258	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T228	1		T303	1		T258	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T141	1		T214	5		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T11	3		T27	1		T157	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1372	1			T7	1		T8	13		T14	22
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T5	6		T54	1		T222	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T157	5		T228	2		T149	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T9	1		T12	1		T13	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T2	2		T142	8		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T9	7		T61	2		T47	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T13	1		T48	14		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T9	12		T44	1		T214	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T48	10		T39	1		T142	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T5	9		T39	1		T163	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T98	1		T150	15		T36	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T2	2		T5	1		T44	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T11	7		T13	1		T54	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T141	1		T223	7		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T1	10		T95	4		T149	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T12	1		T141	1		T98	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17813	1			T1	144		T2	29		T3	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T42	9		T61	3		T224	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T183	12		T323	9		T328	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T302	12		T324	9		T258	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T228	10		T258	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T141	4		T137	13		T146	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T49	18		T132	9		T52	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1285	1			T8	11		T136	43		T26	26
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T5	4		T54	12		T222	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T157	11		T228	26		T143	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T13	10		T42	5		T178	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T142	2		T137	11		T130	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T9	1		T47	6		T16	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T13	12		T48	3		T138	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T9	4		T21	1		T297	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T48	10		T39	11		T142	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T5	8		T39	11		T163	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T36	10		T256	8		T52	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T2	1		T5	5		T163	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T11	7		T13	5		T54	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T141	6		T223	2		T222	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T1	2		T95	2		T222	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T141	4		T144	10		T52	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23340

1

T1

156

T2

33

T3

10

auto[1]

auto[0]

4179

1

T1

2

T2

1

T5

17