Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27519

1

T1

158

T2

34

T3

10

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23852

1

T1

146

T2

34

T3

10

auto[ADC_CTRL_FILTER_COND_OUT]

3667

1

T1

12

T5

6

T9

16

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21476

1

T1

158

T2

34

T3

10

auto[1]

6043

1

T7

1

T8

24

T9

9

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23361

1

T1

149

T2

33

T3

10

auto[1]

4158

1

T1

9

T2

1

T5

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	253	1			T39	12		T157	2		T138	12
values[0]	75	1			T39	12		T100	22		T307	23
values[1]	928	1			T1	12		T2	3		T13	11
values[2]	648	1			T5	17		T11	3		T12	1
values[3]	710	1			T13	19		T104	3		T44	1
values[4]	584	1			T140	1		T54	10		T141	5
values[5]	2941	1			T2	2		T7	1		T9	8
values[6]	688	1			T9	1		T11	14		T48	20
values[7]	684	1			T5	6		T8	24		T9	16
values[8]	703	1			T5	10		T61	2		T214	5
values[9]	1071	1			T42	6		T16	3		T130	42
minimum	18234	1			T1	146		T2	29		T3	10

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	959	1			T1	12		T2	3		T12	1
values[1]	761	1			T5	17		T11	3		T13	6
values[2]	585	1			T44	1		T142	10		T95	6
values[3]	2988	1			T7	1		T13	13		T14	22
values[4]	617	1			T2	2		T9	8		T12	1
values[5]	710	1			T9	17		T11	14		T48	37
values[6]	670	1			T5	6		T8	24		T47	13
values[7]	661	1			T5	10		T61	2		T214	5
values[8]	918	1			T42	6		T16	3		T157	2
values[9]	250	1			T39	12		T233	8		T159	25
minimum	18400	1			T1	146		T2	29		T3	10

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23340

1

T1

156

T2

33

T3

10

auto[1]

4179

1

T1

2

T2

1

T5

17

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T2	2		T12	1		T13	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T1	3		T54	13		T39	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T5	9		T11	1		T13	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T163	16		T97	1		T185	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T44	1		T142	3		T247	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T95	3		T98	1		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1587	1			T7	1		T14	2		T54	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T13	13		T140	1		T137	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T2	2		T9	2		T12	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T44	1		T138	14		T223	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T9	1		T11	8		T48	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T9	5		T48	4		T214	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T8	12		T163	2		T129	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T5	6		T47	9		T214	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T5	5		T137	12		T131	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T61	1		T214	1		T131	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T16	3		T130	20		T17	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T42	6		T157	1		T138	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T183	10		T180	1		T329	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T39	12		T233	8		T159	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18154	1			T1	146		T2	29		T3	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T228	11		T216	1		T134	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T2	1		T174	2		T222	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T1	9		T61	8		T129	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T5	8		T11	2		T104	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T163	14		T97	14		T188	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T142	7		T248	3		T20	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T95	3		T149	8		T222	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1012	1			T14	20		T104	13		T40	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T158	9		T49	18		T227	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T9	6		T31	1		T174	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T44	14		T138	12		T223	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T11	6		T48	9		T16	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T9	11		T48	13		T214	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T8	12		T129	3		T95	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T47	4		T214	9		T157	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T5	5		T149	10		T225	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T61	1		T214	4		T159	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T130	22		T150	4		T18	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T157	1		T138	2		T241	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T183	11		T180	10		T329	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T159	14		T177	13		T151	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T35	1		T44	3		T47	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T307	13		T330	12		T308	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T247	14		T283	10		T284	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T39	12		T157	1		T138	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T100	11		T331	2		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T39	12		T307	10		T308	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T2	2		T13	11		T27	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T1	3		T54	13		T129	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T5	9		T11	1		T12	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T61	4		T163	16		T185	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T13	6		T104	1		T44	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T13	13		T95	3		T97	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T54	10		T141	5		T142	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T140	1		T137	14		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1628	1			T2	2		T7	1		T9	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T138	14		T176	10		T164	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T9	1		T11	8		T48	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T44	1		T214	1		T163	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T8	12		T16	6		T163	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T5	6		T9	5		T48	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T5	5		T137	12		T129	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T61	1		T214	1		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T16	3		T130	20		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T42	6		T233	8		T241	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18098	1			T1	146		T2	29		T3	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T247	9		T246	12		T288	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T157	1		T138	2		T202	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T100	11		T331	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T307	13		T308	5		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T2	1		T142	3		T174	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T1	9		T129	1		T100	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T5	8		T11	2		T18	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T61	8		T163	14		T188	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T104	2		T52	5		T254	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T95	3		T97	14		T149	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T142	7		T138	5		T224	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T158	9		T49	18		T227	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1064	1			T9	6		T14	20		T104	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T138	12		T176	12		T164	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T11	6		T48	9		T36	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T44	14		T214	8		T223	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T8	12		T16	3		T102	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T9	11		T48	13		T47	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T5	5		T129	3		T95	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T61	1		T214	4		T159	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T130	22		T149	10		T150	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T241	2		T256	8		T164	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T35	1		T44	3		T47	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T2	2		T12	1		T13	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T1	10		T54	1		T39	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T5	9		T11	3		T13	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T163	15		T97	15		T185	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T44	1		T142	8		T247	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T95	4		T98	1		T149	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1351	1			T7	1		T14	22		T54	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T13	1		T140	1		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T2	2		T9	7		T12	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T44	15		T138	13		T223	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T9	1		T11	7		T48	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T9	12		T48	14		T214	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T8	13		T163	1		T129	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T5	1		T47	7		T214	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T5	6		T137	1		T131	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T61	2		T214	5		T131	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T16	3		T130	24		T17	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T42	1		T157	2		T138	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T183	12		T180	11		T329	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T39	1		T233	1		T159	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18277	1			T1	146		T2	29		T3	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T228	1		T216	1		T134	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T2	1		T13	10		T141	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T1	2		T54	12		T39	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T5	8		T13	5		T260	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T163	15		T178	9		T309	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T142	2		T248	3		T20	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T95	2		T222	10		T17	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1248	1			T54	9		T136	43		T26	26
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T13	12		T137	13		T49	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T9	1		T42	9		T174	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T138	13		T223	12		T176	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T11	7		T48	10		T16	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T9	4		T48	3		T163	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T8	11		T163	1		T129	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T5	5		T47	6		T157	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T5	4		T137	11		T144	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T159	14		T219	6		T247	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T130	18		T18	1		T282	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T42	5		T138	9		T256	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T183	9		T329	12		T332	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T39	11		T233	7		T159	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T141	4		T142	3		T100	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T228	10		T307	9		T330	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T247	10		T283	1		T284	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T39	1		T157	2		T138	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T100	12		T331	2		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T39	1		T307	14		T308	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T2	2		T13	1		T27	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T1	10		T54	1		T129	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T5	9		T11	3		T12	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T61	9		T163	15		T185	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T13	1		T104	3		T44	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T13	1		T95	4		T97	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T54	1		T141	1		T142	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T140	1		T137	1		T158	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1424	1			T2	2		T7	1		T9	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T138	13		T176	13		T164	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T9	1		T11	7		T48	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T44	15		T214	9		T163	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T8	13		T16	4		T163	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T5	1		T9	12		T48	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T5	6		T137	1		T129	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T61	2		T214	5		T131	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T16	3		T130	24		T149	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	338	1			T42	1		T233	1		T241	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18234	1			T1	146		T2	29		T3	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T247	13		T283	9		T246	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T39	11		T138	9		T294	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T100	10		T331	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T39	11		T307	9		T308	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T2	1		T13	10		T141	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T1	2		T54	12		T129	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T5	8		T18	2		T260	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T61	3		T163	15		T17	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T13	5		T52	7		T248	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T13	12		T95	2		T222	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T54	9		T141	4		T142	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T137	13		T49	18		T222	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1268	1			T9	1		T136	43		T26	26
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T138	13		T176	9		T164	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T11	7		T48	10		T42	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T163	14		T223	14		T201	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T8	11		T16	5		T163	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T5	5		T9	4		T48	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T5	4		T137	11		T129	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T159	14		T247	10		T237	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T130	18		T18	1		T144	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T42	5		T233	7		T256	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23340

1

T1

156

T2

33

T3

10

auto[1]

auto[0]

4179

1

T1

2

T2

1

T5

17