Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27519

1

T1

158

T2

34

T3

10

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23994

1

T1

158

T2

29

T3

10

auto[ADC_CTRL_FILTER_COND_OUT]

3525

1

T2

5

T5

17

T9

25

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21342

1

T1

158

T2

29

T3

10

auto[1]

6177

1

T2

5

T5

17

T7

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23361

1

T1

149

T2

33

T3

10

auto[1]

4158

1

T1

9

T2

1

T5

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	342	1			T39	12		T131	1		T100	22
values[0]	112	1			T104	3		T163	15		T333	1
values[1]	754	1			T11	3		T61	2		T31	3
values[2]	657	1			T9	8		T104	14		T42	10
values[3]	664	1			T13	6		T141	7		T138	26
values[4]	3090	1			T1	12		T2	2		T7	1
values[5]	654	1			T12	1		T54	13		T215	1
values[6]	807	1			T140	1		T16	9		T27	1
values[7]	738	1			T2	3		T5	6		T8	24
values[8]	582	1			T9	16		T12	1		T13	13
values[9]	885	1			T5	27		T9	1		T39	12
minimum	18234	1			T1	146		T2	29		T3	10

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	783	1			T9	8		T11	3		T61	2
values[1]	571	1			T104	14		T42	10		T44	1
values[2]	736	1			T1	12		T11	14		T13	6
values[3]	3075	1			T2	2		T7	1		T12	1
values[4]	665	1			T13	11		T54	13		T141	5
values[5]	835	1			T8	24		T140	1		T16	9
values[6]	740	1			T2	3		T5	6		T13	13
values[7]	595	1			T9	16		T12	1		T54	10
values[8]	907	1			T5	27		T9	1		T39	12
values[9]	82	1			T217	6		T334	1		T179	22
minimum	18530	1			T1	146		T2	29		T3	10

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23340

1

T1

156

T2

33

T3

10

auto[1]

4179

1

T1

2

T2

1

T5

17

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T31	2		T157	12		T138	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T9	2		T11	1		T61	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T104	1		T44	1		T141	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T42	10		T233	8		T222	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T1	3		T11	8		T13	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T48	11		T138	14		T129	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1630	1			T7	1		T12	1		T14	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T2	2		T48	4		T137	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T13	11		T149	1		T144	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T54	13		T141	5		T222	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T8	12		T140	1		T27	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T16	6		T228	9		T49	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T5	6		T44	1		T142	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T2	2		T13	13		T27	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T42	6		T47	9		T214	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T9	5		T12	1		T54	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T5	5		T61	4		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T5	9		T9	1		T39	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T179	13		T327	17		T286	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T217	2		T334	1		T335	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18183	1			T1	146		T2	29		T3	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T104	1		T163	2		T188	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T31	1		T157	4		T138	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T9	6		T11	2		T61	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T104	13		T142	3		T150	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T222	2		T143	10		T220	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T1	9		T11	6		T221	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T48	9		T138	12		T129	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1049	1			T14	20		T40	17		T43	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T48	13		T95	7		T204	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T149	10		T144	7		T201	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T222	4		T133	11		T247	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T8	12		T163	14		T174	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T16	3		T49	4		T50	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T44	14		T142	7		T49	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T2	1		T223	19		T130	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T47	4		T214	8		T52	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T9	11		T158	9		T130	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T5	5		T61	8		T157	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T5	8		T214	4		T164	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T179	9		T286	2		T336	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T217	4		T337	4		T235	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T35	1		T44	3		T47	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T104	2		T188	11		T21	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T100	11		T17	5		T151	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T39	12		T131	1		T177	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T163	15		T213	10		T338	18
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T104	1		T333	1		T319	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T31	2		T157	12		T138	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T11	1		T61	1		T214	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T104	1		T44	1		T141	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T9	2		T42	10		T16	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T13	6		T141	7		T222	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T138	14		T129	6		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1652	1			T1	3		T7	1		T11	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T2	2		T48	15		T137	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T12	1		T227	1		T339	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T54	13		T215	1		T178	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T140	1		T27	1		T163	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T16	6		T141	5		T228	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T5	6		T8	12		T44	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T2	2		T27	1		T223	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T42	6		T214	1		T143	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T9	5		T12	1		T13	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T5	5		T61	4		T47	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T5	9		T9	1		T39	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18098	1			T1	146		T2	29		T3	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T100	11		T17	3		T151	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T177	13		T225	6		T340	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T213	10		T338	18		T226	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T104	2		T319	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T31	1		T157	4		T138	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T11	2		T61	1		T214	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T104	13		T142	3		T150	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T9	6		T102	11		T143	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T219	4		T221	15		T229	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T138	12		T129	1		T222	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1071	1			T1	9		T11	6		T14	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T48	22		T95	7		T149	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T227	2		T201	11		T221	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T224	12		T22	3		T300	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T163	14		T174	2		T102	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T16	3		T222	4		T133	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T8	12		T44	14		T142	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T2	1		T223	13		T130	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T214	8		T143	18		T52	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T9	11		T158	9		T223	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T5	5		T61	8		T47	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T5	8		T214	4		T130	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T35	1		T44	3		T47	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T31	3		T157	5		T138	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T9	7		T11	3		T61	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T104	14		T44	1		T141	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T42	1		T233	1		T222	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T1	10		T11	7		T13	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T48	10		T138	13		T129	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1397	1			T7	1		T12	1		T14	22
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T2	2		T48	14		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T13	1		T149	11		T144	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T54	1		T141	1		T222	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T8	13		T140	1		T27	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T16	4		T228	1		T49	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T5	1		T44	15		T142	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T2	2		T13	1		T27	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T42	1		T47	7		T214	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T9	12		T12	1		T54	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T5	6		T61	9		T157	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T5	9		T9	1		T39	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T179	10		T327	1		T286	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T217	6		T334	1		T335	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18315	1			T1	146		T2	29		T3	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T104	3		T163	1		T188	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T157	11		T138	5		T174	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T9	1		T228	18		T52	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T141	10		T142	3		T137	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T42	9		T233	7		T222	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T1	2		T11	7		T13	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T48	10		T138	13		T129	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1282	1			T136	43		T26	26		T173	31
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T48	3		T137	13		T95	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T13	10		T144	10		T146	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T54	12		T141	4		T222	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T8	11		T163	15		T174	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T16	5		T228	8		T49	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T5	5		T142	2		T49	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T2	1		T13	12		T223	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T42	5		T47	6		T52	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T9	4		T54	9		T39	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T5	4		T61	3		T138	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T5	8		T39	11		T164	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T179	12		T327	16		T286	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T337	6		T235	1		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T163	14		T282	4		T212	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T163	1		T21	1		T242	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T100	12		T17	5		T151	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T39	1		T131	1		T177	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T163	1		T213	11		T338	19
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T104	3		T333	1		T319	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T31	3		T157	5		T138	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T11	3		T61	2		T214	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T104	14		T44	1		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T9	7		T42	1		T16	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T13	1		T141	1		T222	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T138	13		T129	2		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1415	1			T1	10		T7	1		T11	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T2	2		T48	24		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T12	1		T227	3		T339	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T54	1		T215	1		T178	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T140	1		T27	1		T163	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T16	4		T141	1		T228	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T5	1		T8	13		T44	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T2	2		T27	1		T223	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T42	1		T214	9		T143	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T9	12		T12	1		T13	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T5	6		T61	9		T47	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T5	9		T9	1		T39	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18234	1			T1	146		T2	29		T3	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T100	10		T17	3		T229	22
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T39	11		T283	9		T225	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T163	14		T213	9		T338	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T319	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T157	11		T138	5		T174	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T163	1		T228	18		T52	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T141	4		T142	3		T137	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T9	1		T42	9		T233	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T13	5		T141	6		T222	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T138	13		T129	5		T222	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1308	1			T1	2		T11	7		T13	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T48	13		T137	13		T95	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T201	11		T237	1		T221	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T54	12		T178	9		T224	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T163	15		T174	3		T228	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T16	5		T141	4		T228	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T5	5		T8	11		T142	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T2	1		T223	12		T130	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T42	5		T143	12		T52	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T9	4		T13	12		T54	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T5	4		T61	3		T47	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T5	8		T39	11		T130	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23340

1

T1

156

T2

33

T3

10

auto[1]

auto[0]

4179

1

T1

2

T2

1

T5

17