Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T140	1		T39	1		T44	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	335	1			T11	3		T137	1		T130	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T9	8		T61	9		T27	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T5	6		T8	13		T44	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T1	10		T104	3		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T9	12		T42	2		T16	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T13	1		T39	1		T129	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T2	2		T150	5		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T2	2		T48	10		T54	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T27	1		T214	5		T241	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T214	10		T157	2		T97	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T138	3		T158	10		T223	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1468	1			T7	1		T11	7		T14	22
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T61	2		T138	6		T222	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T163	1		T201	12		T19	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T141	1		T98	1		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T5	9		T12	1		T104	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T5	1		T12	1		T13	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T13	1		T214	9		T150	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T54	1		T47	7		T36	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18234	1			T1	146		T2	29		T3	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T240	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T39	11		T141	4		T163	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T137	11		T130	10		T49	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T9	1		T61	3		T142	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T5	4		T8	11		T223	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T1	2		T141	6		T146	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T9	4		T42	14		T138	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T13	5		T39	11		T129	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T2	1		T132	14		T52	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T48	10		T54	12		T163	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T146	11		T135	11		T247	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T143	12		T52	4		T248	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T138	9		T223	2		T18	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1357	1			T11	7		T136	43		T26	26
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T138	5		T222	10		T133	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T163	14		T201	11		T19	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T141	4		T132	9		T135	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T5	8		T16	5		T142	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T5	5		T13	10		T48	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T13	12		T244	13		T229	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T54	9		T47	6		T36	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T240	4		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T202	7		T238	8		T239	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T231	6		T240	3		T90	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T140	1		T44	15		T141	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T11	3		T137	1		T130	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T9	8		T39	1		T27	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T44	1		T223	14		T98	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T1	10		T39	1		T61	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T5	6		T8	13		T9	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T13	1		T104	3		T163	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T42	1		T150	5		T132	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T48	10		T54	1		T129	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T2	2		T27	1		T223	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T2	2		T214	10		T157	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T214	5		T138	3		T158	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T157	5		T49	5		T95	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T61	2		T138	6		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1438	1			T7	1		T11	7		T14	22
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T141	1		T129	4		T98	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T5	9		T12	1		T13	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	455	1			T5	1		T12	1		T13	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18234	1			T1	146		T2	29		T3	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T239	9		T235	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T240	4		T90	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T141	4		T163	15		T228	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T137	11		T130	10		T49	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T9	1		T39	11		T142	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T223	12		T176	9		T204	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T1	2		T39	11		T61	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T5	4		T8	11		T9	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T13	5		T163	1		T228	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T42	5		T132	14		T52	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T48	10		T54	12		T129	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T2	1		T223	2		T135	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T174	3		T233	7		T143	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T138	9		T18	3		T146	22
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T157	11		T49	4		T95	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T138	5		T132	9		T133	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1298	1			T11	7		T136	43		T16	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T141	4		T129	4		T222	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T5	8		T13	12		T163	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	423	1			T5	5		T13	10		T48	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23340

1

T1

156

T2

33

T3

10

auto[1]

auto[0]

4179

1

T1

2

T2

1

T5

17