Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27519

1

T1

158

T2

34

T3

10

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23723

1

T1

146

T2

31

T3

10

auto[ADC_CTRL_FILTER_COND_OUT]

3796

1

T1

12

T2

3

T5

33

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21455

1

T1

158

T2

31

T3

10

auto[1]

6064

1

T2

3

T7

1

T8

24

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23361

1

T1

149

T2

33

T3

10

auto[1]

4158

1

T1

9

T2

1

T5

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	24	1			T128	7		T249	13		T250	1
values[0]	16	1			T52	1		T251	15		-	-
values[1]	734	1			T5	6		T13	6		T140	1
values[2]	659	1			T2	2		T13	13		T48	17
values[3]	664	1			T9	1		T47	13		T141	12
values[4]	397	1			T1	12		T9	16		T12	1
values[5]	3092	1			T7	1		T11	3		T14	22
values[6]	726	1			T2	3		T9	8		T54	13
values[7]	746	1			T5	17		T8	24		T42	6
values[8]	809	1			T12	1		T48	20		T163	2
values[9]	1418	1			T5	10		T11	14		T13	11
minimum	18234	1			T1	146		T2	29		T3	10

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	895	1			T2	2		T5	6		T13	6
values[1]	791	1			T13	13		T47	13		T141	7
values[2]	464	1			T1	12		T9	16		T141	5
values[3]	2824	1			T7	1		T9	1		T12	1
values[4]	643	1			T2	3		T9	8		T11	3
values[5]	790	1			T5	17		T8	24		T54	13
values[6]	910	1			T137	12		T130	27		T131	1
values[7]	817	1			T12	1		T48	20		T42	6
values[8]	876	1			T11	14		T13	11		T54	10
values[9]	248	1			T5	10		T163	30		T241	3
minimum	18261	1			T1	146		T2	29		T3	10

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23340

1

T1

156

T2

33

T3

10

auto[1]

4179

1

T1

2

T2

1

T5

17

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T2	2		T13	6		T48	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T5	6		T39	12		T233	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T13	13		T174	4		T100	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T47	9		T141	7		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T138	10		T129	5		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T1	3		T9	5		T141	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1613	1			T7	1		T12	1		T14	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T9	1		T27	1		T214	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T27	1		T102	1		T185	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T2	2		T9	2		T11	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T54	13		T104	1		T61	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T5	9		T8	12		T104	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T137	12		T143	13		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T130	11		T131	1		T222	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T12	1		T42	6		T31	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T48	11		T163	2		T137	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T13	11		T54	10		T39	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T11	8		T44	1		T141	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T241	1		T36	11		T147	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T5	5		T163	16		T133	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18103	1			T1	146		T2	29		T3	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T252	5		T253	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T48	13		T61	8		T157	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T97	14		T52	5		T254	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T174	2		T100	11		T220	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T47	4		T150	14		T227	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T138	2		T129	3		T143	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T1	9		T9	11		T129	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1017	1			T14	20		T40	17		T43	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T214	9		T246	2		T255	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T102	6		T215	13		T52	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T2	1		T9	6		T11	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T104	13		T61	1		T143	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T5	8		T8	12		T104	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T143	18		T150	4		T144	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T130	16		T222	2		T18	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T31	1		T157	1		T102	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T48	9		T130	6		T256	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T174	14		T223	6		T49	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T11	6		T142	7		T188	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T241	2		T36	3		T243	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T5	5		T163	14		T133	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T35	1		T44	3		T47	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T252	6		T253	10		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T128	6		T249	13		T250	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T257	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T52	1		T251	15		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T13	6		T140	1		T16	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T5	6		T39	12		T52	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T2	2		T13	13		T48	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T129	6		T233	8		T97	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T138	10		T174	4		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T9	1		T47	9		T141	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T12	1		T42	10		T129	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T1	3		T9	5		T27	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1581	1			T7	1		T14	2		T105	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T11	1		T16	6		T223	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T54	13		T104	1		T61	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T2	2		T9	2		T104	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T42	6		T163	15		T137	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T5	9		T8	12		T131	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T12	1		T49	1		T102	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T48	11		T163	2		T137	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	394	1			T13	11		T54	10		T39	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	373	1			T5	5		T11	8		T44	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18098	1			T1	146		T2	29		T3	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T128	1		T258	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T138	12		T158	9		T222	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T52	5		T254	2		T224	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T48	13		T61	8		T157	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T129	1		T97	14		T150	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T138	2		T174	2		T100	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T47	4		T227	6		T204	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T129	3		T143	10		T259	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T1	9		T9	11		T214	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1000	1			T14	20		T40	17		T43	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T11	2		T16	3		T223	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T104	13		T61	1		T143	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T2	1		T9	6		T104	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T143	18		T144	7		T145	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T5	8		T8	12		T222	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T102	11		T150	4		T227	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T48	9		T130	22		T18	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T31	1		T157	1		T174	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	372	1			T5	5		T11	6		T163	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T35	1		T44	3		T47	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	329	1			T2	2		T13	1		T48	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T5	1		T39	1		T233	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T13	1		T174	3		T100	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T47	7		T141	1		T150	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T138	3		T129	4		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T1	10		T9	12		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1365	1			T7	1		T12	1		T14	22
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T9	1		T27	1		T214	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T27	1		T102	7		T185	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T2	2		T9	7		T11	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T54	1		T104	14		T61	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T5	9		T8	13		T104	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T137	1		T143	19		T150	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T130	17		T131	1		T222	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T12	1		T42	1		T31	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T48	10		T163	1		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T13	1		T54	1		T39	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T11	7		T44	1		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T241	3		T36	4		T147	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T5	6		T163	15		T133	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18236	1			T1	146		T2	29		T3	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T252	7		T253	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T13	5		T48	3		T61	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T5	5		T39	11		T233	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T13	12		T174	3		T100	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T47	6		T141	6		T204	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T138	9		T129	4		T143	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T1	2		T9	4		T141	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1265	1			T42	9		T136	43		T26	26
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T260	17		T246	2		T255	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T132	14		T52	4		T159	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T2	1		T9	1		T16	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T54	12		T163	14		T228	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T5	8		T8	11		T142	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T137	11		T143	12		T144	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T130	10		T222	10		T18	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T42	5		T228	18		T50	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T48	10		T163	1		T137	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T13	10		T54	9		T39	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T11	7		T141	4		T142	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T36	10		T183	9		T249	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T5	4		T163	15		T133	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T261	3		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T252	4		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T128	6		T249	1		T250	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T257	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T52	1		T251	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T13	1		T140	1		T16	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T5	1		T39	1		T52	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T2	2		T13	1		T48	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T129	2		T233	1		T97	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T138	3		T174	3		T131	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T9	1		T47	7		T141	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T12	1		T42	1		T129	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T1	10		T9	12		T27	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1339	1			T7	1		T14	22		T105	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T11	3		T16	4		T223	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T54	1		T104	14		T61	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T2	2		T9	7		T104	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T42	1		T163	1		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T5	9		T8	13		T131	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T12	1		T49	1		T102	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T48	10		T163	1		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	362	1			T13	1		T54	1		T39	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	452	1			T5	6		T11	7		T44	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18234	1			T1	146		T2	29		T3	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T128	1		T249	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T251	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T13	5		T138	13		T222	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T5	5		T39	11		T52	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T13	12		T48	3		T61	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T129	5		T233	7		T248	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T138	9		T174	3		T100	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T47	6		T141	10		T204	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T42	9		T129	4		T143	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T1	2		T9	4		T260	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1242	1			T136	43		T26	26		T173	31
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T16	5		T223	12		T49	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T54	12		T228	8		T222	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T2	1		T9	1		T142	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T42	5		T163	14		T137	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T5	8		T8	11		T222	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T204	11		T245	13		T221	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T48	10		T163	1		T137	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T13	10		T54	9		T39	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T5	4		T11	7		T141	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23340

1

T1

156

T2

33

T3

10

auto[1]

auto[0]

4179

1

T1

2

T2

1

T5

17