Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27519

1

T1

158

T2

34

T3

10

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23707

1

T1

158

T2

29

T3

10

auto[ADC_CTRL_FILTER_COND_OUT]

3812

1

T2

5

T5

6

T8

24

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21341

1

T1

158

T2

34

T3

10

auto[1]

6178

1

T5

23

T7

1

T8

24

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23361

1

T1

149

T2

33

T3

10

auto[1]

4158

1

T1

9

T2

1

T5

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	347	1			T44	15		T214	14		T159	25
values[0]	5	1			T19	4		T279	1		-	-
values[1]	763	1			T54	13		T157	16		T163	2
values[2]	3072	1			T2	3		T7	1		T9	1
values[3]	887	1			T8	24		T9	16		T48	20
values[4]	386	1			T54	10		T39	12		T97	15
values[5]	953	1			T5	23		T12	1		T39	12
values[6]	642	1			T2	2		T140	1		T16	12
values[7]	590	1			T13	6		T104	3		T42	6
values[8]	601	1			T12	1		T13	11		T137	14
values[9]	1039	1			T1	12		T5	10		T9	8
minimum	18234	1			T1	146		T2	29		T3	10

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	648	1			T54	13		T163	2		T233	8
values[1]	3209	1			T2	3		T7	1		T9	17
values[2]	660	1			T8	24		T48	20		T39	12
values[3]	561	1			T12	1		T54	10		T39	12
values[4]	841	1			T2	2		T5	17		T16	3
values[5]	710	1			T5	6		T13	6		T140	1
values[6]	510	1			T42	6		T157	2		T174	24
values[7]	724	1			T12	1		T13	11		T104	14
values[8]	911	1			T1	12		T5	10		T9	8
values[9]	221	1			T13	13		T44	15		T144	4
minimum	18524	1			T1	146		T2	29		T3	10

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23340

1

T1

156

T2

33

T3

10

auto[1]

4179

1

T1

2

T2

1

T5

17

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T163	2		T233	8		T228	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T54	13		T17	1		T133	25
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1686	1			T7	1		T14	2		T105	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T2	2		T9	6		T11	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T48	11		T131	1		T227	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T8	12		T39	12		T49	23
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T12	1		T39	12		T61	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T54	10		T27	1		T31	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T5	9		T16	3		T129	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T2	2		T143	11		T51	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T104	1		T141	5		T163	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T5	6		T13	6		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T42	6		T157	1		T174	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T149	1		T188	1		T36	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T137	14		T138	10		T174	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T12	1		T13	11		T104	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T1	3		T5	5		T9	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T48	4		T214	2		T49	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T144	4		T52	8		T246	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T13	13		T44	1		T146	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18149	1			T1	146		T2	29		T3	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T157	12		T150	1		T52	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T17	3		T227	5		T244	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T133	24		T248	3		T21	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1050	1			T14	20		T40	17		T43	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T2	1		T9	11		T11	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T48	9		T227	2		T52	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T8	12		T49	18		T164	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T61	8		T97	14		T102	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T31	1		T143	10		T241	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T5	8		T129	4		T100	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T143	10		T51	1		T18	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T104	2		T163	14		T256	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T16	3		T95	7		T188	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T157	1		T174	14		T222	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T149	10		T188	11		T36	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T138	2		T174	2		T223	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T104	13		T158	9		T130	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T1	9		T5	5		T9	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T48	13		T214	12		T49	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T52	5		T246	4		T263	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T44	14		T159	14		T180	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T35	1		T44	3		T47	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T157	4		T150	9		T52	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T236	11		T237	2		T246	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T44	1		T214	2		T159	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T19	4		T279	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T163	2		T233	8		T228	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T54	13		T157	12		T17	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1653	1			T7	1		T14	2		T105	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T2	2		T9	1		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T48	11		T131	1		T50	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T8	12		T9	5		T49	23
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T97	1		T52	5		T254	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T54	10		T39	12		T143	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T5	9		T12	1		T39	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T5	6		T27	1		T31	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T16	3		T141	5		T163	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T2	2		T140	1		T16	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T104	1		T42	6		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T13	6		T163	15		T137	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T137	14		T138	10		T174	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T12	1		T13	11		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T1	3		T5	5		T9	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T13	13		T48	4		T104	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18098	1			T1	146		T2	29		T3	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T236	6		T246	4		T280	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T44	14		T214	12		T159	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T102	6		T17	3		T227	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T157	4		T150	9		T133	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1043	1			T14	20		T40	17		T43	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T2	1		T11	2		T142	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T48	9		T50	2		T36	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T8	12		T9	11		T49	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T97	14		T52	4		T254	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T143	10		T241	2		T281	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T5	8		T61	8		T129	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T31	1		T143	10		T51	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T163	14		T100	11		T256	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T16	3		T95	7		T188	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T104	2		T157	1		T174	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T149	10		T36	14		T247	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T138	2		T174	2		T223	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T158	9		T130	6		T149	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T1	9		T5	5		T9	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T48	13		T104	13		T49	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T35	1		T44	3		T47	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T163	1		T233	1		T228	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T54	1		T17	1		T133	26
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1402	1			T7	1		T14	22		T105	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T2	2		T9	13		T11	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T48	10		T131	1		T227	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T8	13		T39	1		T49	23
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T12	1		T39	1		T61	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T54	1		T27	1		T31	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T5	9		T16	3		T129	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T2	2		T143	11		T51	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T104	3		T141	1		T163	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T5	1		T13	1		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T42	1		T157	2		T174	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T149	11		T188	12		T36	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T137	1		T138	3		T174	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T12	1		T13	1		T104	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T1	10		T5	6		T9	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T48	14		T214	14		T49	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T144	1		T52	6		T246	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T13	1		T44	15		T146	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18295	1			T1	146		T2	29		T3	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T157	5		T150	10		T52	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T163	1		T233	7		T228	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T54	12		T133	23		T282	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1334	1			T136	43		T26	26		T142	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T2	1		T9	4		T142	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T48	10		T52	4		T219	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T8	11		T39	11		T49	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T39	11		T61	3		T228	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T54	9		T143	11		T146	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T5	8		T129	9		T100	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T143	10		T51	1		T18	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T141	4		T163	15		T256	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T5	5		T13	5		T16	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T42	5		T174	9		T228	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T133	9		T135	11		T245	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T137	13		T138	9		T174	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T13	10		T130	8		T204	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T1	2		T5	4		T9	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T48	3		T49	4		T222	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T144	3		T52	7		T246	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T13	12		T146	11		T159	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T232	9		T221	4		T243	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T157	11		T52	8		T164	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T236	7		T237	1		T246	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T44	15		T214	14		T159	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T19	1		T279	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T163	1		T233	1		T228	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T54	1		T157	5		T17	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1388	1			T7	1		T14	22		T105	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T2	2		T9	1		T11	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T48	10		T131	1		T50	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T8	13		T9	12		T49	23
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T97	15		T52	5		T254	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T54	1		T39	1		T143	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T5	9		T12	1		T39	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T5	1		T27	1		T31	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T16	3		T141	1		T163	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T2	2		T140	1		T16	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T104	3		T42	1		T157	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T13	1		T163	1		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T137	1		T138	3		T174	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T12	1		T13	1		T158	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	331	1			T1	10		T5	6		T9	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T13	1		T48	14		T104	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18234	1			T1	146		T2	29		T3	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T236	10		T237	1		T246	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T159	10		T283	9		T284	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T19	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T163	1		T233	7		T228	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T54	12		T157	11		T133	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1308	1			T136	43		T26	26		T142	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T2	1		T142	3		T223	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T48	10		T50	2		T36	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T8	11		T9	4		T49	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T52	4		T135	12		T229	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T54	9		T39	11		T143	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T5	8		T39	11		T61	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T5	5		T143	10		T51	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T141	4		T163	15		T100	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T16	5		T95	7		T201	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T42	5		T174	9		T228	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T13	5		T163	14		T137	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T137	13		T138	9		T174	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T13	10		T130	8		T133	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T1	2		T5	4		T9	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T13	12		T48	3		T49	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23340

1

T1

156

T2

33

T3

10

auto[1]

auto[0]

4179

1

T1

2

T2

1

T5

17