Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27519

1

T1

158

T2

34

T3

10

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23986

1

T1

158

T2

32

T3

10

auto[ADC_CTRL_FILTER_COND_OUT]

3533

1

T2

2

T5

33

T9

25

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21225

1

T1

158

T2

31

T3

10

auto[1]

6294

1

T2

3

T7

1

T8

24

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23361

1

T1

149

T2

33

T3

10

auto[1]

4158

1

T1

9

T2

1

T5

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	161	1			T137	12		T97	15		T260	18
values[0]	41	1			T168	26		T268	15		-	-
values[1]	662	1			T2	2		T5	10		T104	3
values[2]	560	1			T13	19		T104	14		T214	9
values[3]	636	1			T9	1		T47	13		T141	7
values[4]	887	1			T8	24		T11	14		T39	12
values[5]	940	1			T13	11		T42	6		T61	2
values[6]	681	1			T1	12		T2	3		T5	17
values[7]	506	1			T5	6		T12	1		T48	37
values[8]	712	1			T9	8		T11	3		T12	1
values[9]	3499	1			T7	1		T9	16		T14	22
minimum	18234	1			T1	146		T2	29		T3	10

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	631	1			T2	2		T5	10		T13	13
values[1]	510	1			T13	6		T141	7		T49	9
values[2]	613	1			T9	1		T47	13		T27	1
values[3]	950	1			T8	24		T11	14		T39	12
values[4]	953	1			T2	3		T13	11		T44	15
values[5]	546	1			T1	12		T5	17		T140	1
values[6]	2991	1			T5	6		T7	1		T9	8
values[7]	695	1			T11	3		T12	1		T54	13
values[8]	1019	1			T9	16		T54	10		T142	7
values[9]	104	1			T141	5		T52	13		T164	21
minimum	18507	1			T1	146		T2	29		T3	10

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23340

1

T1

156

T2

33

T3

10

auto[1]

4179

1

T1

2

T2

1

T5

17

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T44	1		T131	1		T49	23
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T2	2		T5	5		T13	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T13	6		T51	3		T215	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T141	7		T49	5		T143	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T47	9		T27	1		T100	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T9	1		T137	14		T138	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T8	12		T42	6		T157	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T11	8		T39	12		T61	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T2	2		T13	11		T27	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T44	1		T214	1		T131	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T1	3		T140	1		T129	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T5	9		T42	10		T16	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1655	1			T7	1		T14	2		T48	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T5	6		T9	2		T12	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T61	4		T163	16		T223	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T11	1		T12	1		T54	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T54	10		T137	12		T228	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T9	5		T142	4		T174	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T52	8		T269	6		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T141	5		T164	10		T285	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18163	1			T1	146		T2	29		T3	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T157	12		T100	11		T247	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T49	18		T149	10		T222	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T5	5		T104	15		T16	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T51	1		T215	13		T52	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T49	4		T143	18		T244	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T47	4		T100	2		T36	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T138	2		T174	2		T188	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T8	12		T157	1		T130	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T11	6		T61	1		T158	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T2	1		T214	4		T138	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T44	14		T214	9		T150	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T1	9		T129	3		T150	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T5	8		T102	6		T144	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1053	1			T14	20		T48	22		T40	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T9	6		T95	3		T204	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T61	8		T163	14		T223	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T11	2		T142	7		T135	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T95	4		T188	11		T52	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T9	11		T142	3		T174	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T52	5		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T164	11		T286	2		T287	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T35	1		T44	3		T47	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T157	4		T100	11		T247	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T137	12		T264	1		T262	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T97	1		T260	18		T128	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T168	15		T268	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T44	1		T49	23		T149	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T2	2		T5	5		T104	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T13	6		T131	1		T215	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T13	13		T104	1		T214	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T47	9		T100	1		T36	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T9	1		T141	7		T137	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T8	12		T27	1		T157	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T11	8		T39	12		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T13	11		T42	6		T27	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T61	1		T214	1		T131	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T1	3		T2	2		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T5	9		T42	10		T44	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T48	15		T141	5		T138	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T5	6		T12	1		T163	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T31	2		T163	16		T223	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T9	2		T11	1		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1754	1			T7	1		T14	2		T54	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T9	5		T54	13		T141	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18098	1			T1	146		T2	29		T3	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T288	3		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T97	14		T128	1		T177	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T168	11		T268	14		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T49	18		T149	10		T222	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T5	5		T104	2		T16	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T215	13		T52	4		T201	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T104	13		T214	8		T143	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T47	4		T100	2		T36	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T138	2		T174	2		T49	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T8	12		T157	1		T130	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T11	6		T158	9		T149	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T214	4		T138	5		T102	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T61	1		T214	9		T150	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T1	9		T2	1		T150	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T5	8		T44	14		T144	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T48	22		T138	12		T129	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T95	3		T102	6		T247	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T31	1		T163	14		T223	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T9	6		T11	2		T204	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1171	1			T14	20		T40	17		T43	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T9	11		T142	10		T174	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T35	1		T44	3		T47	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T44	1		T131	1		T49	23
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T2	2		T5	6		T13	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T13	1		T51	3		T215	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T141	1		T49	5		T143	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T47	7		T27	1		T100	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T9	1		T137	1		T138	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T8	13		T42	1		T157	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T11	7		T39	1		T61	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T2	2		T13	1		T27	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T44	15		T214	10		T131	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T1	10		T140	1		T129	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T5	9		T42	1		T16	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1393	1			T7	1		T14	22		T48	24
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T5	1		T9	7		T12	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T61	9		T163	15		T223	21
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T11	3		T12	1		T54	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T54	1		T137	1		T228	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T9	12		T142	4		T174	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T52	6		T269	1		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T141	1		T164	12		T285	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18295	1			T1	146		T2	29		T3	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T157	5		T100	12		T247	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T49	18		T222	3		T164	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T5	4		T13	12		T16	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T13	5		T51	1		T52	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T141	6		T49	4		T143	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T47	6		T36	10		T132	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T137	13		T138	9		T174	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T8	11		T42	5		T130	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T11	7		T39	11		T17	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T2	1		T13	10		T138	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T133	11		T52	4		T289	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T1	2		T129	4		T233	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T5	8		T42	9		T144	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1315	1			T48	13		T136	43		T26	26
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T5	5		T9	1		T163	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T61	3		T163	15		T223	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T54	12		T39	11		T142	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T54	9		T137	11		T228	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T9	4		T142	3		T174	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T52	7		T269	5		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T141	4		T164	9		T290	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T222	10		T237	1		T284	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T157	11		T100	10		T247	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T137	1		T264	1		T262	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T97	15		T260	1		T128	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T168	12		T268	15		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T44	1		T49	23		T149	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T2	2		T5	6		T104	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T13	1		T131	1		T215	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T13	1		T104	14		T214	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T47	7		T100	3		T36	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T9	1		T141	1		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T8	13		T27	1		T157	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T11	7		T39	1		T158	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T13	1		T42	1		T27	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T61	2		T214	10		T131	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T1	10		T2	2		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T5	9		T42	1		T44	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T48	24		T141	1		T138	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T5	1		T12	1		T163	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T31	3		T163	15		T223	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T9	7		T11	3		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1540	1			T7	1		T14	22		T54	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T9	12		T54	1		T141	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18234	1			T1	146		T2	29		T3	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T137	11		T291	8		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T260	17		T128	1		T162	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T168	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T49	18		T222	13		T164	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T5	4		T16	5		T157	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T13	5		T52	4		T201	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T13	12		T143	12		T244	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T47	6		T36	10		T51	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T141	6		T137	13		T138	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T8	11		T130	10		T132	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T11	7		T39	11		T228	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T13	10		T42	5		T138	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T133	11		T146	11		T52	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T1	2		T2	1		T233	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T5	8		T42	9		T144	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T48	13		T141	4		T138	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T5	5		T163	15		T95	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T163	15		T223	2		T133	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T9	1		T39	11		T222	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1385	1			T54	9		T61	3		T136	43
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T9	4		T54	12		T141	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23340

1

T1

156

T2

33

T3

10

auto[1]

auto[0]

4179

1

T1

2

T2

1

T5

17