Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27519

1

T1

158

T2

34

T3

10

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23859

1

T1

146

T2

31

T3

10

auto[ADC_CTRL_FILTER_COND_OUT]

3660

1

T1

12

T2

3

T5

33

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21077

1

T1

158

T2

31

T3

10

auto[1]

6442

1

T2

3

T7

1

T8

24

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23361

1

T1

149

T2

33

T3

10

auto[1]

4158

1

T1

9

T2

1

T5

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	200	1			T39	12		T100	3		T188	12
values[0]	34	1			T52	1		T234	11		T292	22
values[1]	688	1			T5	6		T13	6		T140	1
values[2]	673	1			T2	2		T13	13		T48	17
values[3]	684	1			T9	1		T47	13		T141	12
values[4]	415	1			T1	12		T9	16		T12	1
values[5]	3046	1			T7	1		T11	3		T14	22
values[6]	703	1			T2	3		T5	17		T9	8
values[7]	803	1			T8	24		T163	15		T131	1
values[8]	864	1			T12	1		T48	20		T42	6
values[9]	1175	1			T5	10		T11	14		T13	11
minimum	18234	1			T1	146		T2	29		T3	10

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	648	1			T2	2		T5	6		T140	1
values[1]	829	1			T13	13		T48	17		T47	13
values[2]	489	1			T1	12		T9	16		T141	5
values[3]	2792	1			T7	1		T9	1		T12	1
values[4]	702	1			T2	3		T9	8		T11	3
values[5]	680	1			T5	17		T54	13		T104	3
values[6]	900	1			T8	24		T137	12		T130	27
values[7]	877	1			T12	1		T48	20		T42	6
values[8]	993	1			T5	10		T11	14		T13	11
values[9]	136	1			T163	30		T133	26		T147	1
minimum	18473	1			T1	146		T2	29		T3	10

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23340

1

T1

156

T2

33

T3

10

auto[1]

4179

1

T1

2

T2

1

T5

17

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T2	2		T140	1		T61	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T5	6		T39	12		T16	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T13	13		T48	4		T157	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T47	9		T141	7		T100	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T138	10		T174	4		T129	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T1	3		T9	5		T141	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1596	1			T7	1		T12	1		T14	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T9	1		T27	1		T214	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T9	2		T16	6		T102	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T2	2		T11	1		T104	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T54	13		T61	1		T214	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T5	9		T104	1		T142	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T8	12		T137	12		T228	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T130	11		T131	1		T222	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T48	11		T31	2		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T12	1		T42	6		T163	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T13	11		T54	10		T39	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T5	5		T11	8		T44	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T133	13		T147	1		T293	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T163	16		T294	2		T295	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18177	1			T1	146		T2	29		T3	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T13	6		T52	8		T210	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T61	8		T138	12		T158	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T97	14		T227	2		T254	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T48	13		T157	4		T149	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T47	4		T100	11		T150	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T138	2		T174	2		T129	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T1	9		T9	11		T248	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	996	1			T14	20		T40	17		T43	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T214	9		T151	10		T271	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T9	6		T16	3		T102	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T2	1		T11	2		T104	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T61	1		T214	12		T51	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T5	8		T104	2		T142	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T8	12		T143	18		T150	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T130	16		T222	2		T177	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T48	9		T31	1		T157	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T130	6		T256	8		T232	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T174	14		T223	6		T100	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T5	5		T11	6		T142	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T133	13		T183	8		T258	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T163	14		T294	9		T295	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T35	1		T44	3		T47	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T52	5		T210	1		T252	6

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T39	12		T100	1		T36	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T188	1		T36	1		T164	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T234	11		T292	22		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T52	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T140	1		T138	14		T158	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T5	6		T13	6		T39	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T2	2		T13	13		T48	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T97	1		T150	1		T227	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T138	10		T174	4		T129	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T9	1		T47	9		T141	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T12	1		T42	10		T129	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T1	3		T9	5		T27	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1577	1			T7	1		T14	2		T105	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T11	1		T27	1		T223	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T9	2		T54	13		T61	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T2	2		T5	9		T104	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T8	12		T163	15		T228	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T131	1		T222	11		T150	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T48	11		T31	2		T137	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T12	1		T42	6		T163	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	333	1			T13	11		T54	10		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T5	5		T11	8		T44	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18098	1			T1	146		T2	29		T3	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T100	2		T36	3		T128	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T188	11		T36	14		T164	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T138	12		T158	9		T222	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T52	5		T254	2		T210	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T48	13		T61	8		T157	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T97	14		T150	14		T227	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T138	2		T174	2		T129	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T47	4		T100	11		T227	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T129	3		T143	10		T259	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T1	9		T9	11		T214	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	989	1			T14	20		T40	17		T43	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T11	2		T223	13		T49	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T9	6		T61	1		T214	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T2	1		T5	8		T104	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T8	12		T143	18		T144	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T222	2		T150	9		T145	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T48	9		T31	1		T102	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T130	22		T256	8		T245	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T157	1		T174	14		T223	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T5	5		T11	6		T163	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T35	1		T44	3		T47	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T2	2		T140	1		T61	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T5	1		T39	1		T16	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T13	1		T48	14		T157	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T47	7		T141	1		T100	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T138	3		T174	3		T129	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T1	10		T9	12		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1339	1			T7	1		T12	1		T14	22
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T9	1		T27	1		T214	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T9	7		T16	4		T102	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T2	2		T11	3		T104	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T54	1		T61	2		T214	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T5	9		T104	3		T142	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T8	13		T137	1		T228	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T130	17		T131	1		T222	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T48	10		T31	3		T157	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T12	1		T42	1		T163	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T13	1		T54	1		T39	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T5	6		T11	7		T44	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T133	14		T147	1		T293	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T163	15		T294	10		T295	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18293	1			T1	146		T2	29		T3	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T13	1		T52	6		T210	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T61	3		T138	13		T18	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T5	5		T39	11		T233	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T13	12		T48	3		T157	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T47	6		T141	6		T100	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T138	9		T174	3		T129	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T1	2		T9	4		T141	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1253	1			T42	9		T136	43		T26	26
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T260	17		T237	1		T246	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T9	1		T16	5		T143	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T2	1		T223	12		T49	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T54	12		T163	14		T204	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T5	8		T142	3		T222	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T8	11		T137	11		T228	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T130	10		T222	10		T289	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T48	10		T228	18		T50	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T42	5		T163	1		T137	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T13	10		T54	9		T39	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T5	4		T11	7		T141	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T133	12		T183	9		T296	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T163	15		T294	1		T295	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T222	3		T135	12		T161	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T13	5		T52	7		T210	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T39	1		T100	3		T36	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T188	12		T36	15		T164	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T234	1		T292	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T52	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T140	1		T138	13		T158	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T5	1		T13	1		T39	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T2	2		T13	1		T48	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T97	15		T150	15		T227	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T138	3		T174	3		T129	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T9	1		T47	7		T141	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T12	1		T42	1		T129	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T1	10		T9	12		T27	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1322	1			T7	1		T14	22		T105	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T11	3		T27	1		T223	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T9	7		T54	1		T61	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T2	2		T5	9		T104	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T8	13		T163	1		T228	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T131	1		T222	3		T150	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T48	10		T31	3		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T12	1		T42	1		T163	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	329	1			T13	1		T54	1		T157	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	348	1			T5	6		T11	7		T44	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18234	1			T1	146		T2	29		T3	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T39	11		T36	10		T128	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T164	12		T295	8		T249	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T234	10		T292	21		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T138	13		T222	3		T18	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T5	5		T13	5		T39	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T13	12		T48	3		T61	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T224	10		T297	2		T298	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T138	9		T174	3		T129	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T47	6		T141	10		T100	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T42	9		T129	4		T143	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T1	2		T9	4		T260	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1244	1			T136	43		T16	5		T26	26
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T223	12		T49	18		T95	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T9	1		T54	12		T143	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T2	1		T5	8		T142	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T8	11		T163	14		T228	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T222	10		T178	9		T247	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T48	10		T137	11		T18	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T42	5		T163	1		T137	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T13	10		T54	9		T174	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T5	4		T11	7		T141	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23340

1

T1

156

T2

33

T3

10

auto[1]

auto[0]

4179

1

T1

2

T2

1

T5

17