Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27519

1

T1

158

T2

34

T3

10

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23777

1

T1

158

T2

31

T3

10

auto[ADC_CTRL_FILTER_COND_OUT]

3742

1

T2

3

T5

16

T9

9

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21034

1

T1

144

T2

31

T3

10

auto[1]

6485

1

T1

14

T2

3

T7

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23361

1

T1

149

T2

33

T3

10

auto[1]

4158

1

T1

9

T2

1

T5

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	441	1			T1	2		T9	12		T41	1
values[0]	111	1			T11	3		T228	11		T132	10
values[1]	648	1			T8	24		T27	1		T141	5
values[2]	2941	1			T5	10		T7	1		T14	22
values[3]	655	1			T9	1		T13	11		T104	3
values[4]	731	1			T2	2		T9	8		T12	1
values[5]	794	1			T9	16		T13	13		T140	1
values[6]	541	1			T5	17		T48	20		T39	24
values[7]	833	1			T2	3		T5	6		T163	2
values[8]	788	1			T11	14		T13	6		T54	10
values[9]	1223	1			T1	12		T12	1		T104	14
minimum	17813	1			T1	144		T2	29		T3	10

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	878	1			T8	24		T11	3		T27	1
values[1]	2972	1			T5	10		T7	1		T13	11
values[2]	722	1			T9	1		T12	1		T54	13
values[3]	712	1			T2	2		T9	24		T140	1
values[4]	693	1			T13	13		T48	17		T44	1
values[5]	682	1			T2	3		T5	17		T48	20
values[6]	908	1			T5	6		T44	15		T141	7
values[7]	601	1			T11	14		T13	6		T54	10
values[8]	827	1			T1	12		T12	1		T104	14
values[9]	270	1			T149	9		T244	23		T224	44
minimum	18254	1			T1	146		T2	29		T3	10

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23340

1

T1

156

T2

33

T3

10

auto[1]

4179

1

T1

2

T2

1

T5

17

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T8	12		T141	5		T214	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T11	1		T27	1		T49	23
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1585	1			T7	1		T13	11		T14	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T5	5		T104	1		T42	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T157	12		T131	1		T228	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T9	1		T12	1		T54	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T2	2		T9	5		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T9	2		T163	16		T142	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T13	13		T48	4		T44	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T214	1		T133	12		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T5	9		T48	11		T39	24
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T2	2		T163	15		T143	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T44	1		T163	2		T138	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T5	6		T141	7		T95	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T11	8		T13	6		T54	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T131	1		T97	1		T144	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T1	3		T42	10		T61	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T12	1		T104	1		T141	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T149	1		T224	6		T154	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T244	14		T224	13		T248	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18105	1			T1	146		T2	29		T3	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T299	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T8	12		T214	4		T157	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T11	2		T49	18		T222	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	991	1			T14	20		T40	17		T43	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T5	5		T104	2		T150	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T157	4		T149	10		T143	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T16	3		T158	9		T271	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T9	11		T61	1		T47	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T9	6		T163	14		T142	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T48	13		T142	3		T138	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T214	8		T133	11		T224	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T5	8		T48	9		T138	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T2	1		T143	18		T18	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T44	14		T138	12		T174	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T95	4		T100	11		T222	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T11	6		T223	19		T49	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T97	14		T202	6		T220	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T1	9		T61	8		T214	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T104	13		T95	3		T188	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T149	8		T224	13		T300	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T244	9		T224	12		T248	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T35	1		T44	3		T47	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	431	1			T1	2		T9	12		T41	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T301	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T228	11		T237	6		T302	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T11	1		T132	10		T303	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T8	12		T141	5		T214	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T27	1		T49	23		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1577	1			T7	1		T14	2		T105	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T5	5		T54	13		T222	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T13	11		T31	2		T157	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T9	1		T104	1		T42	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T2	2		T48	4		T61	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T9	2		T12	1		T16	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T9	5		T13	13		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T214	1		T174	4		T17	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T5	9		T48	11		T39	24
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T163	15		T18	4		T133	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T163	2		T98	1		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T2	2		T5	6		T95	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T11	8		T13	6		T54	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T141	7		T131	1		T97	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T1	3		T61	4		T214	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	365	1			T12	1		T104	1		T141	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17677	1			T1	144		T2	29		T3	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T301	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T302	13		T258	11		T304	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T11	2		T277	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T8	12		T214	4		T157	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T49	18		T150	4		T145	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1001	1			T14	20		T40	17		T43	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T5	5		T222	4		T150	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T31	1		T157	4		T149	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T104	2		T158	9		T102	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T48	13		T61	1		T47	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T9	6		T16	3		T163	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T9	11		T138	2		T52	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T214	8		T174	2		T36	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T5	8		T48	9		T44	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T18	1		T133	11		T204	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T150	14		T36	3		T256	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T2	1		T95	4		T100	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T11	6		T138	12		T174	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T97	14		T222	2		T133	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T1	9		T61	8		T214	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T104	13		T95	3		T188	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T35	1		T44	3		T47	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T8	13		T141	1		T214	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T11	3		T27	1		T49	23
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1326	1			T7	1		T13	1		T14	22
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T5	6		T104	3		T42	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T157	5		T131	1		T228	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T9	1		T12	1		T54	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T2	2		T9	12		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T9	7		T163	15		T142	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T13	1		T48	14		T44	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T214	9		T133	12		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T5	9		T48	10		T39	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T2	2		T163	1		T143	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T44	15		T163	1		T138	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T5	1		T141	1		T95	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T11	7		T13	1		T54	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T131	1		T97	15		T144	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T1	10		T42	1		T61	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T12	1		T104	14		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T149	9		T224	14		T154	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T244	10		T224	13		T248	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18242	1			T1	146		T2	29		T3	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T299	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T8	11		T141	4		T137	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T49	18		T222	3		T132	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1250	1			T13	10		T136	43		T26	26
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T5	4		T42	5		T132	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T157	11		T228	8		T143	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T54	12		T16	5		T282	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T9	4		T47	6		T233	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T9	1		T163	15		T142	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T13	12		T48	3		T142	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T133	11		T178	9		T224	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T5	8		T48	10		T39	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T2	1		T163	14		T143	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T163	1		T138	13		T174	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T5	5		T141	6		T95	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T11	7		T13	5		T54	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T144	3		T220	1		T276	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T1	2		T42	9		T61	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T141	4		T95	2		T144	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T224	5		T273	8		T305	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T244	13		T224	12		T248	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T88	3		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T299	8		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	422	1			T1	2		T9	12		T41	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T301	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T228	1		T237	1		T302	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T11	3		T132	1		T303	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T8	13		T141	1		T214	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T27	1		T49	23		T150	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1333	1			T7	1		T14	22		T105	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T5	6		T54	1		T222	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T13	1		T31	3		T157	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T9	1		T104	3		T42	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T2	2		T48	14		T61	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T9	7		T12	1		T16	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T9	12		T13	1		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T214	9		T174	3		T17	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T5	9		T48	10		T39	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T163	1		T18	3		T133	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T163	1		T98	1		T150	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T2	2		T5	1		T95	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T11	7		T13	1		T54	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T141	1		T131	1		T97	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	331	1			T1	10		T61	9		T214	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	398	1			T12	1		T104	14		T141	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17813	1			T1	144		T2	29		T3	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T42	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T228	10		T237	5		T302	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T132	9		T277	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T8	11		T141	4		T137	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T49	18		T146	11		T52	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1245	1			T136	43		T26	26		T173	31
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T5	4		T54	12		T222	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T13	10		T157	11		T228	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T42	5		T228	18		T132	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T48	3		T47	6		T22	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T9	1		T16	5		T163	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T9	4		T13	12		T138	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T174	3		T224	10		T289	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T5	8		T48	10		T39	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T163	14		T18	2		T133	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T163	1		T36	10		T256	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T2	1		T5	5		T95	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T11	7		T13	5		T54	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T141	6		T222	10		T144	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T1	2		T61	3		T223	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T141	4		T95	2		T144	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23340

1

T1

156

T2

33

T3

10

auto[1]

auto[0]

4179

1

T1

2

T2

1

T5

17