Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.76 99.07 96.67 100.00 100.00 98.83 98.33 91.39


Total test records in report: 919
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T795 /workspace/coverage/default/47.adc_ctrl_alert_test.2770255213 Jun 11 03:50:53 PM PDT 24 Jun 11 03:50:55 PM PDT 24 343710637 ps
T796 /workspace/coverage/default/49.adc_ctrl_filters_polled.4129661953 Jun 11 03:51:07 PM PDT 24 Jun 11 03:54:35 PM PDT 24 333725005488 ps
T797 /workspace/coverage/default/13.adc_ctrl_lowpower_counter.346281773 Jun 11 03:44:58 PM PDT 24 Jun 11 03:45:13 PM PDT 24 21734203480 ps
T798 /workspace/coverage/default/34.adc_ctrl_poweron_counter.1633434396 Jun 11 03:48:26 PM PDT 24 Jun 11 03:48:30 PM PDT 24 3532522391 ps
T799 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.814160560 Jun 11 03:43:17 PM PDT 24 Jun 11 03:43:22 PM PDT 24 447328389 ps
T62 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.4186144592 Jun 11 03:43:02 PM PDT 24 Jun 11 03:43:10 PM PDT 24 4565097554 ps
T65 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.942020934 Jun 11 03:42:51 PM PDT 24 Jun 11 03:42:55 PM PDT 24 493311564 ps
T800 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.4107739033 Jun 11 03:43:06 PM PDT 24 Jun 11 03:43:09 PM PDT 24 456712790 ps
T81 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.447163984 Jun 11 03:43:05 PM PDT 24 Jun 11 03:43:07 PM PDT 24 397567615 ps
T68 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3801348107 Jun 11 03:43:06 PM PDT 24 Jun 11 03:43:10 PM PDT 24 455290622 ps
T84 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.973375314 Jun 11 03:42:42 PM PDT 24 Jun 11 03:42:45 PM PDT 24 501956363 ps
T59 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.4019842028 Jun 11 03:43:06 PM PDT 24 Jun 11 03:43:20 PM PDT 24 4849533874 ps
T63 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3184263156 Jun 11 03:42:49 PM PDT 24 Jun 11 03:43:02 PM PDT 24 4204996220 ps
T801 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.2399518856 Jun 11 03:43:14 PM PDT 24 Jun 11 03:43:17 PM PDT 24 495166386 ps
T120 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3272763657 Jun 11 03:42:41 PM PDT 24 Jun 11 03:42:43 PM PDT 24 631598920 ps
T56 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1531821393 Jun 11 03:43:07 PM PDT 24 Jun 11 03:43:12 PM PDT 24 4355780853 ps
T802 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3901150941 Jun 11 03:42:57 PM PDT 24 Jun 11 03:42:59 PM PDT 24 363844557 ps
T60 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.874843975 Jun 11 03:43:01 PM PDT 24 Jun 11 03:43:04 PM PDT 24 549019152 ps
T803 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3577887548 Jun 11 03:42:34 PM PDT 24 Jun 11 03:42:36 PM PDT 24 392040245 ps
T57 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.89428667 Jun 11 03:42:26 PM PDT 24 Jun 11 03:44:13 PM PDT 24 53193618715 ps
T121 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.208916413 Jun 11 03:43:06 PM PDT 24 Jun 11 03:43:09 PM PDT 24 444313496 ps
T64 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3415371881 Jun 11 03:42:34 PM PDT 24 Jun 11 03:42:56 PM PDT 24 8042524257 ps
T804 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.440915416 Jun 11 03:43:00 PM PDT 24 Jun 11 03:43:02 PM PDT 24 278135133 ps
T805 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.1330407606 Jun 11 03:43:15 PM PDT 24 Jun 11 03:43:19 PM PDT 24 340197643 ps
T58 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3766849113 Jun 11 03:42:26 PM PDT 24 Jun 11 03:42:34 PM PDT 24 5726853725 ps
T806 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.358159540 Jun 11 03:43:15 PM PDT 24 Jun 11 03:43:20 PM PDT 24 330174418 ps
T122 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3602200824 Jun 11 03:43:04 PM PDT 24 Jun 11 03:43:06 PM PDT 24 2843178055 ps
T807 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.101903127 Jun 11 03:43:15 PM PDT 24 Jun 11 03:43:18 PM PDT 24 529096450 ps
T82 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1904843969 Jun 11 03:42:41 PM PDT 24 Jun 11 03:42:44 PM PDT 24 370520263 ps
T106 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3334884092 Jun 11 03:42:26 PM PDT 24 Jun 11 03:42:29 PM PDT 24 893654881 ps
T75 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2782777574 Jun 11 03:42:35 PM PDT 24 Jun 11 03:42:38 PM PDT 24 602363572 ps
T71 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3791606137 Jun 11 03:42:58 PM PDT 24 Jun 11 03:43:03 PM PDT 24 534801161 ps
T69 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1989844501 Jun 11 03:42:34 PM PDT 24 Jun 11 03:42:39 PM PDT 24 1220488842 ps
T70 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1640924362 Jun 11 03:42:57 PM PDT 24 Jun 11 03:43:00 PM PDT 24 1003150907 ps
T808 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1797736193 Jun 11 03:43:07 PM PDT 24 Jun 11 03:43:09 PM PDT 24 694273993 ps
T123 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.329294432 Jun 11 03:42:56 PM PDT 24 Jun 11 03:43:01 PM PDT 24 3841910344 ps
T76 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.4274790527 Jun 11 03:42:42 PM PDT 24 Jun 11 03:42:49 PM PDT 24 4239106947 ps
T809 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1112689932 Jun 11 03:42:18 PM PDT 24 Jun 11 03:42:22 PM PDT 24 455561285 ps
T74 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3136161960 Jun 11 03:42:25 PM PDT 24 Jun 11 03:42:28 PM PDT 24 535375264 ps
T810 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.3408396708 Jun 11 03:43:07 PM PDT 24 Jun 11 03:43:10 PM PDT 24 346924691 ps
T811 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.3650119491 Jun 11 03:42:50 PM PDT 24 Jun 11 03:42:53 PM PDT 24 482626751 ps
T812 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.329338881 Jun 11 03:43:12 PM PDT 24 Jun 11 03:43:15 PM PDT 24 476779060 ps
T124 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3885944017 Jun 11 03:42:58 PM PDT 24 Jun 11 03:43:04 PM PDT 24 2428325519 ps
T125 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2365849885 Jun 11 03:42:42 PM PDT 24 Jun 11 03:42:56 PM PDT 24 4938951327 ps
T813 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3832287663 Jun 11 03:43:14 PM PDT 24 Jun 11 03:43:17 PM PDT 24 421415060 ps
T107 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1429837220 Jun 11 03:42:18 PM PDT 24 Jun 11 03:42:20 PM PDT 24 471340343 ps
T108 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.570634233 Jun 11 03:42:25 PM PDT 24 Jun 11 03:42:59 PM PDT 24 52529125628 ps
T814 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.83375901 Jun 11 03:42:34 PM PDT 24 Jun 11 03:42:37 PM PDT 24 523696729 ps
T77 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1790961988 Jun 11 03:42:54 PM PDT 24 Jun 11 03:43:01 PM PDT 24 8218916035 ps
T815 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.1545607260 Jun 11 03:43:14 PM PDT 24 Jun 11 03:43:17 PM PDT 24 355159036 ps
T816 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.4016727954 Jun 11 03:43:05 PM PDT 24 Jun 11 03:43:07 PM PDT 24 419447171 ps
T817 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.3652336909 Jun 11 03:43:14 PM PDT 24 Jun 11 03:43:17 PM PDT 24 421108179 ps
T342 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.121813319 Jun 11 03:42:40 PM PDT 24 Jun 11 03:42:48 PM PDT 24 8922042182 ps
T818 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.4276365294 Jun 11 03:42:18 PM PDT 24 Jun 11 03:42:22 PM PDT 24 1395078751 ps
T819 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1093033516 Jun 11 03:42:41 PM PDT 24 Jun 11 03:42:45 PM PDT 24 412239105 ps
T820 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.859204592 Jun 11 03:42:26 PM PDT 24 Jun 11 03:42:31 PM PDT 24 1302909968 ps
T109 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.768878088 Jun 11 03:43:06 PM PDT 24 Jun 11 03:43:09 PM PDT 24 426860597 ps
T821 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1214042479 Jun 11 03:43:02 PM PDT 24 Jun 11 03:43:05 PM PDT 24 485844238 ps
T822 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2705833794 Jun 11 03:43:05 PM PDT 24 Jun 11 03:43:09 PM PDT 24 619487681 ps
T823 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2939471283 Jun 11 03:42:58 PM PDT 24 Jun 11 03:43:08 PM PDT 24 4585144437 ps
T824 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.182370236 Jun 11 03:42:35 PM PDT 24 Jun 11 03:42:40 PM PDT 24 5338297614 ps
T825 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2176718244 Jun 11 03:43:06 PM PDT 24 Jun 11 03:43:15 PM PDT 24 3804139990 ps
T826 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2537053127 Jun 11 03:42:34 PM PDT 24 Jun 11 03:42:37 PM PDT 24 496263604 ps
T827 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.50634245 Jun 11 03:42:35 PM PDT 24 Jun 11 03:42:39 PM PDT 24 1209097618 ps
T110 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1591395659 Jun 11 03:42:25 PM PDT 24 Jun 11 03:42:28 PM PDT 24 325666821 ps
T828 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.2970715518 Jun 11 03:43:08 PM PDT 24 Jun 11 03:43:11 PM PDT 24 515988252 ps
T829 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.4140678543 Jun 11 03:42:58 PM PDT 24 Jun 11 03:43:02 PM PDT 24 522482217 ps
T830 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3185679123 Jun 11 03:42:19 PM PDT 24 Jun 11 03:42:22 PM PDT 24 1134356282 ps
T831 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3646290142 Jun 11 03:42:39 PM PDT 24 Jun 11 03:42:41 PM PDT 24 434874629 ps
T832 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.3322423319 Jun 11 03:42:31 PM PDT 24 Jun 11 03:42:52 PM PDT 24 8065567855 ps
T833 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.1057461530 Jun 11 03:43:16 PM PDT 24 Jun 11 03:43:21 PM PDT 24 540652713 ps
T111 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.3354241273 Jun 11 03:42:33 PM PDT 24 Jun 11 03:42:38 PM PDT 24 1420108920 ps
T834 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3791974427 Jun 11 03:43:06 PM PDT 24 Jun 11 03:43:09 PM PDT 24 411436927 ps
T835 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.355855844 Jun 11 03:42:36 PM PDT 24 Jun 11 03:42:39 PM PDT 24 5080201533 ps
T836 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.1584569455 Jun 11 03:42:33 PM PDT 24 Jun 11 03:42:39 PM PDT 24 4834166743 ps
T112 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3427488385 Jun 11 03:42:30 PM PDT 24 Jun 11 03:42:34 PM PDT 24 1097942670 ps
T837 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.42357195 Jun 11 03:42:42 PM PDT 24 Jun 11 03:42:44 PM PDT 24 439752426 ps
T838 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.3883955420 Jun 11 03:42:51 PM PDT 24 Jun 11 03:42:55 PM PDT 24 4902426651 ps
T839 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.753681511 Jun 11 03:43:08 PM PDT 24 Jun 11 03:43:11 PM PDT 24 381491775 ps
T840 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.109861366 Jun 11 03:42:57 PM PDT 24 Jun 11 03:43:00 PM PDT 24 447867811 ps
T113 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3433469102 Jun 11 03:42:50 PM PDT 24 Jun 11 03:42:52 PM PDT 24 309769497 ps
T841 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.4164072325 Jun 11 03:42:35 PM PDT 24 Jun 11 03:42:37 PM PDT 24 421922991 ps
T842 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.89311265 Jun 11 03:43:05 PM PDT 24 Jun 11 03:43:07 PM PDT 24 335468392 ps
T114 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2329634765 Jun 11 03:42:50 PM PDT 24 Jun 11 03:42:52 PM PDT 24 337662881 ps
T843 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.3521674025 Jun 11 03:42:49 PM PDT 24 Jun 11 03:42:51 PM PDT 24 696603293 ps
T844 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1493877716 Jun 11 03:43:06 PM PDT 24 Jun 11 03:43:10 PM PDT 24 578417265 ps
T845 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3133844819 Jun 11 03:42:33 PM PDT 24 Jun 11 03:42:49 PM PDT 24 4130876702 ps
T846 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2538156920 Jun 11 03:42:58 PM PDT 24 Jun 11 03:43:02 PM PDT 24 499013267 ps
T847 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.98238422 Jun 11 03:42:19 PM PDT 24 Jun 11 03:42:21 PM PDT 24 457528255 ps
T848 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.3030634342 Jun 11 03:42:34 PM PDT 24 Jun 11 03:42:38 PM PDT 24 847383420 ps
T849 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3105019937 Jun 11 03:43:06 PM PDT 24 Jun 11 03:43:16 PM PDT 24 8180588069 ps
T115 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.122144987 Jun 11 03:42:35 PM PDT 24 Jun 11 03:42:37 PM PDT 24 721943634 ps
T850 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.478868718 Jun 11 03:42:36 PM PDT 24 Jun 11 03:42:49 PM PDT 24 5121574335 ps
T851 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.2248158031 Jun 11 03:42:35 PM PDT 24 Jun 11 03:42:37 PM PDT 24 377580161 ps
T852 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.3582688048 Jun 11 03:43:15 PM PDT 24 Jun 11 03:43:18 PM PDT 24 593553817 ps
T116 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2701482528 Jun 11 03:42:18 PM PDT 24 Jun 11 03:42:21 PM PDT 24 1268904931 ps
T117 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.4280814409 Jun 11 03:42:41 PM PDT 24 Jun 11 03:42:43 PM PDT 24 830594146 ps
T853 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3034898972 Jun 11 03:42:50 PM PDT 24 Jun 11 03:42:52 PM PDT 24 576624562 ps
T854 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.1124529369 Jun 11 03:42:43 PM PDT 24 Jun 11 03:42:46 PM PDT 24 518625123 ps
T855 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.1425516232 Jun 11 03:42:18 PM PDT 24 Jun 11 03:42:21 PM PDT 24 699430313 ps
T856 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.678263839 Jun 11 03:42:49 PM PDT 24 Jun 11 03:42:52 PM PDT 24 475188618 ps
T857 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2363962680 Jun 11 03:42:25 PM PDT 24 Jun 11 03:42:28 PM PDT 24 591102990 ps
T858 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1113622512 Jun 11 03:42:19 PM PDT 24 Jun 11 03:43:27 PM PDT 24 52545146537 ps
T859 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.180753524 Jun 11 03:43:04 PM PDT 24 Jun 11 03:43:07 PM PDT 24 399748417 ps
T860 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.1756706368 Jun 11 03:42:18 PM PDT 24 Jun 11 03:42:22 PM PDT 24 2581758143 ps
T861 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1198487429 Jun 11 03:43:15 PM PDT 24 Jun 11 03:43:19 PM PDT 24 418217835 ps
T862 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3631631196 Jun 11 03:42:27 PM PDT 24 Jun 11 03:42:32 PM PDT 24 1176442801 ps
T863 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.4292642632 Jun 11 03:43:00 PM PDT 24 Jun 11 03:43:02 PM PDT 24 362165746 ps
T864 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.3007575139 Jun 11 03:43:06 PM PDT 24 Jun 11 03:43:08 PM PDT 24 315047919 ps
T865 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.334556440 Jun 11 03:43:15 PM PDT 24 Jun 11 03:43:20 PM PDT 24 316587376 ps
T866 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1564160859 Jun 11 03:43:05 PM PDT 24 Jun 11 03:43:08 PM PDT 24 337832725 ps
T867 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.909178331 Jun 11 03:42:57 PM PDT 24 Jun 11 03:42:59 PM PDT 24 439037849 ps
T868 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.4160143738 Jun 11 03:43:13 PM PDT 24 Jun 11 03:43:15 PM PDT 24 367445268 ps
T869 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.3795406035 Jun 11 03:43:14 PM PDT 24 Jun 11 03:43:17 PM PDT 24 465555513 ps
T870 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1398812395 Jun 11 03:42:17 PM PDT 24 Jun 11 03:42:19 PM PDT 24 550152936 ps
T871 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3878203698 Jun 11 03:43:14 PM PDT 24 Jun 11 03:43:17 PM PDT 24 418695225 ps
T872 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3520982626 Jun 11 03:42:18 PM PDT 24 Jun 11 03:42:26 PM PDT 24 4605275990 ps
T873 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.227789389 Jun 11 03:42:49 PM PDT 24 Jun 11 03:42:56 PM PDT 24 2448216707 ps
T874 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2145579460 Jun 11 03:42:51 PM PDT 24 Jun 11 03:42:53 PM PDT 24 523112360 ps
T875 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2428514937 Jun 11 03:42:49 PM PDT 24 Jun 11 03:42:52 PM PDT 24 2128934516 ps
T876 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2744269320 Jun 11 03:43:05 PM PDT 24 Jun 11 03:43:13 PM PDT 24 5305229219 ps
T341 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1765062582 Jun 11 03:42:25 PM PDT 24 Jun 11 03:42:30 PM PDT 24 4877870415 ps
T877 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.2530747936 Jun 11 03:43:06 PM PDT 24 Jun 11 03:43:11 PM PDT 24 474610834 ps
T78 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1733372713 Jun 11 03:43:05 PM PDT 24 Jun 11 03:43:13 PM PDT 24 8096951866 ps
T878 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1768013841 Jun 11 03:43:14 PM PDT 24 Jun 11 03:43:17 PM PDT 24 277659204 ps
T879 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.872866992 Jun 11 03:42:24 PM PDT 24 Jun 11 03:42:26 PM PDT 24 340412632 ps
T880 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1342294947 Jun 11 03:42:24 PM PDT 24 Jun 11 03:42:35 PM PDT 24 2012432668 ps
T118 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.2786743882 Jun 11 03:42:34 PM PDT 24 Jun 11 03:42:37 PM PDT 24 533264281 ps
T881 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2323831052 Jun 11 03:42:26 PM PDT 24 Jun 11 03:42:30 PM PDT 24 1306207459 ps
T882 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.4127521054 Jun 11 03:43:00 PM PDT 24 Jun 11 03:43:06 PM PDT 24 4218159980 ps
T883 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.4037117559 Jun 11 03:43:14 PM PDT 24 Jun 11 03:43:16 PM PDT 24 433429848 ps
T884 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.3862579271 Jun 11 03:43:14 PM PDT 24 Jun 11 03:43:18 PM PDT 24 346861573 ps
T885 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.1370303137 Jun 11 03:43:07 PM PDT 24 Jun 11 03:43:10 PM PDT 24 487763198 ps
T886 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.2696615981 Jun 11 03:42:27 PM PDT 24 Jun 11 03:42:29 PM PDT 24 357465990 ps
T887 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.1647420120 Jun 11 03:42:25 PM PDT 24 Jun 11 03:42:27 PM PDT 24 649683997 ps
T888 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.2950105630 Jun 11 03:43:14 PM PDT 24 Jun 11 03:43:16 PM PDT 24 348405444 ps
T889 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.981271303 Jun 11 03:43:04 PM PDT 24 Jun 11 03:43:17 PM PDT 24 8236404323 ps
T890 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.919227178 Jun 11 03:42:34 PM PDT 24 Jun 11 03:42:37 PM PDT 24 478075864 ps
T891 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.3290168278 Jun 11 03:42:19 PM PDT 24 Jun 11 03:42:21 PM PDT 24 605233311 ps
T892 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1004071310 Jun 11 03:43:01 PM PDT 24 Jun 11 03:43:04 PM PDT 24 796683665 ps
T893 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.4177907186 Jun 11 03:43:14 PM PDT 24 Jun 11 03:43:17 PM PDT 24 411784980 ps
T894 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2701409875 Jun 11 03:42:41 PM PDT 24 Jun 11 03:43:03 PM PDT 24 8587225181 ps
T343 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2288744911 Jun 11 03:42:18 PM PDT 24 Jun 11 03:42:23 PM PDT 24 4304296036 ps
T895 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.913183103 Jun 11 03:42:56 PM PDT 24 Jun 11 03:42:58 PM PDT 24 664281166 ps
T896 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2512699169 Jun 11 03:43:05 PM PDT 24 Jun 11 03:43:14 PM PDT 24 8626833577 ps
T897 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.1585627444 Jun 11 03:43:14 PM PDT 24 Jun 11 03:43:18 PM PDT 24 372681291 ps
T898 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.1306882750 Jun 11 03:42:42 PM PDT 24 Jun 11 03:42:44 PM PDT 24 522816053 ps
T899 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.352357170 Jun 11 03:43:05 PM PDT 24 Jun 11 03:43:08 PM PDT 24 463267200 ps
T900 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3239005600 Jun 11 03:42:54 PM PDT 24 Jun 11 03:42:57 PM PDT 24 523464204 ps
T119 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2044724918 Jun 11 03:42:30 PM PDT 24 Jun 11 03:43:00 PM PDT 24 28081149939 ps
T901 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2100081886 Jun 11 03:42:42 PM PDT 24 Jun 11 03:42:49 PM PDT 24 2304139785 ps
T902 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1619953920 Jun 11 03:42:19 PM PDT 24 Jun 11 03:42:21 PM PDT 24 407060955 ps
T903 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.4063705118 Jun 11 03:42:35 PM PDT 24 Jun 11 03:43:09 PM PDT 24 30634466808 ps
T904 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.4116162649 Jun 11 03:42:33 PM PDT 24 Jun 11 03:42:38 PM PDT 24 518465053 ps
T905 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1400227260 Jun 11 03:43:05 PM PDT 24 Jun 11 03:43:07 PM PDT 24 516954003 ps
T906 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2805964341 Jun 11 03:42:41 PM PDT 24 Jun 11 03:42:46 PM PDT 24 596155427 ps
T907 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1744569384 Jun 11 03:43:06 PM PDT 24 Jun 11 03:43:09 PM PDT 24 499421069 ps
T908 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.4271115213 Jun 11 03:42:56 PM PDT 24 Jun 11 03:42:58 PM PDT 24 499738278 ps
T909 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.645209422 Jun 11 03:43:08 PM PDT 24 Jun 11 03:43:11 PM PDT 24 386611381 ps
T910 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.1645467592 Jun 11 03:43:12 PM PDT 24 Jun 11 03:43:15 PM PDT 24 499837724 ps
T911 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.4246309714 Jun 11 03:42:56 PM PDT 24 Jun 11 03:42:58 PM PDT 24 362954049 ps
T912 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.157614342 Jun 11 03:43:07 PM PDT 24 Jun 11 03:43:10 PM PDT 24 509427540 ps
T913 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.4054809427 Jun 11 03:42:34 PM PDT 24 Jun 11 03:42:39 PM PDT 24 4117566637 ps
T914 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.4240445065 Jun 11 03:42:51 PM PDT 24 Jun 11 03:42:53 PM PDT 24 328579131 ps
T915 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3515276698 Jun 11 03:43:06 PM PDT 24 Jun 11 03:43:09 PM PDT 24 577000201 ps
T916 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1289649803 Jun 11 03:43:00 PM PDT 24 Jun 11 03:43:22 PM PDT 24 8370761380 ps
T917 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.4191127189 Jun 11 03:42:26 PM PDT 24 Jun 11 03:42:29 PM PDT 24 557468375 ps
T918 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.861107548 Jun 11 03:42:59 PM PDT 24 Jun 11 03:43:07 PM PDT 24 4338789485 ps
T919 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3690724440 Jun 11 03:42:26 PM PDT 24 Jun 11 03:42:28 PM PDT 24 550906562 ps

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.591473348
Short name T9
Test name
Test status
Simulation time 1263694189518 ps
CPU time 1017.01 seconds
Started Jun 11 03:48:57 PM PDT 24
Finished Jun 11 04:05:56 PM PDT 24
Peak memory 218468 kb
Host smart-9a1f22bf-b239-47b7-b551-9d10e89491a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591473348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all.
591473348
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.3144654573
Short name T49
Test name
Test status
Simulation time 923682347374 ps
CPU time 1091.08 seconds
Started Jun 11 03:48:12 PM PDT 24
Finished Jun 11 04:06:24 PM PDT 24
Peak memory 210480 kb
Host smart-1eb10a6d-2a8b-4789-bcbf-8ff9de180d6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144654573 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.3144654573
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.2211356994
Short name T5
Test name
Test status
Simulation time 551728557637 ps
CPU time 725.79 seconds
Started Jun 11 03:44:29 PM PDT 24
Finished Jun 11 03:56:36 PM PDT 24
Peak memory 201980 kb
Host smart-3a1245ac-d957-4a47-94b3-ad2c88ec388a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211356994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.2211356994
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.2900284448
Short name T52
Test name
Test status
Simulation time 526958702403 ps
CPU time 310.16 seconds
Started Jun 11 03:44:27 PM PDT 24
Finished Jun 11 03:49:39 PM PDT 24
Peak memory 210224 kb
Host smart-cae05890-244a-49e4-8c17-0c1a8a69f788
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900284448 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.2900284448
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.4149123033
Short name T18
Test name
Test status
Simulation time 71580994721 ps
CPU time 39.8 seconds
Started Jun 11 03:45:25 PM PDT 24
Finished Jun 11 03:46:06 PM PDT 24
Peak memory 201980 kb
Host smart-775d3595-7918-4b43-aa97-0b38681425c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149123033 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.4149123033
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.4270440974
Short name T143
Test name
Test status
Simulation time 556747059627 ps
CPU time 165.92 seconds
Started Jun 11 03:48:40 PM PDT 24
Finished Jun 11 03:51:27 PM PDT 24
Peak memory 201788 kb
Host smart-1023ed79-c341-40c0-930b-6ed320cef991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270440974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.4270440974
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.235455490
Short name T138
Test name
Test status
Simulation time 528445430123 ps
CPU time 1359.89 seconds
Started Jun 11 03:45:35 PM PDT 24
Finished Jun 11 04:08:16 PM PDT 24
Peak memory 201816 kb
Host smart-32ac815c-bb01-4edd-856d-7303707405ce
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235455490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gati
ng.235455490
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.3622764869
Short name T149
Test name
Test status
Simulation time 493792151448 ps
CPU time 1265.11 seconds
Started Jun 11 03:47:28 PM PDT 24
Finished Jun 11 04:08:35 PM PDT 24
Peak memory 201800 kb
Host smart-020271bf-505e-4b7c-8688-ad4205246661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622764869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.3622764869
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.1472711010
Short name T163
Test name
Test status
Simulation time 506049516030 ps
CPU time 1082.68 seconds
Started Jun 11 03:46:07 PM PDT 24
Finished Jun 11 04:04:11 PM PDT 24
Peak memory 201848 kb
Host smart-caf74559-ae4f-4ad9-88d8-38507cd9ffb9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472711010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.1472711010
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.3935020775
Short name T14
Test name
Test status
Simulation time 328035739101 ps
CPU time 78.74 seconds
Started Jun 11 03:44:53 PM PDT 24
Finished Jun 11 03:46:13 PM PDT 24
Peak memory 201824 kb
Host smart-c03b3f41-ce07-4129-a0a2-46cb4eac0ed0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935020775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.3935020775
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.1391532436
Short name T46
Test name
Test status
Simulation time 8609478195 ps
CPU time 5.86 seconds
Started Jun 11 03:44:27 PM PDT 24
Finished Jun 11 03:44:34 PM PDT 24
Peak memory 218416 kb
Host smart-b5675c7d-656e-4887-8ceb-5506b7ed178e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391532436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.1391532436
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.3092205469
Short name T224
Test name
Test status
Simulation time 561673896729 ps
CPU time 352.15 seconds
Started Jun 11 03:48:27 PM PDT 24
Finished Jun 11 03:54:20 PM PDT 24
Peak memory 201816 kb
Host smart-a101d3d4-71ad-4593-bea2-73d6ff46fe7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092205469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.3092205469
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.112062558
Short name T222
Test name
Test status
Simulation time 502200152551 ps
CPU time 323.86 seconds
Started Jun 11 03:48:35 PM PDT 24
Finished Jun 11 03:54:00 PM PDT 24
Peak memory 201804 kb
Host smart-40aeabb6-a979-414c-865c-3f5990ff6d3f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112062558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gati
ng.112062558
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.942020934
Short name T65
Test name
Test status
Simulation time 493311564 ps
CPU time 2.85 seconds
Started Jun 11 03:42:51 PM PDT 24
Finished Jun 11 03:42:55 PM PDT 24
Peak memory 218244 kb
Host smart-a9d8bc49-b9a9-4bad-8590-4965091a514f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942020934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.942020934
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.4150092455
Short name T159
Test name
Test status
Simulation time 344376043157 ps
CPU time 212.46 seconds
Started Jun 11 03:48:25 PM PDT 24
Finished Jun 11 03:51:59 PM PDT 24
Peak memory 201876 kb
Host smart-a5d49f3d-dfca-4eb3-99ee-7877fef956f0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150092455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.4150092455
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.3447978014
Short name T100
Test name
Test status
Simulation time 333059656829 ps
CPU time 202.11 seconds
Started Jun 11 03:50:43 PM PDT 24
Finished Jun 11 03:54:05 PM PDT 24
Peak memory 201800 kb
Host smart-214a8827-cf42-4a58-82bd-974888494a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447978014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.3447978014
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.570634233
Short name T108
Test name
Test status
Simulation time 52529125628 ps
CPU time 32.27 seconds
Started Jun 11 03:42:25 PM PDT 24
Finished Jun 11 03:42:59 PM PDT 24
Peak memory 202004 kb
Host smart-d6b3ebe7-fe2c-420d-8042-2f30d8074e3d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570634233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_b
ash.570634233
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.3925608619
Short name T36
Test name
Test status
Simulation time 460787523638 ps
CPU time 1010.49 seconds
Started Jun 11 03:50:02 PM PDT 24
Finished Jun 11 04:06:53 PM PDT 24
Peak memory 202104 kb
Host smart-1f26e034-2db5-4200-ab94-d9edbf41ed87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925608619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.3925608619
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.3372600857
Short name T135
Test name
Test status
Simulation time 497164185182 ps
CPU time 335.41 seconds
Started Jun 11 03:49:22 PM PDT 24
Finished Jun 11 03:54:58 PM PDT 24
Peak memory 201820 kb
Host smart-96102598-6831-4ebd-8804-0132de25eba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372600857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.3372600857
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.762808958
Short name T243
Test name
Test status
Simulation time 522303282770 ps
CPU time 327.49 seconds
Started Jun 11 03:45:57 PM PDT 24
Finished Jun 11 03:51:26 PM PDT 24
Peak memory 201804 kb
Host smart-6fe98b29-9ca0-4636-80fe-c1eb98680cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762808958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.762808958
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.2878174494
Short name T142
Test name
Test status
Simulation time 357110269604 ps
CPU time 878.79 seconds
Started Jun 11 03:46:15 PM PDT 24
Finished Jun 11 04:00:56 PM PDT 24
Peak memory 201840 kb
Host smart-a4438a31-32ce-4b2b-826c-b16ac1fd8bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878174494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.2878174494
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.2961939207
Short name T129
Test name
Test status
Simulation time 402550613611 ps
CPU time 511.32 seconds
Started Jun 11 03:51:00 PM PDT 24
Finished Jun 11 03:59:32 PM PDT 24
Peak memory 201764 kb
Host smart-a6f9d40d-2a1a-4836-aad9-59c77652383e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961939207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.2961939207
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.3800080231
Short name T160
Test name
Test status
Simulation time 540407100917 ps
CPU time 233.96 seconds
Started Jun 11 03:47:22 PM PDT 24
Finished Jun 11 03:51:17 PM PDT 24
Peak memory 201820 kb
Host smart-a2174ea2-c879-4de1-a4cf-4a64e3ad0ad9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800080231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.3800080231
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.2736442663
Short name T183
Test name
Test status
Simulation time 501690795769 ps
CPU time 1115.45 seconds
Started Jun 11 03:48:33 PM PDT 24
Finished Jun 11 04:07:10 PM PDT 24
Peak memory 201808 kb
Host smart-871e05cc-79a9-486a-a5ca-4b37e83ccd0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736442663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.2736442663
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.3572079232
Short name T225
Test name
Test status
Simulation time 568767424606 ps
CPU time 1445.11 seconds
Started Jun 11 03:49:45 PM PDT 24
Finished Jun 11 04:13:51 PM PDT 24
Peak memory 201776 kb
Host smart-eae056ca-b539-4b1f-8d86-63ff425576c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572079232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.3572079232
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.1007656857
Short name T240
Test name
Test status
Simulation time 73815588350 ps
CPU time 47.73 seconds
Started Jun 11 03:45:01 PM PDT 24
Finished Jun 11 03:45:50 PM PDT 24
Peak memory 210060 kb
Host smart-c1b5d8d0-3556-4e78-9864-250f32e2e75a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007656857 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.1007656857
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.2453027652
Short name T53
Test name
Test status
Simulation time 496391292 ps
CPU time 1.26 seconds
Started Jun 11 03:45:15 PM PDT 24
Finished Jun 11 03:45:18 PM PDT 24
Peak memory 201464 kb
Host smart-79ef6486-852a-442d-be9f-6da7fd15c8fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453027652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.2453027652
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1790961988
Short name T77
Test name
Test status
Simulation time 8218916035 ps
CPU time 6.82 seconds
Started Jun 11 03:42:54 PM PDT 24
Finished Jun 11 03:43:01 PM PDT 24
Peak memory 201956 kb
Host smart-93fa4b53-27b3-4ea7-82bc-918eb61dbea0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790961988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.1790961988
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.3206887191
Short name T307
Test name
Test status
Simulation time 344864138579 ps
CPU time 376.45 seconds
Started Jun 11 03:46:22 PM PDT 24
Finished Jun 11 03:52:41 PM PDT 24
Peak memory 201832 kb
Host smart-e6e9b57a-4374-4889-952f-afa4c1eb3356
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206887191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.3206887191
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.100314383
Short name T258
Test name
Test status
Simulation time 518645358328 ps
CPU time 906.06 seconds
Started Jun 11 03:50:01 PM PDT 24
Finished Jun 11 04:05:08 PM PDT 24
Peak memory 201820 kb
Host smart-d4b1ea1c-176b-4f9d-9c55-bbce458da97b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100314383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gati
ng.100314383
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.43635066
Short name T93
Test name
Test status
Simulation time 619003298732 ps
CPU time 179.42 seconds
Started Jun 11 03:45:32 PM PDT 24
Finished Jun 11 03:48:33 PM PDT 24
Peak memory 210228 kb
Host smart-4c97d53a-0304-4bd8-9d49-9e8f1e0e22d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43635066 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.43635066
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.3094525308
Short name T319
Test name
Test status
Simulation time 537709439202 ps
CPU time 1347.04 seconds
Started Jun 11 03:44:53 PM PDT 24
Finished Jun 11 04:07:22 PM PDT 24
Peak memory 201968 kb
Host smart-fb5938ae-59dc-4342-8248-4978f6b522b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094525308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.3094525308
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.1472731056
Short name T255
Test name
Test status
Simulation time 519898444344 ps
CPU time 1279.61 seconds
Started Jun 11 03:47:44 PM PDT 24
Finished Jun 11 04:09:04 PM PDT 24
Peak memory 201804 kb
Host smart-e24ab210-78ae-4fb2-af46-71fed917f407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472731056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.1472731056
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3766849113
Short name T58
Test name
Test status
Simulation time 5726853725 ps
CPU time 6.16 seconds
Started Jun 11 03:42:26 PM PDT 24
Finished Jun 11 03:42:34 PM PDT 24
Peak memory 201976 kb
Host smart-58df11cd-d055-4ae7-be92-450dcda1743c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766849113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.3766849113
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.1815320904
Short name T213
Test name
Test status
Simulation time 503373293187 ps
CPU time 129.37 seconds
Started Jun 11 03:45:34 PM PDT 24
Finished Jun 11 03:47:45 PM PDT 24
Peak memory 201816 kb
Host smart-264a3cc9-3e96-4409-b226-52b8439a26fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815320904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.1815320904
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.2739150611
Short name T13
Test name
Test status
Simulation time 620943771656 ps
CPU time 1457.51 seconds
Started Jun 11 03:47:29 PM PDT 24
Finished Jun 11 04:11:48 PM PDT 24
Peak memory 201960 kb
Host smart-1101d7b7-68b5-4496-ab63-0dbbf94fae5b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739150611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.2739150611
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.944951794
Short name T247
Test name
Test status
Simulation time 490635539644 ps
CPU time 1204.92 seconds
Started Jun 11 03:44:49 PM PDT 24
Finished Jun 11 04:04:56 PM PDT 24
Peak memory 201788 kb
Host smart-01d23324-1d3f-45a9-beb1-1b42696ef0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944951794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.944951794
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.2796548841
Short name T235
Test name
Test status
Simulation time 114725029758 ps
CPU time 70.28 seconds
Started Jun 11 03:44:18 PM PDT 24
Finished Jun 11 03:45:29 PM PDT 24
Peak memory 210056 kb
Host smart-5aafa7ad-09d6-4274-83f9-b666ebb79678
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796548841 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.2796548841
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.1423389103
Short name T168
Test name
Test status
Simulation time 343446079188 ps
CPU time 59.54 seconds
Started Jun 11 03:49:53 PM PDT 24
Finished Jun 11 03:50:54 PM PDT 24
Peak memory 201800 kb
Host smart-d1fe528b-7d3c-4e51-8d67-d53c66afe5b8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423389103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.1423389103
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.678480094
Short name T11
Test name
Test status
Simulation time 414038193700 ps
CPU time 858.42 seconds
Started Jun 11 03:50:35 PM PDT 24
Finished Jun 11 04:04:54 PM PDT 24
Peak memory 201688 kb
Host smart-18f0559d-fa72-4fd9-af38-5f5515e17428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678480094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.678480094
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.2401316744
Short name T177
Test name
Test status
Simulation time 493724131342 ps
CPU time 307.44 seconds
Started Jun 11 03:48:43 PM PDT 24
Finished Jun 11 03:53:52 PM PDT 24
Peak memory 201808 kb
Host smart-e833ef32-405c-40b6-9baa-d11a09626803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401316744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.2401316744
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1640924362
Short name T70
Test name
Test status
Simulation time 1003150907 ps
CPU time 2.26 seconds
Started Jun 11 03:42:57 PM PDT 24
Finished Jun 11 03:43:00 PM PDT 24
Peak memory 201952 kb
Host smart-8f1bb749-d185-4a5a-bd54-25c87a147dad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640924362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.1640924362
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.3705951184
Short name T292
Test name
Test status
Simulation time 546921709164 ps
CPU time 1260.05 seconds
Started Jun 11 03:44:36 PM PDT 24
Finished Jun 11 04:05:38 PM PDT 24
Peak memory 201828 kb
Host smart-b8ac30e9-3668-4d0f-84eb-195749a70e78
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705951184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.3705951184
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.1238357623
Short name T144
Test name
Test status
Simulation time 536568190180 ps
CPU time 939.14 seconds
Started Jun 11 03:45:15 PM PDT 24
Finished Jun 11 04:00:56 PM PDT 24
Peak memory 201784 kb
Host smart-00e8ef3e-d829-456d-be3d-d50bcb4196f2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238357623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.1238357623
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.1735766671
Short name T21
Test name
Test status
Simulation time 564024264703 ps
CPU time 142.59 seconds
Started Jun 11 03:46:16 PM PDT 24
Finished Jun 11 03:48:41 PM PDT 24
Peak memory 210432 kb
Host smart-76b451e6-8eef-4155-b583-a75bd6c5bc37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735766671 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.1735766671
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.2298365469
Short name T301
Test name
Test status
Simulation time 336753721980 ps
CPU time 210.64 seconds
Started Jun 11 03:44:49 PM PDT 24
Finished Jun 11 03:48:20 PM PDT 24
Peak memory 201520 kb
Host smart-65842fd4-ad85-4746-86f7-5a190a71fdf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298365469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.2298365469
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.214066208
Short name T291
Test name
Test status
Simulation time 394189401223 ps
CPU time 128.14 seconds
Started Jun 11 03:45:18 PM PDT 24
Finished Jun 11 03:47:27 PM PDT 24
Peak memory 201800 kb
Host smart-7748ae18-7137-4002-9e73-a02537380ab6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214066208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_
wakeup.214066208
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.359142344
Short name T203
Test name
Test status
Simulation time 261877809677 ps
CPU time 890.24 seconds
Started Jun 11 03:49:13 PM PDT 24
Finished Jun 11 04:04:04 PM PDT 24
Peak memory 218464 kb
Host smart-795ea178-c2b3-45e5-8a58-5e551754c834
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359142344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all.
359142344
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.37778227
Short name T19
Test name
Test status
Simulation time 147776712853 ps
CPU time 53.32 seconds
Started Jun 11 03:49:12 PM PDT 24
Finished Jun 11 03:50:06 PM PDT 24
Peak memory 210184 kb
Host smart-ebaad1dc-b3df-4eda-8cb7-ec4c55a05741
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37778227 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.37778227
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.4078036975
Short name T90
Test name
Test status
Simulation time 509596116110 ps
CPU time 306.23 seconds
Started Jun 11 03:44:20 PM PDT 24
Finished Jun 11 03:49:27 PM PDT 24
Peak memory 201824 kb
Host smart-32e94767-c604-4bff-a73f-c85a717a4f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078036975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.4078036975
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.1222607565
Short name T206
Test name
Test status
Simulation time 121851303751 ps
CPU time 349.82 seconds
Started Jun 11 03:45:00 PM PDT 24
Finished Jun 11 03:50:52 PM PDT 24
Peak memory 201708 kb
Host smart-66d0f22c-34c2-443a-87e4-2a7dc8ecc145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222607565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.1222607565
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.3976043228
Short name T252
Test name
Test status
Simulation time 325693002710 ps
CPU time 863.54 seconds
Started Jun 11 03:50:19 PM PDT 24
Finished Jun 11 04:04:44 PM PDT 24
Peak memory 201788 kb
Host smart-248fec61-d0bf-4d3f-8ca3-3c9bbc38bc9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976043228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.3976043228
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.2520730947
Short name T356
Test name
Test status
Simulation time 616227123374 ps
CPU time 702.39 seconds
Started Jun 11 03:44:51 PM PDT 24
Finished Jun 11 03:56:35 PM PDT 24
Peak memory 201808 kb
Host smart-ec54696d-7ee4-4784-810d-3fd489567e48
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520730947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.2520730947
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.3394251684
Short name T313
Test name
Test status
Simulation time 207734194809 ps
CPU time 463.17 seconds
Started Jun 11 03:44:59 PM PDT 24
Finished Jun 11 03:52:43 PM PDT 24
Peak memory 201880 kb
Host smart-80c8a76f-9203-4b79-9b7c-4b668c0ca4fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394251684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.3394251684
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.4054458876
Short name T344
Test name
Test status
Simulation time 85744127318 ps
CPU time 474.4 seconds
Started Jun 11 03:45:24 PM PDT 24
Finished Jun 11 03:53:20 PM PDT 24
Peak memory 202228 kb
Host smart-04a441db-9d10-40ce-8c29-ca8e40812cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054458876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.4054458876
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.3857449897
Short name T104
Test name
Test status
Simulation time 325306444545 ps
CPU time 143.11 seconds
Started Jun 11 03:45:40 PM PDT 24
Finished Jun 11 03:48:04 PM PDT 24
Peak memory 201820 kb
Host smart-046da094-f935-45cf-a292-b834aa886205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857449897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.3857449897
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.1518604389
Short name T270
Test name
Test status
Simulation time 324699053145 ps
CPU time 391.01 seconds
Started Jun 11 03:48:41 PM PDT 24
Finished Jun 11 03:55:14 PM PDT 24
Peak memory 201896 kb
Host smart-101847c7-190c-4448-8d1e-de7f78d8b7b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518604389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.1518604389
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.2908989438
Short name T299
Test name
Test status
Simulation time 413287403708 ps
CPU time 422.22 seconds
Started Jun 11 03:49:55 PM PDT 24
Finished Jun 11 03:56:58 PM PDT 24
Peak memory 201780 kb
Host smart-8e7c425f-d4f9-478d-b8ff-b206706957ea
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908989438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.2908989438
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.3047060364
Short name T262
Test name
Test status
Simulation time 17421417282 ps
CPU time 62.27 seconds
Started Jun 11 03:50:13 PM PDT 24
Finished Jun 11 03:51:16 PM PDT 24
Peak memory 202260 kb
Host smart-615cdaf1-14c3-4414-a7f2-bda52e653560
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047060364 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.3047060364
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.801624845
Short name T275
Test name
Test status
Simulation time 322870099780 ps
CPU time 195.19 seconds
Started Jun 11 03:50:53 PM PDT 24
Finished Jun 11 03:54:09 PM PDT 24
Peak memory 202056 kb
Host smart-9ea424c7-1cc5-42a1-ab1c-11598a35eec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801624845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.801624845
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.1730976812
Short name T306
Test name
Test status
Simulation time 487868249833 ps
CPU time 1246.22 seconds
Started Jun 11 03:44:11 PM PDT 24
Finished Jun 11 04:04:59 PM PDT 24
Peak memory 201968 kb
Host smart-ce101c28-9303-433e-b401-2e224572ca22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730976812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.1730976812
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.3790743498
Short name T244
Test name
Test status
Simulation time 191751458949 ps
CPU time 110.31 seconds
Started Jun 11 03:45:00 PM PDT 24
Finished Jun 11 03:46:51 PM PDT 24
Peak memory 201788 kb
Host smart-b5cb2029-5ddc-4945-898d-c69e3d8eed85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790743498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.3790743498
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.136690035
Short name T164
Test name
Test status
Simulation time 497718441312 ps
CPU time 286.54 seconds
Started Jun 11 03:45:07 PM PDT 24
Finished Jun 11 03:49:56 PM PDT 24
Peak memory 201824 kb
Host smart-78a24f4a-942d-4d74-b870-138ffe2378f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136690035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.136690035
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.1644146531
Short name T179
Test name
Test status
Simulation time 501094003327 ps
CPU time 296.22 seconds
Started Jun 11 03:47:44 PM PDT 24
Finished Jun 11 03:52:41 PM PDT 24
Peak memory 201812 kb
Host smart-63ff55a4-a5aa-4204-bdf2-2329228ad355
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644146531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.1644146531
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.2889917750
Short name T218
Test name
Test status
Simulation time 489931603838 ps
CPU time 348.92 seconds
Started Jun 11 03:48:48 PM PDT 24
Finished Jun 11 03:54:38 PM PDT 24
Peak memory 201788 kb
Host smart-6a57169f-61ef-436f-ad6b-2b980fafe596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889917750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.2889917750
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.3604251613
Short name T257
Test name
Test status
Simulation time 492307208818 ps
CPU time 286.18 seconds
Started Jun 11 03:44:45 PM PDT 24
Finished Jun 11 03:49:32 PM PDT 24
Peak memory 201816 kb
Host smart-d76d0112-e34e-41de-9b57-6350ec1436f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604251613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.3604251613
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2288744911
Short name T343
Test name
Test status
Simulation time 4304296036 ps
CPU time 4.13 seconds
Started Jun 11 03:42:18 PM PDT 24
Finished Jun 11 03:42:23 PM PDT 24
Peak memory 201980 kb
Host smart-3ca4d012-cb49-409d-9bb4-72d08eb4da9a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288744911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.2288744911
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.478888316
Short name T326
Test name
Test status
Simulation time 490302484531 ps
CPU time 1046.68 seconds
Started Jun 11 03:45:00 PM PDT 24
Finished Jun 11 04:02:28 PM PDT 24
Peak memory 201804 kb
Host smart-505fdf37-cc69-48e9-91fa-4d0fd237bc66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478888316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.478888316
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.3946957618
Short name T289
Test name
Test status
Simulation time 353733230321 ps
CPU time 798.11 seconds
Started Jun 11 03:45:15 PM PDT 24
Finished Jun 11 03:58:34 PM PDT 24
Peak memory 201832 kb
Host smart-6a2525b3-c0d1-4a0f-a076-734a3b5f9b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946957618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.3946957618
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.2329831064
Short name T193
Test name
Test status
Simulation time 90477061816 ps
CPU time 280.95 seconds
Started Jun 11 03:45:32 PM PDT 24
Finished Jun 11 03:50:14 PM PDT 24
Peak memory 202188 kb
Host smart-234f2582-33d1-4c78-9769-9ce0fbbf8b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329831064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.2329831064
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.2500543428
Short name T205
Test name
Test status
Simulation time 84947556384 ps
CPU time 279.89 seconds
Started Jun 11 03:46:17 PM PDT 24
Finished Jun 11 03:50:58 PM PDT 24
Peak memory 202148 kb
Host smart-bb8c8565-021c-4fea-bc82-ad4a92e1d574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500543428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.2500543428
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.3757315978
Short name T277
Test name
Test status
Simulation time 193032610554 ps
CPU time 39.59 seconds
Started Jun 11 03:46:23 PM PDT 24
Finished Jun 11 03:47:04 PM PDT 24
Peak memory 201812 kb
Host smart-ca1f37d2-6cc8-4b9f-b3e7-52b989df7e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757315978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.3757315978
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.3452751499
Short name T88
Test name
Test status
Simulation time 57745931265 ps
CPU time 117.92 seconds
Started Jun 11 03:46:39 PM PDT 24
Finished Jun 11 03:48:37 PM PDT 24
Peak memory 210216 kb
Host smart-c9584941-9d79-4796-aa0e-6ef698cc91da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452751499 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.3452751499
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.2687092073
Short name T128
Test name
Test status
Simulation time 50911579683 ps
CPU time 122 seconds
Started Jun 11 03:47:36 PM PDT 24
Finished Jun 11 03:49:39 PM PDT 24
Peak memory 210144 kb
Host smart-bf690323-7003-4cd6-90e9-989491c5999f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687092073 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.2687092073
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.3594826801
Short name T25
Test name
Test status
Simulation time 379882990655 ps
CPU time 730.08 seconds
Started Jun 11 03:47:45 PM PDT 24
Finished Jun 11 03:59:56 PM PDT 24
Peak memory 210724 kb
Host smart-26c1f471-4100-42ab-b1e3-ee54583e492e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594826801 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.3594826801
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.372951971
Short name T42
Test name
Test status
Simulation time 380141474998 ps
CPU time 482.15 seconds
Started Jun 11 03:49:20 PM PDT 24
Finished Jun 11 03:57:23 PM PDT 24
Peak memory 201812 kb
Host smart-7d53e87b-4dc2-4d10-a12f-3180c4c6f76b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372951971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_
wakeup.372951971
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.1420237166
Short name T251
Test name
Test status
Simulation time 331786687007 ps
CPU time 188.61 seconds
Started Jun 11 03:49:28 PM PDT 24
Finished Jun 11 03:52:38 PM PDT 24
Peak memory 201772 kb
Host smart-c3599c6d-67f8-4603-9450-385ec8b428f0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420237166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.1420237166
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.1339796899
Short name T197
Test name
Test status
Simulation time 113756566320 ps
CPU time 371.04 seconds
Started Jun 11 03:50:02 PM PDT 24
Finished Jun 11 03:56:14 PM PDT 24
Peak memory 202096 kb
Host smart-552a4743-9293-4f66-b772-18f3c2ac0c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339796899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.1339796899
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.3088865176
Short name T288
Test name
Test status
Simulation time 501959212142 ps
CPU time 109.65 seconds
Started Jun 11 03:50:01 PM PDT 24
Finished Jun 11 03:51:51 PM PDT 24
Peak memory 201824 kb
Host smart-5a980cd2-6ae8-4f3f-bcba-dfa8a5424736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088865176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.3088865176
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.241620415
Short name T267
Test name
Test status
Simulation time 275308918197 ps
CPU time 614.26 seconds
Started Jun 11 03:50:19 PM PDT 24
Finished Jun 11 04:00:34 PM PDT 24
Peak memory 210452 kb
Host smart-1a61e8b4-c2c2-46ab-baa5-d7a7f0927ff8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241620415 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.241620415
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.57064404
Short name T261
Test name
Test status
Simulation time 540032534817 ps
CPU time 1269.19 seconds
Started Jun 11 03:51:17 PM PDT 24
Finished Jun 11 04:12:27 PM PDT 24
Peak memory 201824 kb
Host smart-635b3e86-5239-487a-aa19-08e73db105c8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57064404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_w
akeup.57064404
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.651101925
Short name T320
Test name
Test status
Simulation time 329075523799 ps
CPU time 708.66 seconds
Started Jun 11 03:44:38 PM PDT 24
Finished Jun 11 03:56:28 PM PDT 24
Peak memory 201856 kb
Host smart-d1e06015-196a-40cc-a028-2060557910ec
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651101925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gatin
g.651101925
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3185679123
Short name T830
Test name
Test status
Simulation time 1134356282 ps
CPU time 1.61 seconds
Started Jun 11 03:42:19 PM PDT 24
Finished Jun 11 03:42:22 PM PDT 24
Peak memory 201920 kb
Host smart-844d0382-b1ea-4f74-9ab2-9c87fb058040
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185679123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.3185679123
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1113622512
Short name T858
Test name
Test status
Simulation time 52545146537 ps
CPU time 67.09 seconds
Started Jun 11 03:42:19 PM PDT 24
Finished Jun 11 03:43:27 PM PDT 24
Peak memory 201996 kb
Host smart-3b7359e0-1055-4e04-9a22-c1ba3f858d39
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113622512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.1113622512
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2701482528
Short name T116
Test name
Test status
Simulation time 1268904931 ps
CPU time 2.34 seconds
Started Jun 11 03:42:18 PM PDT 24
Finished Jun 11 03:42:21 PM PDT 24
Peak memory 201640 kb
Host smart-5763aeb3-7681-4e7e-9394-c6ae9d2af119
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701482528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.2701482528
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.98238422
Short name T847
Test name
Test status
Simulation time 457528255 ps
CPU time 1.07 seconds
Started Jun 11 03:42:19 PM PDT 24
Finished Jun 11 03:42:21 PM PDT 24
Peak memory 201780 kb
Host smart-4d9c54ca-75b6-49c8-b160-5b8e8bad35cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98238422 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.98238422
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1429837220
Short name T107
Test name
Test status
Simulation time 471340343 ps
CPU time 0.98 seconds
Started Jun 11 03:42:18 PM PDT 24
Finished Jun 11 03:42:20 PM PDT 24
Peak memory 201684 kb
Host smart-7e152443-a115-4006-bf31-f79bbdf2ef15
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429837220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.1429837220
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.3290168278
Short name T891
Test name
Test status
Simulation time 605233311 ps
CPU time 0.74 seconds
Started Jun 11 03:42:19 PM PDT 24
Finished Jun 11 03:42:21 PM PDT 24
Peak memory 201712 kb
Host smart-26e04143-73df-4e20-9227-93707c1e4e9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290168278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.3290168278
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.1756706368
Short name T860
Test name
Test status
Simulation time 2581758143 ps
CPU time 3.2 seconds
Started Jun 11 03:42:18 PM PDT 24
Finished Jun 11 03:42:22 PM PDT 24
Peak memory 201788 kb
Host smart-4ee6870a-4fea-4e4d-9256-46f146cf16fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756706368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.1756706368
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1112689932
Short name T809
Test name
Test status
Simulation time 455561285 ps
CPU time 2.39 seconds
Started Jun 11 03:42:18 PM PDT 24
Finished Jun 11 03:42:22 PM PDT 24
Peak memory 217776 kb
Host smart-8aa41488-dd3d-4348-8023-c0dc126a8ec8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112689932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.1112689932
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3520982626
Short name T872
Test name
Test status
Simulation time 4605275990 ps
CPU time 7.16 seconds
Started Jun 11 03:42:18 PM PDT 24
Finished Jun 11 03:42:26 PM PDT 24
Peak memory 201976 kb
Host smart-ec252d67-807a-43a7-9627-ad2341b15fd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520982626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.3520982626
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3334884092
Short name T106
Test name
Test status
Simulation time 893654881 ps
CPU time 1.99 seconds
Started Jun 11 03:42:26 PM PDT 24
Finished Jun 11 03:42:29 PM PDT 24
Peak memory 201952 kb
Host smart-f7e7e943-8e6f-4bd0-b243-784489f6dea4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334884092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.3334884092
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2044724918
Short name T119
Test name
Test status
Simulation time 28081149939 ps
CPU time 28.35 seconds
Started Jun 11 03:42:30 PM PDT 24
Finished Jun 11 03:43:00 PM PDT 24
Peak memory 202032 kb
Host smart-29e4cb1a-a216-48f2-b6ab-28e3e524707b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044724918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.2044724918
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.1425516232
Short name T855
Test name
Test status
Simulation time 699430313 ps
CPU time 2.39 seconds
Started Jun 11 03:42:18 PM PDT 24
Finished Jun 11 03:42:21 PM PDT 24
Peak memory 201684 kb
Host smart-eeb3a3bb-e1ce-46e3-8d6e-46c0223a33a9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425516232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.1425516232
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2363962680
Short name T857
Test name
Test status
Simulation time 591102990 ps
CPU time 1.34 seconds
Started Jun 11 03:42:25 PM PDT 24
Finished Jun 11 03:42:28 PM PDT 24
Peak memory 201792 kb
Host smart-4ab74af8-78eb-4746-9695-a60a76a7d553
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363962680 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.2363962680
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1398812395
Short name T870
Test name
Test status
Simulation time 550152936 ps
CPU time 1 seconds
Started Jun 11 03:42:17 PM PDT 24
Finished Jun 11 03:42:19 PM PDT 24
Peak memory 201632 kb
Host smart-e3aeb6ad-4810-4789-aa74-3c41ae467806
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398812395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.1398812395
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1619953920
Short name T902
Test name
Test status
Simulation time 407060955 ps
CPU time 0.91 seconds
Started Jun 11 03:42:19 PM PDT 24
Finished Jun 11 03:42:21 PM PDT 24
Peak memory 201716 kb
Host smart-03039de8-db88-465d-9b5f-93d1dbf75432
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619953920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.1619953920
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.4276365294
Short name T818
Test name
Test status
Simulation time 1395078751 ps
CPU time 2.28 seconds
Started Jun 11 03:42:18 PM PDT 24
Finished Jun 11 03:42:22 PM PDT 24
Peak memory 218504 kb
Host smart-f6d6fbff-79fc-4dd4-9089-dc9ad38928ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276365294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.4276365294
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2145579460
Short name T874
Test name
Test status
Simulation time 523112360 ps
CPU time 2.04 seconds
Started Jun 11 03:42:51 PM PDT 24
Finished Jun 11 03:42:53 PM PDT 24
Peak memory 201804 kb
Host smart-53e17cce-5e98-4b45-bdd3-51c396459ccf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145579460 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.2145579460
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3433469102
Short name T113
Test name
Test status
Simulation time 309769497 ps
CPU time 1.43 seconds
Started Jun 11 03:42:50 PM PDT 24
Finished Jun 11 03:42:52 PM PDT 24
Peak memory 201724 kb
Host smart-88cc6768-e43b-47a2-9841-c46e389f69b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433469102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.3433469102
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.3521674025
Short name T843
Test name
Test status
Simulation time 696603293 ps
CPU time 0.76 seconds
Started Jun 11 03:42:49 PM PDT 24
Finished Jun 11 03:42:51 PM PDT 24
Peak memory 201716 kb
Host smart-4abb2bc6-4bbb-40f3-b459-6ca5aa010bb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521674025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.3521674025
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.227789389
Short name T873
Test name
Test status
Simulation time 2448216707 ps
CPU time 6.05 seconds
Started Jun 11 03:42:49 PM PDT 24
Finished Jun 11 03:42:56 PM PDT 24
Peak memory 201832 kb
Host smart-190f3465-7536-4e67-8ac8-d47b8f015c22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227789389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_c
trl_same_csr_outstanding.227789389
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.678263839
Short name T856
Test name
Test status
Simulation time 475188618 ps
CPU time 2.18 seconds
Started Jun 11 03:42:49 PM PDT 24
Finished Jun 11 03:42:52 PM PDT 24
Peak memory 218120 kb
Host smart-a37826cd-6866-4d88-8b3a-6270ce48b5fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678263839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.678263839
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.109861366
Short name T840
Test name
Test status
Simulation time 447867811 ps
CPU time 1.82 seconds
Started Jun 11 03:42:57 PM PDT 24
Finished Jun 11 03:43:00 PM PDT 24
Peak memory 201804 kb
Host smart-a24fbc5d-cb7a-48c9-b80b-1d2e5d2e6885
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109861366 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.109861366
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2329634765
Short name T114
Test name
Test status
Simulation time 337662881 ps
CPU time 1.59 seconds
Started Jun 11 03:42:50 PM PDT 24
Finished Jun 11 03:42:52 PM PDT 24
Peak memory 201908 kb
Host smart-f84e0ba8-83c5-4ed0-9451-30caea1fc44c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329634765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.2329634765
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.4240445065
Short name T914
Test name
Test status
Simulation time 328579131 ps
CPU time 1.31 seconds
Started Jun 11 03:42:51 PM PDT 24
Finished Jun 11 03:42:53 PM PDT 24
Peak memory 201624 kb
Host smart-2dd80193-b441-4872-9cd9-693b4957bdb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240445065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.4240445065
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2428514937
Short name T875
Test name
Test status
Simulation time 2128934516 ps
CPU time 2.88 seconds
Started Jun 11 03:42:49 PM PDT 24
Finished Jun 11 03:42:52 PM PDT 24
Peak memory 201728 kb
Host smart-2427cbad-50ea-4d5e-abe8-2a8415abdecd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428514937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.2428514937
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3184263156
Short name T63
Test name
Test status
Simulation time 4204996220 ps
CPU time 11.69 seconds
Started Jun 11 03:42:49 PM PDT 24
Finished Jun 11 03:43:02 PM PDT 24
Peak memory 201972 kb
Host smart-3ce15fe9-746c-466c-b5fe-f94496ec4920
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184263156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.3184263156
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.4140678543
Short name T829
Test name
Test status
Simulation time 522482217 ps
CPU time 2.29 seconds
Started Jun 11 03:42:58 PM PDT 24
Finished Jun 11 03:43:02 PM PDT 24
Peak memory 201840 kb
Host smart-da0185a7-c515-49a4-999b-0e48c672071e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140678543 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.4140678543
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.4246309714
Short name T911
Test name
Test status
Simulation time 362954049 ps
CPU time 1.12 seconds
Started Jun 11 03:42:56 PM PDT 24
Finished Jun 11 03:42:58 PM PDT 24
Peak memory 201680 kb
Host smart-d1fcb8eb-835f-41de-9e14-1afd1a099add
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246309714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.4246309714
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3901150941
Short name T802
Test name
Test status
Simulation time 363844557 ps
CPU time 1.43 seconds
Started Jun 11 03:42:57 PM PDT 24
Finished Jun 11 03:42:59 PM PDT 24
Peak memory 201712 kb
Host smart-c497a890-886a-4763-9cb0-d6bdd80efe10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901150941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.3901150941
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.861107548
Short name T918
Test name
Test status
Simulation time 4338789485 ps
CPU time 6.4 seconds
Started Jun 11 03:42:59 PM PDT 24
Finished Jun 11 03:43:07 PM PDT 24
Peak memory 202020 kb
Host smart-ff97f618-353f-4a1a-9669-4fdc95af18c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861107548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_c
trl_same_csr_outstanding.861107548
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1004071310
Short name T892
Test name
Test status
Simulation time 796683665 ps
CPU time 1.41 seconds
Started Jun 11 03:43:01 PM PDT 24
Finished Jun 11 03:43:04 PM PDT 24
Peak memory 201916 kb
Host smart-69764691-7351-4c58-ad06-ba4969a976ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004071310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.1004071310
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.4127521054
Short name T882
Test name
Test status
Simulation time 4218159980 ps
CPU time 4.62 seconds
Started Jun 11 03:43:00 PM PDT 24
Finished Jun 11 03:43:06 PM PDT 24
Peak memory 201968 kb
Host smart-94e99a56-5e3b-4725-816c-cb8d664b3649
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127521054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.4127521054
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.913183103
Short name T895
Test name
Test status
Simulation time 664281166 ps
CPU time 1.65 seconds
Started Jun 11 03:42:56 PM PDT 24
Finished Jun 11 03:42:58 PM PDT 24
Peak memory 201792 kb
Host smart-73fc0ad2-ee0f-4c74-aa3a-f9e4541cb2a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913183103 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.913183103
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.874843975
Short name T60
Test name
Test status
Simulation time 549019152 ps
CPU time 1.08 seconds
Started Jun 11 03:43:01 PM PDT 24
Finished Jun 11 03:43:04 PM PDT 24
Peak memory 201620 kb
Host smart-8bf316e4-f3af-475a-9959-acbed1e586b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874843975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.874843975
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.440915416
Short name T804
Test name
Test status
Simulation time 278135133 ps
CPU time 1.28 seconds
Started Jun 11 03:43:00 PM PDT 24
Finished Jun 11 03:43:02 PM PDT 24
Peak memory 201712 kb
Host smart-2039e566-d383-4c5f-8d49-d3f75a19f46c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440915416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.440915416
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3885944017
Short name T124
Test name
Test status
Simulation time 2428325519 ps
CPU time 3.93 seconds
Started Jun 11 03:42:58 PM PDT 24
Finished Jun 11 03:43:04 PM PDT 24
Peak memory 201824 kb
Host smart-e8728958-6bd3-4f84-9b77-2c957cdd928f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885944017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.3885944017
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2538156920
Short name T846
Test name
Test status
Simulation time 499013267 ps
CPU time 2.26 seconds
Started Jun 11 03:42:58 PM PDT 24
Finished Jun 11 03:43:02 PM PDT 24
Peak memory 202004 kb
Host smart-67b34547-b1be-4c4c-94c9-f0786d856484
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538156920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.2538156920
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2939471283
Short name T823
Test name
Test status
Simulation time 4585144437 ps
CPU time 8.04 seconds
Started Jun 11 03:42:58 PM PDT 24
Finished Jun 11 03:43:08 PM PDT 24
Peak memory 201912 kb
Host smart-ce77d25d-02ad-4142-b2b7-50452802c212
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939471283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.2939471283
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1214042479
Short name T821
Test name
Test status
Simulation time 485844238 ps
CPU time 1.51 seconds
Started Jun 11 03:43:02 PM PDT 24
Finished Jun 11 03:43:05 PM PDT 24
Peak memory 201696 kb
Host smart-7cde663e-edde-4186-b395-7cfc34a72bbc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214042479 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.1214042479
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.4271115213
Short name T908
Test name
Test status
Simulation time 499738278 ps
CPU time 1.06 seconds
Started Jun 11 03:42:56 PM PDT 24
Finished Jun 11 03:42:58 PM PDT 24
Peak memory 201728 kb
Host smart-502ba6db-e913-470a-9302-fa8c6354b72e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271115213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.4271115213
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.909178331
Short name T867
Test name
Test status
Simulation time 439037849 ps
CPU time 0.72 seconds
Started Jun 11 03:42:57 PM PDT 24
Finished Jun 11 03:42:59 PM PDT 24
Peak memory 201712 kb
Host smart-ccb4b344-e1fb-4d58-ae11-01145565526a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909178331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.909178331
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.329294432
Short name T123
Test name
Test status
Simulation time 3841910344 ps
CPU time 4.26 seconds
Started Jun 11 03:42:56 PM PDT 24
Finished Jun 11 03:43:01 PM PDT 24
Peak memory 201964 kb
Host smart-8467723b-5e15-45b0-88d5-ade025d2acad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329294432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_c
trl_same_csr_outstanding.329294432
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3791606137
Short name T71
Test name
Test status
Simulation time 534801161 ps
CPU time 2.71 seconds
Started Jun 11 03:42:58 PM PDT 24
Finished Jun 11 03:43:03 PM PDT 24
Peak memory 201920 kb
Host smart-b576a53d-df20-4093-9c32-b2fdc1437472
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791606137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.3791606137
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.4186144592
Short name T62
Test name
Test status
Simulation time 4565097554 ps
CPU time 6.55 seconds
Started Jun 11 03:43:02 PM PDT 24
Finished Jun 11 03:43:10 PM PDT 24
Peak memory 201848 kb
Host smart-88355524-eb62-482a-9655-a6cf0adc3730
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186144592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.4186144592
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2705833794
Short name T822
Test name
Test status
Simulation time 619487681 ps
CPU time 2.44 seconds
Started Jun 11 03:43:05 PM PDT 24
Finished Jun 11 03:43:09 PM PDT 24
Peak memory 201800 kb
Host smart-aeb25db4-d1af-481c-887c-dbcf2cc7b236
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705833794 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.2705833794
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.208916413
Short name T121
Test name
Test status
Simulation time 444313496 ps
CPU time 0.96 seconds
Started Jun 11 03:43:06 PM PDT 24
Finished Jun 11 03:43:09 PM PDT 24
Peak memory 201680 kb
Host smart-c6a65174-cc7a-4447-bb59-0286cd7b820a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208916413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.208916413
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.4292642632
Short name T863
Test name
Test status
Simulation time 362165746 ps
CPU time 1.51 seconds
Started Jun 11 03:43:00 PM PDT 24
Finished Jun 11 03:43:02 PM PDT 24
Peak memory 201716 kb
Host smart-7a04b7ea-a644-47b3-80ea-7c07a7b6533a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292642632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.4292642632
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2744269320
Short name T876
Test name
Test status
Simulation time 5305229219 ps
CPU time 6.85 seconds
Started Jun 11 03:43:05 PM PDT 24
Finished Jun 11 03:43:13 PM PDT 24
Peak memory 202072 kb
Host smart-62ea780b-b866-416b-abcc-cb7bb6e31288
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744269320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.2744269320
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1289649803
Short name T916
Test name
Test status
Simulation time 8370761380 ps
CPU time 20.19 seconds
Started Jun 11 03:43:00 PM PDT 24
Finished Jun 11 03:43:22 PM PDT 24
Peak memory 201868 kb
Host smart-9eb2dc16-5323-4ee2-9f1c-d3f2ba9a4af7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289649803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.1289649803
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.447163984
Short name T81
Test name
Test status
Simulation time 397567615 ps
CPU time 1.07 seconds
Started Jun 11 03:43:05 PM PDT 24
Finished Jun 11 03:43:07 PM PDT 24
Peak memory 201804 kb
Host smart-b649a34a-4454-466a-bb71-594565c67236
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447163984 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.447163984
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.753681511
Short name T839
Test name
Test status
Simulation time 381491775 ps
CPU time 1.8 seconds
Started Jun 11 03:43:08 PM PDT 24
Finished Jun 11 03:43:11 PM PDT 24
Peak memory 201716 kb
Host smart-3c534ff2-e551-4579-ab55-7202a1ca9b1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753681511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.753681511
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.2970715518
Short name T828
Test name
Test status
Simulation time 515988252 ps
CPU time 1.24 seconds
Started Jun 11 03:43:08 PM PDT 24
Finished Jun 11 03:43:11 PM PDT 24
Peak memory 201716 kb
Host smart-1a898c65-aadb-4cf7-9c3b-dea278bc50e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970715518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.2970715518
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2176718244
Short name T825
Test name
Test status
Simulation time 3804139990 ps
CPU time 7.78 seconds
Started Jun 11 03:43:06 PM PDT 24
Finished Jun 11 03:43:15 PM PDT 24
Peak memory 201980 kb
Host smart-da85e0cd-7d55-4185-921e-8e28b36a8f75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176718244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.2176718244
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3801348107
Short name T68
Test name
Test status
Simulation time 455290622 ps
CPU time 1.51 seconds
Started Jun 11 03:43:06 PM PDT 24
Finished Jun 11 03:43:10 PM PDT 24
Peak memory 201956 kb
Host smart-a4ca1b88-90ac-42d3-9731-04879778bab7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801348107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.3801348107
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.3105019937
Short name T849
Test name
Test status
Simulation time 8180588069 ps
CPU time 8.43 seconds
Started Jun 11 03:43:06 PM PDT 24
Finished Jun 11 03:43:16 PM PDT 24
Peak memory 201916 kb
Host smart-5fb43a26-2dfe-4d70-bd79-96fae668e3ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105019937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.3105019937
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.352357170
Short name T899
Test name
Test status
Simulation time 463267200 ps
CPU time 1.84 seconds
Started Jun 11 03:43:05 PM PDT 24
Finished Jun 11 03:43:08 PM PDT 24
Peak memory 201788 kb
Host smart-a7ff9084-ca12-4b78-a7e4-44aab20261e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352357170 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.352357170
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.645209422
Short name T909
Test name
Test status
Simulation time 386611381 ps
CPU time 1.17 seconds
Started Jun 11 03:43:08 PM PDT 24
Finished Jun 11 03:43:11 PM PDT 24
Peak memory 201700 kb
Host smart-e7d30da1-76cc-4ec1-a8f5-6c9477f1e790
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645209422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.645209422
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.4016727954
Short name T816
Test name
Test status
Simulation time 419447171 ps
CPU time 1.15 seconds
Started Jun 11 03:43:05 PM PDT 24
Finished Jun 11 03:43:07 PM PDT 24
Peak memory 201704 kb
Host smart-a6044ed1-54ac-4fb8-a8af-4d281dd3b979
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016727954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.4016727954
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3602200824
Short name T122
Test name
Test status
Simulation time 2843178055 ps
CPU time 1.39 seconds
Started Jun 11 03:43:04 PM PDT 24
Finished Jun 11 03:43:06 PM PDT 24
Peak memory 201832 kb
Host smart-143293b0-5bff-406a-85a8-22eae143d41a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602200824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.3602200824
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1493877716
Short name T844
Test name
Test status
Simulation time 578417265 ps
CPU time 2.76 seconds
Started Jun 11 03:43:06 PM PDT 24
Finished Jun 11 03:43:10 PM PDT 24
Peak memory 201944 kb
Host smart-21e2392d-cced-4d1c-9003-045be6b77b77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493877716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.1493877716
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.981271303
Short name T889
Test name
Test status
Simulation time 8236404323 ps
CPU time 11.81 seconds
Started Jun 11 03:43:04 PM PDT 24
Finished Jun 11 03:43:17 PM PDT 24
Peak memory 201964 kb
Host smart-3f5c259b-0906-4f12-8226-7af13fdb489b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981271303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_in
tg_err.981271303
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1744569384
Short name T907
Test name
Test status
Simulation time 499421069 ps
CPU time 1.17 seconds
Started Jun 11 03:43:06 PM PDT 24
Finished Jun 11 03:43:09 PM PDT 24
Peak memory 201800 kb
Host smart-4c41d1d2-af22-4547-852b-9fc11b1bbd49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744569384 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.1744569384
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3791974427
Short name T834
Test name
Test status
Simulation time 411436927 ps
CPU time 1.12 seconds
Started Jun 11 03:43:06 PM PDT 24
Finished Jun 11 03:43:09 PM PDT 24
Peak memory 201704 kb
Host smart-3de30dd3-2d4a-48ed-953c-c5c8aa7559a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791974427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.3791974427
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.180753524
Short name T859
Test name
Test status
Simulation time 399748417 ps
CPU time 1.58 seconds
Started Jun 11 03:43:04 PM PDT 24
Finished Jun 11 03:43:07 PM PDT 24
Peak memory 201724 kb
Host smart-ffa31c51-c6e0-4842-a008-9ec60f48030b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180753524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.180753524
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.4019842028
Short name T59
Test name
Test status
Simulation time 4849533874 ps
CPU time 12.43 seconds
Started Jun 11 03:43:06 PM PDT 24
Finished Jun 11 03:43:20 PM PDT 24
Peak memory 202020 kb
Host smart-4cc536a9-662d-48de-8d2e-0cfed8a66047
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019842028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.4019842028
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.2530747936
Short name T877
Test name
Test status
Simulation time 474610834 ps
CPU time 3.06 seconds
Started Jun 11 03:43:06 PM PDT 24
Finished Jun 11 03:43:11 PM PDT 24
Peak memory 210160 kb
Host smart-b07e2225-2c1e-4f64-a69a-188aead306e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530747936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.2530747936
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1733372713
Short name T78
Test name
Test status
Simulation time 8096951866 ps
CPU time 6.25 seconds
Started Jun 11 03:43:05 PM PDT 24
Finished Jun 11 03:43:13 PM PDT 24
Peak memory 201952 kb
Host smart-2e09535b-e3db-4945-97c5-fd135833ba2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733372713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.1733372713
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1564160859
Short name T866
Test name
Test status
Simulation time 337832725 ps
CPU time 1.53 seconds
Started Jun 11 03:43:05 PM PDT 24
Finished Jun 11 03:43:08 PM PDT 24
Peak memory 201832 kb
Host smart-02034e2c-db62-4ed6-9e48-d362fa5e5d4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564160859 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.1564160859
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.768878088
Short name T109
Test name
Test status
Simulation time 426860597 ps
CPU time 1.21 seconds
Started Jun 11 03:43:06 PM PDT 24
Finished Jun 11 03:43:09 PM PDT 24
Peak memory 201760 kb
Host smart-25007ab0-276a-477e-a7a0-9631688529c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768878088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.768878088
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.3408396708
Short name T810
Test name
Test status
Simulation time 346924691 ps
CPU time 1.41 seconds
Started Jun 11 03:43:07 PM PDT 24
Finished Jun 11 03:43:10 PM PDT 24
Peak memory 201692 kb
Host smart-51a33285-7e3b-4372-be33-20ec6fb11135
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408396708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.3408396708
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1531821393
Short name T56
Test name
Test status
Simulation time 4355780853 ps
CPU time 3.37 seconds
Started Jun 11 03:43:07 PM PDT 24
Finished Jun 11 03:43:12 PM PDT 24
Peak memory 201936 kb
Host smart-08295592-b4e6-4f49-91a4-d195dd770f31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531821393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.1531821393
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3515276698
Short name T915
Test name
Test status
Simulation time 577000201 ps
CPU time 1.85 seconds
Started Jun 11 03:43:06 PM PDT 24
Finished Jun 11 03:43:09 PM PDT 24
Peak memory 217864 kb
Host smart-d39a0f55-3861-4bf0-95a1-5beb7f90f6ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515276698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.3515276698
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2512699169
Short name T896
Test name
Test status
Simulation time 8626833577 ps
CPU time 7.88 seconds
Started Jun 11 03:43:05 PM PDT 24
Finished Jun 11 03:43:14 PM PDT 24
Peak memory 202156 kb
Host smart-a3ca7255-e5db-4846-8898-dec62e55476a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512699169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.2512699169
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2323831052
Short name T881
Test name
Test status
Simulation time 1306207459 ps
CPU time 2.99 seconds
Started Jun 11 03:42:26 PM PDT 24
Finished Jun 11 03:42:30 PM PDT 24
Peak memory 201944 kb
Host smart-420a5f06-2a26-4f02-a302-d8794deb20b1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323831052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.2323831052
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.89428667
Short name T57
Test name
Test status
Simulation time 53193618715 ps
CPU time 105.69 seconds
Started Jun 11 03:42:26 PM PDT 24
Finished Jun 11 03:44:13 PM PDT 24
Peak memory 201964 kb
Host smart-00f664dc-6711-4061-8a3f-4f861adf7628
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89428667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_ba
sh.89428667
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.859204592
Short name T820
Test name
Test status
Simulation time 1302909968 ps
CPU time 3.71 seconds
Started Jun 11 03:42:26 PM PDT 24
Finished Jun 11 03:42:31 PM PDT 24
Peak memory 201756 kb
Host smart-99277e26-25e3-428a-bc23-7b5dcb7f7f4e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859204592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_re
set.859204592
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3690724440
Short name T919
Test name
Test status
Simulation time 550906562 ps
CPU time 1.22 seconds
Started Jun 11 03:42:26 PM PDT 24
Finished Jun 11 03:42:28 PM PDT 24
Peak memory 201764 kb
Host smart-a86448fb-1e8b-4e87-b950-9df74310458a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690724440 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.3690724440
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1591395659
Short name T110
Test name
Test status
Simulation time 325666821 ps
CPU time 1.45 seconds
Started Jun 11 03:42:25 PM PDT 24
Finished Jun 11 03:42:28 PM PDT 24
Peak memory 201760 kb
Host smart-830696af-54b4-4493-9fcf-c2035a703adb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591395659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.1591395659
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.1647420120
Short name T887
Test name
Test status
Simulation time 649683997 ps
CPU time 0.73 seconds
Started Jun 11 03:42:25 PM PDT 24
Finished Jun 11 03:42:27 PM PDT 24
Peak memory 201724 kb
Host smart-a2b48d59-a5d7-44e9-8a59-61f5a3ee6814
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647420120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.1647420120
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1342294947
Short name T880
Test name
Test status
Simulation time 2012432668 ps
CPU time 9.81 seconds
Started Jun 11 03:42:24 PM PDT 24
Finished Jun 11 03:42:35 PM PDT 24
Peak memory 201900 kb
Host smart-df9ba5e7-1c84-4baf-9e01-5fe8f5314015
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342294947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.1342294947
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.4191127189
Short name T917
Test name
Test status
Simulation time 557468375 ps
CPU time 1.78 seconds
Started Jun 11 03:42:26 PM PDT 24
Finished Jun 11 03:42:29 PM PDT 24
Peak memory 202060 kb
Host smart-84c31ec4-5768-4f88-b095-7d8aa004d15e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191127189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.4191127189
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.3322423319
Short name T832
Test name
Test status
Simulation time 8065567855 ps
CPU time 19.98 seconds
Started Jun 11 03:42:31 PM PDT 24
Finished Jun 11 03:42:52 PM PDT 24
Peak memory 202028 kb
Host smart-e47c8e57-2a73-4da8-9b3b-50726a3ee861
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322423319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.3322423319
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.157614342
Short name T912
Test name
Test status
Simulation time 509427540 ps
CPU time 1.13 seconds
Started Jun 11 03:43:07 PM PDT 24
Finished Jun 11 03:43:10 PM PDT 24
Peak memory 201668 kb
Host smart-4e2302e3-e3c4-4999-9913-e95ba51a7027
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157614342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.157614342
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1400227260
Short name T905
Test name
Test status
Simulation time 516954003 ps
CPU time 0.96 seconds
Started Jun 11 03:43:05 PM PDT 24
Finished Jun 11 03:43:07 PM PDT 24
Peak memory 201716 kb
Host smart-a0ab7e6c-159b-40d6-a7ed-04f517acc77e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400227260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.1400227260
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.4107739033
Short name T800
Test name
Test status
Simulation time 456712790 ps
CPU time 0.92 seconds
Started Jun 11 03:43:06 PM PDT 24
Finished Jun 11 03:43:09 PM PDT 24
Peak memory 201728 kb
Host smart-d484496a-b15c-4cd8-9c09-d8b99783bc2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107739033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.4107739033
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.1370303137
Short name T885
Test name
Test status
Simulation time 487763198 ps
CPU time 1.27 seconds
Started Jun 11 03:43:07 PM PDT 24
Finished Jun 11 03:43:10 PM PDT 24
Peak memory 201660 kb
Host smart-191ebaf8-29e7-4f79-8027-5029cd5aa3f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370303137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.1370303137
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.89311265
Short name T842
Test name
Test status
Simulation time 335468392 ps
CPU time 0.81 seconds
Started Jun 11 03:43:05 PM PDT 24
Finished Jun 11 03:43:07 PM PDT 24
Peak memory 201720 kb
Host smart-b18e0a3e-bf30-4320-93fa-e162b855373e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89311265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.89311265
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1797736193
Short name T808
Test name
Test status
Simulation time 694273993 ps
CPU time 0.73 seconds
Started Jun 11 03:43:07 PM PDT 24
Finished Jun 11 03:43:09 PM PDT 24
Peak memory 201764 kb
Host smart-d3a31f3c-b650-47cf-86f1-bcdaa049022f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797736193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.1797736193
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.3007575139
Short name T864
Test name
Test status
Simulation time 315047919 ps
CPU time 1.44 seconds
Started Jun 11 03:43:06 PM PDT 24
Finished Jun 11 03:43:08 PM PDT 24
Peak memory 201632 kb
Host smart-98a8e38c-733f-405c-b9b0-2c821b2dada7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007575139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.3007575139
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.1585627444
Short name T897
Test name
Test status
Simulation time 372681291 ps
CPU time 1.54 seconds
Started Jun 11 03:43:14 PM PDT 24
Finished Jun 11 03:43:18 PM PDT 24
Peak memory 201708 kb
Host smart-e4554d2f-d998-4271-8c1e-ed06610e091c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585627444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.1585627444
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3832287663
Short name T813
Test name
Test status
Simulation time 421415060 ps
CPU time 1.59 seconds
Started Jun 11 03:43:14 PM PDT 24
Finished Jun 11 03:43:17 PM PDT 24
Peak memory 201756 kb
Host smart-26a79658-b277-4347-8ff0-f5b622e2ca95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832287663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.3832287663
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.334556440
Short name T865
Test name
Test status
Simulation time 316587376 ps
CPU time 1.41 seconds
Started Jun 11 03:43:15 PM PDT 24
Finished Jun 11 03:43:20 PM PDT 24
Peak memory 201716 kb
Host smart-ab8d9955-ae59-479b-b7af-b8d9d0146f37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334556440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.334556440
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3427488385
Short name T112
Test name
Test status
Simulation time 1097942670 ps
CPU time 2.94 seconds
Started Jun 11 03:42:30 PM PDT 24
Finished Jun 11 03:42:34 PM PDT 24
Peak memory 201964 kb
Host smart-02e050c6-2a67-4736-806a-1785cc31b26c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427488385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.3427488385
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3631631196
Short name T862
Test name
Test status
Simulation time 1176442801 ps
CPU time 3.57 seconds
Started Jun 11 03:42:27 PM PDT 24
Finished Jun 11 03:42:32 PM PDT 24
Peak memory 201724 kb
Host smart-e5eb86ac-84a5-4de1-9fb6-c4087ab7909b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631631196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.3631631196
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2782777574
Short name T75
Test name
Test status
Simulation time 602363572 ps
CPU time 2.39 seconds
Started Jun 11 03:42:35 PM PDT 24
Finished Jun 11 03:42:38 PM PDT 24
Peak memory 201824 kb
Host smart-a93c8308-8e8c-4ce7-a056-127d16820cec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782777574 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.2782777574
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.2696615981
Short name T886
Test name
Test status
Simulation time 357465990 ps
CPU time 0.95 seconds
Started Jun 11 03:42:27 PM PDT 24
Finished Jun 11 03:42:29 PM PDT 24
Peak memory 201752 kb
Host smart-9ba38d8e-bd0e-49aa-8656-7a2b6ff05d6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696615981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.2696615981
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.872866992
Short name T879
Test name
Test status
Simulation time 340412632 ps
CPU time 1.38 seconds
Started Jun 11 03:42:24 PM PDT 24
Finished Jun 11 03:42:26 PM PDT 24
Peak memory 201708 kb
Host smart-ece01f1a-e6e6-41d1-93c5-e98b4899f777
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872866992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.872866992
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3133844819
Short name T845
Test name
Test status
Simulation time 4130876702 ps
CPU time 15.02 seconds
Started Jun 11 03:42:33 PM PDT 24
Finished Jun 11 03:42:49 PM PDT 24
Peak memory 202012 kb
Host smart-78397725-37a9-420a-ba2e-b189dc0bc9f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133844819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.3133844819
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3136161960
Short name T74
Test name
Test status
Simulation time 535375264 ps
CPU time 1.66 seconds
Started Jun 11 03:42:25 PM PDT 24
Finished Jun 11 03:42:28 PM PDT 24
Peak memory 202048 kb
Host smart-073e68a3-8178-4f5c-aa86-5ff53848ea81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136161960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.3136161960
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1765062582
Short name T341
Test name
Test status
Simulation time 4877870415 ps
CPU time 3.06 seconds
Started Jun 11 03:42:25 PM PDT 24
Finished Jun 11 03:42:30 PM PDT 24
Peak memory 202040 kb
Host smart-9c454b7d-a6e4-4154-bfd1-a88977766991
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765062582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.1765062582
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.329338881
Short name T812
Test name
Test status
Simulation time 476779060 ps
CPU time 1.58 seconds
Started Jun 11 03:43:12 PM PDT 24
Finished Jun 11 03:43:15 PM PDT 24
Peak memory 201724 kb
Host smart-57f1c579-5eb9-44c3-aad7-b0118de528aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329338881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.329338881
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1768013841
Short name T878
Test name
Test status
Simulation time 277659204 ps
CPU time 1.3 seconds
Started Jun 11 03:43:14 PM PDT 24
Finished Jun 11 03:43:17 PM PDT 24
Peak memory 201732 kb
Host smart-51ddf3fb-250c-4c60-afd3-f07dcb90368b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768013841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.1768013841
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.3582688048
Short name T852
Test name
Test status
Simulation time 593553817 ps
CPU time 0.72 seconds
Started Jun 11 03:43:15 PM PDT 24
Finished Jun 11 03:43:18 PM PDT 24
Peak memory 201740 kb
Host smart-0204058e-2347-4ea4-8162-281302b88758
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582688048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.3582688048
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.3795406035
Short name T869
Test name
Test status
Simulation time 465555513 ps
CPU time 0.88 seconds
Started Jun 11 03:43:14 PM PDT 24
Finished Jun 11 03:43:17 PM PDT 24
Peak memory 201660 kb
Host smart-ce6339fa-64d9-4219-a846-e93d68cd3dca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795406035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.3795406035
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.3862579271
Short name T884
Test name
Test status
Simulation time 346861573 ps
CPU time 0.88 seconds
Started Jun 11 03:43:14 PM PDT 24
Finished Jun 11 03:43:18 PM PDT 24
Peak memory 201700 kb
Host smart-6ef480ed-f1e9-4e93-b1ce-d88e0d9fed5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862579271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.3862579271
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.101903127
Short name T807
Test name
Test status
Simulation time 529096450 ps
CPU time 1.12 seconds
Started Jun 11 03:43:15 PM PDT 24
Finished Jun 11 03:43:18 PM PDT 24
Peak memory 201716 kb
Host smart-96f4691a-75ea-4e18-848b-63fd2d26d204
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101903127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.101903127
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.1330407606
Short name T805
Test name
Test status
Simulation time 340197643 ps
CPU time 0.92 seconds
Started Jun 11 03:43:15 PM PDT 24
Finished Jun 11 03:43:19 PM PDT 24
Peak memory 201704 kb
Host smart-33332c3e-2391-4b52-8fb7-cb3547eebfd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330407606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.1330407606
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3878203698
Short name T871
Test name
Test status
Simulation time 418695225 ps
CPU time 0.86 seconds
Started Jun 11 03:43:14 PM PDT 24
Finished Jun 11 03:43:17 PM PDT 24
Peak memory 201756 kb
Host smart-43f0900b-361c-4af9-ba16-5bf9021813bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878203698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.3878203698
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.2950105630
Short name T888
Test name
Test status
Simulation time 348405444 ps
CPU time 1.06 seconds
Started Jun 11 03:43:14 PM PDT 24
Finished Jun 11 03:43:16 PM PDT 24
Peak memory 201748 kb
Host smart-8dd82794-3764-48b2-b02a-a5af0d46b190
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950105630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.2950105630
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.814160560
Short name T799
Test name
Test status
Simulation time 447328389 ps
CPU time 1.78 seconds
Started Jun 11 03:43:17 PM PDT 24
Finished Jun 11 03:43:22 PM PDT 24
Peak memory 201716 kb
Host smart-2ec42ecf-dbd2-4c49-97d6-8b1cc8d7542d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814160560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.814160560
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.50634245
Short name T827
Test name
Test status
Simulation time 1209097618 ps
CPU time 2.86 seconds
Started Jun 11 03:42:35 PM PDT 24
Finished Jun 11 03:42:39 PM PDT 24
Peak memory 201952 kb
Host smart-b8811523-3c29-4146-84b5-2fd6f8062007
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50634245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_aliasi
ng.50634245
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.4063705118
Short name T903
Test name
Test status
Simulation time 30634466808 ps
CPU time 33.13 seconds
Started Jun 11 03:42:35 PM PDT 24
Finished Jun 11 03:43:09 PM PDT 24
Peak memory 202044 kb
Host smart-1618a236-b070-4b20-94d7-afdb2f285505
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063705118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.4063705118
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.3354241273
Short name T111
Test name
Test status
Simulation time 1420108920 ps
CPU time 4.15 seconds
Started Jun 11 03:42:33 PM PDT 24
Finished Jun 11 03:42:38 PM PDT 24
Peak memory 201892 kb
Host smart-da7181ec-07fe-4c1d-9dcb-614e1cfb3002
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354241273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.3354241273
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.919227178
Short name T890
Test name
Test status
Simulation time 478075864 ps
CPU time 1.15 seconds
Started Jun 11 03:42:34 PM PDT 24
Finished Jun 11 03:42:37 PM PDT 24
Peak memory 201760 kb
Host smart-2bd61dcc-3f80-4629-a0fc-d25feb97d655
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919227178 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.919227178
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.2786743882
Short name T118
Test name
Test status
Simulation time 533264281 ps
CPU time 2 seconds
Started Jun 11 03:42:34 PM PDT 24
Finished Jun 11 03:42:37 PM PDT 24
Peak memory 201744 kb
Host smart-9a4e38d1-5fd6-4ffd-99e6-33452b8b28dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786743882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.2786743882
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.4164072325
Short name T841
Test name
Test status
Simulation time 421922991 ps
CPU time 1.49 seconds
Started Jun 11 03:42:35 PM PDT 24
Finished Jun 11 03:42:37 PM PDT 24
Peak memory 201704 kb
Host smart-ef51cd93-fb89-4da7-9efd-bfa9b229ebe0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164072325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.4164072325
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.478868718
Short name T850
Test name
Test status
Simulation time 5121574335 ps
CPU time 12.06 seconds
Started Jun 11 03:42:36 PM PDT 24
Finished Jun 11 03:42:49 PM PDT 24
Peak memory 201976 kb
Host smart-ac1a1f3b-07e9-402e-802e-3b5c3b9cb5f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478868718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ct
rl_same_csr_outstanding.478868718
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1989844501
Short name T69
Test name
Test status
Simulation time 1220488842 ps
CPU time 3.4 seconds
Started Jun 11 03:42:34 PM PDT 24
Finished Jun 11 03:42:39 PM PDT 24
Peak memory 210188 kb
Host smart-4dd1e752-5562-43af-875c-99e38e28f7b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989844501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.1989844501
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3415371881
Short name T64
Test name
Test status
Simulation time 8042524257 ps
CPU time 20.77 seconds
Started Jun 11 03:42:34 PM PDT 24
Finished Jun 11 03:42:56 PM PDT 24
Peak memory 201972 kb
Host smart-67960f75-2e86-4323-8e02-f4635ae29682
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415371881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.3415371881
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1198487429
Short name T861
Test name
Test status
Simulation time 418217835 ps
CPU time 0.81 seconds
Started Jun 11 03:43:15 PM PDT 24
Finished Jun 11 03:43:19 PM PDT 24
Peak memory 201700 kb
Host smart-cdb3dfbb-5ba5-405f-8749-0b953b9a331d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198487429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.1198487429
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.1545607260
Short name T815
Test name
Test status
Simulation time 355159036 ps
CPU time 1.08 seconds
Started Jun 11 03:43:14 PM PDT 24
Finished Jun 11 03:43:17 PM PDT 24
Peak memory 201892 kb
Host smart-2ed56d1a-b8f3-43d2-aed6-7e6713ba36c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545607260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.1545607260
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.4160143738
Short name T868
Test name
Test status
Simulation time 367445268 ps
CPU time 1 seconds
Started Jun 11 03:43:13 PM PDT 24
Finished Jun 11 03:43:15 PM PDT 24
Peak memory 201732 kb
Host smart-c888da78-bb40-4673-97e5-3daddd5859ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160143738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.4160143738
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.4037117559
Short name T883
Test name
Test status
Simulation time 433429848 ps
CPU time 0.7 seconds
Started Jun 11 03:43:14 PM PDT 24
Finished Jun 11 03:43:16 PM PDT 24
Peak memory 201716 kb
Host smart-b9b6747d-c04c-44eb-baf7-ce3dc65962b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037117559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.4037117559
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.4177907186
Short name T893
Test name
Test status
Simulation time 411784980 ps
CPU time 0.91 seconds
Started Jun 11 03:43:14 PM PDT 24
Finished Jun 11 03:43:17 PM PDT 24
Peak memory 201748 kb
Host smart-681c437d-5aca-43a5-ae9d-4d69352e911d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177907186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.4177907186
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.1645467592
Short name T910
Test name
Test status
Simulation time 499837724 ps
CPU time 1.78 seconds
Started Jun 11 03:43:12 PM PDT 24
Finished Jun 11 03:43:15 PM PDT 24
Peak memory 201684 kb
Host smart-07591906-1ac5-4062-ab61-f6d333fdcea4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645467592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.1645467592
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.1057461530
Short name T833
Test name
Test status
Simulation time 540652713 ps
CPU time 0.99 seconds
Started Jun 11 03:43:16 PM PDT 24
Finished Jun 11 03:43:21 PM PDT 24
Peak memory 201716 kb
Host smart-8f2f9762-a298-4151-ac77-7d504ff4d7ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057461530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.1057461530
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.2399518856
Short name T801
Test name
Test status
Simulation time 495166386 ps
CPU time 0.73 seconds
Started Jun 11 03:43:14 PM PDT 24
Finished Jun 11 03:43:17 PM PDT 24
Peak memory 201744 kb
Host smart-77e67b8a-4b0a-4e72-a770-900a564fef5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399518856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.2399518856
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.358159540
Short name T806
Test name
Test status
Simulation time 330174418 ps
CPU time 1.45 seconds
Started Jun 11 03:43:15 PM PDT 24
Finished Jun 11 03:43:20 PM PDT 24
Peak memory 201732 kb
Host smart-f19981d1-de71-4ce3-b73d-b015dde769f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358159540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.358159540
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.3652336909
Short name T817
Test name
Test status
Simulation time 421108179 ps
CPU time 1.11 seconds
Started Jun 11 03:43:14 PM PDT 24
Finished Jun 11 03:43:17 PM PDT 24
Peak memory 201724 kb
Host smart-673defd4-feb3-46ac-bd2f-a40a4b763570
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652336909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.3652336909
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.83375901
Short name T814
Test name
Test status
Simulation time 523696729 ps
CPU time 1.13 seconds
Started Jun 11 03:42:34 PM PDT 24
Finished Jun 11 03:42:37 PM PDT 24
Peak memory 201792 kb
Host smart-ab31d336-d129-4449-8d20-8bfdb280c9b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83375901 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.83375901
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.122144987
Short name T115
Test name
Test status
Simulation time 721943634 ps
CPU time 0.9 seconds
Started Jun 11 03:42:35 PM PDT 24
Finished Jun 11 03:42:37 PM PDT 24
Peak memory 201728 kb
Host smart-eff6b580-afc0-4956-b4f6-7a82804ee57e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122144987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.122144987
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3577887548
Short name T803
Test name
Test status
Simulation time 392040245 ps
CPU time 1.06 seconds
Started Jun 11 03:42:34 PM PDT 24
Finished Jun 11 03:42:36 PM PDT 24
Peak memory 201712 kb
Host smart-8bb27635-63a2-4e07-b30c-0d39c2b1047c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577887548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.3577887548
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.355855844
Short name T835
Test name
Test status
Simulation time 5080201533 ps
CPU time 2.21 seconds
Started Jun 11 03:42:36 PM PDT 24
Finished Jun 11 03:42:39 PM PDT 24
Peak memory 201972 kb
Host smart-ed6c9c81-19ef-416c-8414-89db3ad8e912
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355855844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ct
rl_same_csr_outstanding.355855844
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.4116162649
Short name T904
Test name
Test status
Simulation time 518465053 ps
CPU time 3.02 seconds
Started Jun 11 03:42:33 PM PDT 24
Finished Jun 11 03:42:38 PM PDT 24
Peak memory 201992 kb
Host smart-dd56537f-34fc-4d94-82ca-f3ff5edffe32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116162649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.4116162649
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.4054809427
Short name T913
Test name
Test status
Simulation time 4117566637 ps
CPU time 4.25 seconds
Started Jun 11 03:42:34 PM PDT 24
Finished Jun 11 03:42:39 PM PDT 24
Peak memory 201920 kb
Host smart-c1b07a5a-741e-4db9-a2c9-48c40947264b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054809427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.4054809427
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1904843969
Short name T82
Test name
Test status
Simulation time 370520263 ps
CPU time 1 seconds
Started Jun 11 03:42:41 PM PDT 24
Finished Jun 11 03:42:44 PM PDT 24
Peak memory 201736 kb
Host smart-fa9417bf-4a3e-4c43-a866-95381693749b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904843969 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.1904843969
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.2248158031
Short name T851
Test name
Test status
Simulation time 377580161 ps
CPU time 1.26 seconds
Started Jun 11 03:42:35 PM PDT 24
Finished Jun 11 03:42:37 PM PDT 24
Peak memory 201728 kb
Host smart-81e9e36d-0ad9-4e0d-9146-a4ed3fad566d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248158031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.2248158031
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2537053127
Short name T826
Test name
Test status
Simulation time 496263604 ps
CPU time 1.2 seconds
Started Jun 11 03:42:34 PM PDT 24
Finished Jun 11 03:42:37 PM PDT 24
Peak memory 201740 kb
Host smart-8698d835-d4a9-4497-929e-672daac9606c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537053127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.2537053127
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.1584569455
Short name T836
Test name
Test status
Simulation time 4834166743 ps
CPU time 4.62 seconds
Started Jun 11 03:42:33 PM PDT 24
Finished Jun 11 03:42:39 PM PDT 24
Peak memory 201992 kb
Host smart-9af588cb-2a6f-44af-b39c-ca19d6507352
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584569455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.1584569455
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.3030634342
Short name T848
Test name
Test status
Simulation time 847383420 ps
CPU time 2.17 seconds
Started Jun 11 03:42:34 PM PDT 24
Finished Jun 11 03:42:38 PM PDT 24
Peak memory 201920 kb
Host smart-411fcce1-551c-4a50-ae89-b9966896dd6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030634342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.3030634342
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.182370236
Short name T824
Test name
Test status
Simulation time 5338297614 ps
CPU time 2.9 seconds
Started Jun 11 03:42:35 PM PDT 24
Finished Jun 11 03:42:40 PM PDT 24
Peak memory 202000 kb
Host smart-8d651bc1-7c84-46b8-bf8f-babd59849376
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182370236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_int
g_err.182370236
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.973375314
Short name T84
Test name
Test status
Simulation time 501956363 ps
CPU time 1.01 seconds
Started Jun 11 03:42:42 PM PDT 24
Finished Jun 11 03:42:45 PM PDT 24
Peak memory 201684 kb
Host smart-068f5141-0224-4f80-a386-588e2518ccd6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973375314 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.973375314
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3272763657
Short name T120
Test name
Test status
Simulation time 631598920 ps
CPU time 0.89 seconds
Started Jun 11 03:42:41 PM PDT 24
Finished Jun 11 03:42:43 PM PDT 24
Peak memory 201748 kb
Host smart-9c824f03-2e52-4825-af65-f40214c94912
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272763657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.3272763657
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.1306882750
Short name T898
Test name
Test status
Simulation time 522816053 ps
CPU time 0.96 seconds
Started Jun 11 03:42:42 PM PDT 24
Finished Jun 11 03:42:44 PM PDT 24
Peak memory 201724 kb
Host smart-a98f8ea7-25d1-4ab2-81f2-657d8555b887
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306882750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.1306882750
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2365849885
Short name T125
Test name
Test status
Simulation time 4938951327 ps
CPU time 12.63 seconds
Started Jun 11 03:42:42 PM PDT 24
Finished Jun 11 03:42:56 PM PDT 24
Peak memory 201936 kb
Host smart-bcdde192-ef25-45cc-a744-6841f04af6ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365849885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.2365849885
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.1124529369
Short name T854
Test name
Test status
Simulation time 518625123 ps
CPU time 2.19 seconds
Started Jun 11 03:42:43 PM PDT 24
Finished Jun 11 03:42:46 PM PDT 24
Peak memory 218252 kb
Host smart-d21d3266-9696-4565-b758-d664746b33f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124529369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.1124529369
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.4274790527
Short name T76
Test name
Test status
Simulation time 4239106947 ps
CPU time 5.85 seconds
Started Jun 11 03:42:42 PM PDT 24
Finished Jun 11 03:42:49 PM PDT 24
Peak memory 201996 kb
Host smart-46fab6d6-8317-492f-8acc-50679176f2cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274790527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.4274790527
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3646290142
Short name T831
Test name
Test status
Simulation time 434874629 ps
CPU time 1.32 seconds
Started Jun 11 03:42:39 PM PDT 24
Finished Jun 11 03:42:41 PM PDT 24
Peak memory 201768 kb
Host smart-cad8c6c9-2162-4d06-9d61-1805ed8bb8d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646290142 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.3646290142
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.4280814409
Short name T117
Test name
Test status
Simulation time 830594146 ps
CPU time 0.92 seconds
Started Jun 11 03:42:41 PM PDT 24
Finished Jun 11 03:42:43 PM PDT 24
Peak memory 201764 kb
Host smart-0e2c5dad-fd5f-4e36-81eb-a1b195657990
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280814409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.4280814409
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.42357195
Short name T837
Test name
Test status
Simulation time 439752426 ps
CPU time 0.89 seconds
Started Jun 11 03:42:42 PM PDT 24
Finished Jun 11 03:42:44 PM PDT 24
Peak memory 201704 kb
Host smart-da462c28-8806-4efb-859d-20c9fc80b0ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42357195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.42357195
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2100081886
Short name T901
Test name
Test status
Simulation time 2304139785 ps
CPU time 5.6 seconds
Started Jun 11 03:42:42 PM PDT 24
Finished Jun 11 03:42:49 PM PDT 24
Peak memory 201752 kb
Host smart-2015a452-586f-4526-b5bc-b24de4569841
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100081886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.2100081886
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1093033516
Short name T819
Test name
Test status
Simulation time 412239105 ps
CPU time 3.33 seconds
Started Jun 11 03:42:41 PM PDT 24
Finished Jun 11 03:42:45 PM PDT 24
Peak memory 210172 kb
Host smart-849f05db-2a17-4a51-8be6-ef9f29e7ac81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093033516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.1093033516
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.121813319
Short name T342
Test name
Test status
Simulation time 8922042182 ps
CPU time 7.63 seconds
Started Jun 11 03:42:40 PM PDT 24
Finished Jun 11 03:42:48 PM PDT 24
Peak memory 201964 kb
Host smart-d7e2ed98-c679-4ac8-8152-8e2a77327b2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121813319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_int
g_err.121813319
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3239005600
Short name T900
Test name
Test status
Simulation time 523464204 ps
CPU time 2.15 seconds
Started Jun 11 03:42:54 PM PDT 24
Finished Jun 11 03:42:57 PM PDT 24
Peak memory 201796 kb
Host smart-0749fb5b-59e2-438c-b5ee-3c49ef7bd393
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239005600 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.3239005600
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3034898972
Short name T853
Test name
Test status
Simulation time 576624562 ps
CPU time 1.07 seconds
Started Jun 11 03:42:50 PM PDT 24
Finished Jun 11 03:42:52 PM PDT 24
Peak memory 201764 kb
Host smart-632a1a45-1b32-44ea-ac4b-a069af20c369
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034898972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.3034898972
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.3650119491
Short name T811
Test name
Test status
Simulation time 482626751 ps
CPU time 1.82 seconds
Started Jun 11 03:42:50 PM PDT 24
Finished Jun 11 03:42:53 PM PDT 24
Peak memory 201712 kb
Host smart-e2b49d5d-2b37-4c8d-88b7-942ac3595aea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650119491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.3650119491
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.3883955420
Short name T838
Test name
Test status
Simulation time 4902426651 ps
CPU time 3.84 seconds
Started Jun 11 03:42:51 PM PDT 24
Finished Jun 11 03:42:55 PM PDT 24
Peak memory 201960 kb
Host smart-20ebac98-0553-4668-9459-43aeed1d100c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883955420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.3883955420
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2805964341
Short name T906
Test name
Test status
Simulation time 596155427 ps
CPU time 3 seconds
Started Jun 11 03:42:41 PM PDT 24
Finished Jun 11 03:42:46 PM PDT 24
Peak memory 218264 kb
Host smart-0268914a-149a-4cef-9593-194d795d61cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805964341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.2805964341
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2701409875
Short name T894
Test name
Test status
Simulation time 8587225181 ps
CPU time 21.74 seconds
Started Jun 11 03:42:41 PM PDT 24
Finished Jun 11 03:43:03 PM PDT 24
Peak memory 201940 kb
Host smart-d4d3c5ac-eeca-4e85-8eac-5e65dd3c9c4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701409875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.2701409875
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.1049653065
Short name T369
Test name
Test status
Simulation time 301566684 ps
CPU time 1.04 seconds
Started Jun 11 03:44:12 PM PDT 24
Finished Jun 11 03:44:14 PM PDT 24
Peak memory 201488 kb
Host smart-56beef3c-6cd2-430c-bfbc-7614ffe65534
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049653065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.1049653065
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.1805915347
Short name T280
Test name
Test status
Simulation time 198650515122 ps
CPU time 114.66 seconds
Started Jun 11 03:44:13 PM PDT 24
Finished Jun 11 03:46:09 PM PDT 24
Peak memory 201900 kb
Host smart-d7bdfd07-6ee4-42ad-9a12-65b46d8c63dc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805915347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.1805915347
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.2767530218
Short name T268
Test name
Test status
Simulation time 173200260869 ps
CPU time 207.63 seconds
Started Jun 11 03:44:11 PM PDT 24
Finished Jun 11 03:47:40 PM PDT 24
Peak memory 201816 kb
Host smart-e71c52e3-aefe-4ebc-96de-5cce4718b2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767530218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.2767530218
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.1869702079
Short name T530
Test name
Test status
Simulation time 162002106462 ps
CPU time 397.48 seconds
Started Jun 11 03:44:11 PM PDT 24
Finished Jun 11 03:50:50 PM PDT 24
Peak memory 201824 kb
Host smart-e346430a-ff01-48e8-8de3-0707ee94e156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869702079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.1869702079
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.2156984171
Short name T680
Test name
Test status
Simulation time 164996027750 ps
CPU time 100.32 seconds
Started Jun 11 03:44:09 PM PDT 24
Finished Jun 11 03:45:51 PM PDT 24
Peak memory 201780 kb
Host smart-d9755cf4-45e8-4d96-bf1c-b9cb5dc88ff9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156984171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.2156984171
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.1487514404
Short name T152
Test name
Test status
Simulation time 160420532617 ps
CPU time 200.07 seconds
Started Jun 11 03:44:13 PM PDT 24
Finished Jun 11 03:47:34 PM PDT 24
Peak memory 201872 kb
Host smart-3899bcb6-456c-4050-9678-9a7dbed51157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487514404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.1487514404
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.3421318685
Short name T547
Test name
Test status
Simulation time 485385158205 ps
CPU time 1070.25 seconds
Started Jun 11 03:44:12 PM PDT 24
Finished Jun 11 04:02:04 PM PDT 24
Peak memory 201872 kb
Host smart-b28d4ad0-5ea3-47f5-970f-13ad7a72522d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421318685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.3421318685
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.1586763923
Short name T581
Test name
Test status
Simulation time 291649081887 ps
CPU time 345.83 seconds
Started Jun 11 03:44:15 PM PDT 24
Finished Jun 11 03:50:01 PM PDT 24
Peak memory 201768 kb
Host smart-dce54ae8-6d1a-4b14-b81c-4087bc92bd58
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586763923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.1586763923
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.1068433602
Short name T559
Test name
Test status
Simulation time 389270820104 ps
CPU time 445.93 seconds
Started Jun 11 03:44:15 PM PDT 24
Finished Jun 11 03:51:42 PM PDT 24
Peak memory 201692 kb
Host smart-e782cf4f-e076-40c2-ad75-4080264f135e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068433602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.1068433602
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.3553096661
Short name T394
Test name
Test status
Simulation time 123091089103 ps
CPU time 648.37 seconds
Started Jun 11 03:44:12 PM PDT 24
Finished Jun 11 03:55:02 PM PDT 24
Peak memory 202148 kb
Host smart-b4ffafaf-e33a-4e1e-a6d9-3793e4c5dca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553096661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.3553096661
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.122878030
Short name T186
Test name
Test status
Simulation time 42514669358 ps
CPU time 52.98 seconds
Started Jun 11 03:44:10 PM PDT 24
Finished Jun 11 03:45:04 PM PDT 24
Peak memory 201604 kb
Host smart-fc5ae449-1211-4486-871e-8ef1833e7fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122878030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.122878030
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.3002415142
Short name T611
Test name
Test status
Simulation time 4151054524 ps
CPU time 1.8 seconds
Started Jun 11 03:44:10 PM PDT 24
Finished Jun 11 03:44:14 PM PDT 24
Peak memory 201580 kb
Host smart-232cd5bd-c760-4400-92f9-392d43930050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002415142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.3002415142
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.3680491337
Short name T66
Test name
Test status
Simulation time 4045532152 ps
CPU time 10.02 seconds
Started Jun 11 03:44:11 PM PDT 24
Finished Jun 11 03:44:22 PM PDT 24
Peak memory 217500 kb
Host smart-8ce61f11-9139-40a7-bc48-eab8ed8b7401
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680491337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.3680491337
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.3264161722
Short name T607
Test name
Test status
Simulation time 6071991437 ps
CPU time 4.41 seconds
Started Jun 11 03:44:10 PM PDT 24
Finished Jun 11 03:44:16 PM PDT 24
Peak memory 201564 kb
Host smart-9ddc2129-06e5-4bb9-810c-801d5a46e208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264161722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.3264161722
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.110144134
Short name T788
Test name
Test status
Simulation time 505642335082 ps
CPU time 1152.28 seconds
Started Jun 11 03:44:10 PM PDT 24
Finished Jun 11 04:03:24 PM PDT 24
Peak memory 201840 kb
Host smart-9816a26e-f10a-45b5-ad6f-bff203bd973d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110144134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.110144134
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.3503463383
Short name T766
Test name
Test status
Simulation time 33209397579 ps
CPU time 42.61 seconds
Started Jun 11 03:44:11 PM PDT 24
Finished Jun 11 03:44:55 PM PDT 24
Peak memory 218292 kb
Host smart-0a071b72-6f3c-43e8-b24f-7688e62ac4e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503463383 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.3503463383
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.3635127332
Short name T757
Test name
Test status
Simulation time 439684473 ps
CPU time 1.63 seconds
Started Jun 11 03:44:19 PM PDT 24
Finished Jun 11 03:44:21 PM PDT 24
Peak memory 201492 kb
Host smart-8d45e9c1-0335-46f8-82af-3bedb839c067
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635127332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.3635127332
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.1528605579
Short name T229
Test name
Test status
Simulation time 514126430080 ps
CPU time 303.42 seconds
Started Jun 11 03:44:19 PM PDT 24
Finished Jun 11 03:49:24 PM PDT 24
Peak memory 201812 kb
Host smart-725618e8-0af5-40f1-9a57-a11ef2c51e5f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528605579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.1528605579
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.4067864900
Short name T300
Test name
Test status
Simulation time 496622169639 ps
CPU time 1189.61 seconds
Started Jun 11 03:44:12 PM PDT 24
Finished Jun 11 04:04:03 PM PDT 24
Peak memory 201852 kb
Host smart-8f17873e-1764-4481-9124-f3cae491214a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067864900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.4067864900
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.3183678133
Short name T640
Test name
Test status
Simulation time 498314754538 ps
CPU time 1286.15 seconds
Started Jun 11 03:44:18 PM PDT 24
Finished Jun 11 04:05:46 PM PDT 24
Peak memory 201808 kb
Host smart-bc289e88-12cb-42bd-96c1-16e879b562ee
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183678133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.3183678133
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.2030670254
Short name T357
Test name
Test status
Simulation time 488193938368 ps
CPU time 275.15 seconds
Started Jun 11 03:44:15 PM PDT 24
Finished Jun 11 03:48:51 PM PDT 24
Peak memory 201704 kb
Host smart-cf0c7a5e-4c38-4fd6-b7c6-f6252d5fed80
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030670254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.2030670254
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.376586735
Short name T314
Test name
Test status
Simulation time 355786307618 ps
CPU time 894.03 seconds
Started Jun 11 03:44:18 PM PDT 24
Finished Jun 11 03:59:13 PM PDT 24
Peak memory 201924 kb
Host smart-9e74b9ec-af99-4605-a69e-74e221924103
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376586735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_w
akeup.376586735
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.819429723
Short name T190
Test name
Test status
Simulation time 395861192795 ps
CPU time 896.65 seconds
Started Jun 11 03:44:17 PM PDT 24
Finished Jun 11 03:59:15 PM PDT 24
Peak memory 201796 kb
Host smart-54c59f8a-deaf-4d80-a64a-e3cdb521aff9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819429723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.a
dc_ctrl_filters_wakeup_fixed.819429723
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.3264576518
Short name T588
Test name
Test status
Simulation time 111783058707 ps
CPU time 583.38 seconds
Started Jun 11 03:44:21 PM PDT 24
Finished Jun 11 03:54:05 PM PDT 24
Peak memory 202280 kb
Host smart-3fd654be-566a-4869-b971-f201325c1fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264576518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.3264576518
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.1903173575
Short name T744
Test name
Test status
Simulation time 41129418919 ps
CPU time 97.35 seconds
Started Jun 11 03:44:21 PM PDT 24
Finished Jun 11 03:45:59 PM PDT 24
Peak memory 201632 kb
Host smart-682a94bc-0087-44a4-86ad-cd77f24f65e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903173575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.1903173575
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.1847529219
Short name T652
Test name
Test status
Simulation time 4023545918 ps
CPU time 3.16 seconds
Started Jun 11 03:44:18 PM PDT 24
Finished Jun 11 03:44:22 PM PDT 24
Peak memory 201608 kb
Host smart-70623ae7-66c0-4554-8e00-7c51399ee56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847529219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.1847529219
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.2401163770
Short name T80
Test name
Test status
Simulation time 3799688138 ps
CPU time 3.23 seconds
Started Jun 11 03:44:20 PM PDT 24
Finished Jun 11 03:44:25 PM PDT 24
Peak memory 217372 kb
Host smart-5e666289-18b4-40e9-be6b-3967a618fc1a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401163770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.2401163770
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.966864596
Short name T495
Test name
Test status
Simulation time 6146209918 ps
CPU time 8.26 seconds
Started Jun 11 03:44:10 PM PDT 24
Finished Jun 11 03:44:20 PM PDT 24
Peak memory 201668 kb
Host smart-7ccf04b6-6052-4f81-9d21-c1e87048a867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966864596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.966864596
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.2879293692
Short name T614
Test name
Test status
Simulation time 93707066508 ps
CPU time 427.95 seconds
Started Jun 11 03:44:23 PM PDT 24
Finished Jun 11 03:51:32 PM PDT 24
Peak memory 210344 kb
Host smart-ab22d621-e3aa-4633-82f8-1c4a76adaacb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879293692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
2879293692
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.2804378289
Short name T350
Test name
Test status
Simulation time 334045914 ps
CPU time 0.79 seconds
Started Jun 11 03:44:55 PM PDT 24
Finished Jun 11 03:44:57 PM PDT 24
Peak memory 201472 kb
Host smart-cea34575-43ed-468e-a19d-25e02abcd603
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804378289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.2804378289
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.1482165740
Short name T646
Test name
Test status
Simulation time 169642789312 ps
CPU time 366.09 seconds
Started Jun 11 03:44:50 PM PDT 24
Finished Jun 11 03:50:58 PM PDT 24
Peak memory 201800 kb
Host smart-8ef19141-adcf-4683-bb71-e2a4d4c954e4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482165740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.1482165740
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.3172611098
Short name T756
Test name
Test status
Simulation time 533392497785 ps
CPU time 1344.08 seconds
Started Jun 11 03:45:01 PM PDT 24
Finished Jun 11 04:07:27 PM PDT 24
Peak memory 201848 kb
Host smart-763e551f-8925-4e97-91b8-7f61065d1949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172611098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.3172611098
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.1913679368
Short name T790
Test name
Test status
Simulation time 487755665948 ps
CPU time 1239.17 seconds
Started Jun 11 03:44:49 PM PDT 24
Finished Jun 11 04:05:30 PM PDT 24
Peak memory 201776 kb
Host smart-01eadd68-abf8-4993-8eaa-bcae3805170e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913679368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.1913679368
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.1028231949
Short name T711
Test name
Test status
Simulation time 492208857010 ps
CPU time 731.24 seconds
Started Jun 11 03:44:51 PM PDT 24
Finished Jun 11 03:57:04 PM PDT 24
Peak memory 201936 kb
Host smart-dca6411c-813a-4708-95af-9ba8a2cce4f3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028231949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.1028231949
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.1153077865
Short name T748
Test name
Test status
Simulation time 166166594133 ps
CPU time 157.14 seconds
Started Jun 11 03:44:54 PM PDT 24
Finished Jun 11 03:47:33 PM PDT 24
Peak memory 201808 kb
Host smart-907e738b-42e9-4d3c-a9bf-8e2985ecd5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153077865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.1153077865
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.1829391032
Short name T414
Test name
Test status
Simulation time 157853893491 ps
CPU time 63.75 seconds
Started Jun 11 03:44:51 PM PDT 24
Finished Jun 11 03:45:56 PM PDT 24
Peak memory 201780 kb
Host smart-5e02233e-0677-4132-be68-41c60d77ddb9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829391032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.1829391032
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.1710087233
Short name T234
Test name
Test status
Simulation time 365034053653 ps
CPU time 817.6 seconds
Started Jun 11 03:44:51 PM PDT 24
Finished Jun 11 03:58:30 PM PDT 24
Peak memory 201804 kb
Host smart-b21c0f69-701e-42ab-af52-b016a0efa626
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710087233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.1710087233
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.2329482947
Short name T172
Test name
Test status
Simulation time 43503614282 ps
CPU time 26.95 seconds
Started Jun 11 03:44:49 PM PDT 24
Finished Jun 11 03:45:17 PM PDT 24
Peak memory 201652 kb
Host smart-7b2459a8-a1ba-48fb-acf6-00ff516b22f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329482947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.2329482947
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.2473766070
Short name T445
Test name
Test status
Simulation time 3564926550 ps
CPU time 4.07 seconds
Started Jun 11 03:44:51 PM PDT 24
Finished Jun 11 03:44:57 PM PDT 24
Peak memory 201660 kb
Host smart-36b6d874-2811-4186-a984-6958b4a12ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473766070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.2473766070
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.1881253384
Short name T385
Test name
Test status
Simulation time 5985463419 ps
CPU time 7.78 seconds
Started Jun 11 03:45:00 PM PDT 24
Finished Jun 11 03:45:09 PM PDT 24
Peak memory 201600 kb
Host smart-7a582232-a052-4ba1-93dd-6bf833fe5c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881253384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.1881253384
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.1856619915
Short name T318
Test name
Test status
Simulation time 171069017960 ps
CPU time 392.78 seconds
Started Jun 11 03:44:54 PM PDT 24
Finished Jun 11 03:51:28 PM PDT 24
Peak memory 201800 kb
Host smart-98422c38-e200-4640-a46d-1acd23ffa9da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856619915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.1856619915
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.3834761530
Short name T263
Test name
Test status
Simulation time 222704165209 ps
CPU time 265.99 seconds
Started Jun 11 03:44:51 PM PDT 24
Finished Jun 11 03:49:19 PM PDT 24
Peak memory 218264 kb
Host smart-4789abf5-5678-4b3c-8af7-3d891b312856
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834761530 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.3834761530
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.2272075209
Short name T354
Test name
Test status
Simulation time 402111788 ps
CPU time 0.66 seconds
Started Jun 11 03:44:52 PM PDT 24
Finished Jun 11 03:44:54 PM PDT 24
Peak memory 201512 kb
Host smart-819be24e-b824-4823-93f2-ae90200c55f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272075209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.2272075209
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.2778365677
Short name T526
Test name
Test status
Simulation time 176445395145 ps
CPU time 89.46 seconds
Started Jun 11 03:44:55 PM PDT 24
Finished Jun 11 03:46:26 PM PDT 24
Peak memory 201788 kb
Host smart-e6bc8827-00b7-428e-ac53-a2c8bb726725
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778365677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.2778365677
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.1707081904
Short name T431
Test name
Test status
Simulation time 162398832304 ps
CPU time 97.98 seconds
Started Jun 11 03:44:50 PM PDT 24
Finished Jun 11 03:46:30 PM PDT 24
Peak memory 201820 kb
Host smart-63256b84-765e-405d-be6f-d448231b0093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707081904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.1707081904
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.159287413
Short name T411
Test name
Test status
Simulation time 155654098338 ps
CPU time 356.41 seconds
Started Jun 11 03:44:50 PM PDT 24
Finished Jun 11 03:50:48 PM PDT 24
Peak memory 201852 kb
Host smart-f57431e9-fe07-4ab0-86c9-3580ff4f1ddc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=159287413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrup
t_fixed.159287413
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.2711053002
Short name T568
Test name
Test status
Simulation time 334075826960 ps
CPU time 178.63 seconds
Started Jun 11 03:44:52 PM PDT 24
Finished Jun 11 03:47:53 PM PDT 24
Peak memory 201868 kb
Host smart-ff77caac-3020-4a46-887a-035233f660d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711053002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.2711053002
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.4269706957
Short name T479
Test name
Test status
Simulation time 338160338133 ps
CPU time 191.56 seconds
Started Jun 11 03:45:00 PM PDT 24
Finished Jun 11 03:48:13 PM PDT 24
Peak memory 201340 kb
Host smart-030cf761-24f9-489c-bcb3-b010615b7164
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269706957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.4269706957
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.1124337022
Short name T768
Test name
Test status
Simulation time 339677827887 ps
CPU time 845.56 seconds
Started Jun 11 03:44:52 PM PDT 24
Finished Jun 11 03:58:59 PM PDT 24
Peak memory 201780 kb
Host smart-6fb1ec39-9cb6-456d-8ad2-ddd0b4c59caa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124337022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.1124337022
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.1570439579
Short name T433
Test name
Test status
Simulation time 408331656895 ps
CPU time 357.42 seconds
Started Jun 11 03:44:51 PM PDT 24
Finished Jun 11 03:50:50 PM PDT 24
Peak memory 201804 kb
Host smart-37670f64-2bdb-4873-b674-fec84426e357
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570439579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.1570439579
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.478038349
Short name T453
Test name
Test status
Simulation time 83935967682 ps
CPU time 305.88 seconds
Started Jun 11 03:44:52 PM PDT 24
Finished Jun 11 03:50:00 PM PDT 24
Peak memory 202144 kb
Host smart-4419ed91-cb71-4697-a786-14b2a07cbf1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478038349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.478038349
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.3676163690
Short name T731
Test name
Test status
Simulation time 25000117723 ps
CPU time 56.54 seconds
Started Jun 11 03:44:54 PM PDT 24
Finished Jun 11 03:45:53 PM PDT 24
Peak memory 201632 kb
Host smart-9eba95ae-0804-44d9-9815-a75152431c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676163690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.3676163690
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.2298455243
Short name T439
Test name
Test status
Simulation time 4672036079 ps
CPU time 3.34 seconds
Started Jun 11 03:44:50 PM PDT 24
Finished Jun 11 03:44:56 PM PDT 24
Peak memory 201596 kb
Host smart-bae78b7b-d22c-40b3-8ce0-01dd33260e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298455243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.2298455243
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.222632377
Short name T371
Test name
Test status
Simulation time 5822358774 ps
CPU time 17.24 seconds
Started Jun 11 03:44:50 PM PDT 24
Finished Jun 11 03:45:09 PM PDT 24
Peak memory 201672 kb
Host smart-756c8ede-7bb4-4c9e-93d2-16ffcc1f037b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222632377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.222632377
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.763647110
Short name T574
Test name
Test status
Simulation time 327424428436 ps
CPU time 585.71 seconds
Started Jun 11 03:44:55 PM PDT 24
Finished Jun 11 03:54:42 PM PDT 24
Peak memory 210296 kb
Host smart-4220cb08-5283-4352-a8ac-6a621244cb32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763647110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all.
763647110
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.3428634529
Short name T51
Test name
Test status
Simulation time 1002238465161 ps
CPU time 351.74 seconds
Started Jun 11 03:45:01 PM PDT 24
Finished Jun 11 03:50:54 PM PDT 24
Peak memory 210440 kb
Host smart-befcfd15-241e-42cb-b719-968d380c199a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428634529 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.3428634529
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.664553019
Short name T376
Test name
Test status
Simulation time 452130406 ps
CPU time 0.92 seconds
Started Jun 11 03:45:00 PM PDT 24
Finished Jun 11 03:45:02 PM PDT 24
Peak memory 201508 kb
Host smart-a8c6b1b3-c2ef-483e-9144-14b125526428
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664553019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.664553019
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.3281706554
Short name T327
Test name
Test status
Simulation time 492889658002 ps
CPU time 344.65 seconds
Started Jun 11 03:45:04 PM PDT 24
Finished Jun 11 03:50:49 PM PDT 24
Peak memory 201752 kb
Host smart-eaf004d9-ef83-4929-b127-dde0e266f499
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281706554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.3281706554
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.783035872
Short name T102
Test name
Test status
Simulation time 327923342525 ps
CPU time 183.96 seconds
Started Jun 11 03:44:53 PM PDT 24
Finished Jun 11 03:47:59 PM PDT 24
Peak memory 201804 kb
Host smart-89a5f2b9-18be-411b-b066-001cc93e006e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783035872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.783035872
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.3252958946
Short name T624
Test name
Test status
Simulation time 323885890649 ps
CPU time 227.81 seconds
Started Jun 11 03:44:54 PM PDT 24
Finished Jun 11 03:48:44 PM PDT 24
Peak memory 201820 kb
Host smart-11afa9cb-e2d6-42cd-87f4-8a6968314961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252958946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.3252958946
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.3719586224
Short name T670
Test name
Test status
Simulation time 498220232680 ps
CPU time 1167.27 seconds
Started Jun 11 03:44:54 PM PDT 24
Finished Jun 11 04:04:23 PM PDT 24
Peak memory 201776 kb
Host smart-dcaa2258-8b5d-45b5-b91c-2480fde4ee91
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719586224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.3719586224
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.2164190300
Short name T664
Test name
Test status
Simulation time 356550136421 ps
CPU time 900.37 seconds
Started Jun 11 03:44:59 PM PDT 24
Finished Jun 11 04:00:01 PM PDT 24
Peak memory 201784 kb
Host smart-1b18f0f1-0402-4a1a-b2eb-6f0f337e4d66
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164190300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.2164190300
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.2687063170
Short name T450
Test name
Test status
Simulation time 195866297355 ps
CPU time 61.8 seconds
Started Jun 11 03:44:58 PM PDT 24
Finished Jun 11 03:46:01 PM PDT 24
Peak memory 201820 kb
Host smart-42b35ffd-03f8-4377-9527-cee1cce97a01
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687063170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.2687063170
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.2128146639
Short name T747
Test name
Test status
Simulation time 94326358087 ps
CPU time 305.82 seconds
Started Jun 11 03:44:59 PM PDT 24
Finished Jun 11 03:50:06 PM PDT 24
Peak memory 202236 kb
Host smart-da06a77f-47da-4f2e-909a-8cee6afc1a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128146639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.2128146639
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.795365453
Short name T675
Test name
Test status
Simulation time 32464845696 ps
CPU time 8.01 seconds
Started Jun 11 03:45:04 PM PDT 24
Finished Jun 11 03:45:13 PM PDT 24
Peak memory 201508 kb
Host smart-4c2cccb7-8084-4903-b80d-e9334e3c0e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795365453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.795365453
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.1680591980
Short name T10
Test name
Test status
Simulation time 4179034711 ps
CPU time 3.02 seconds
Started Jun 11 03:45:04 PM PDT 24
Finished Jun 11 03:45:08 PM PDT 24
Peak memory 201480 kb
Host smart-c1036d81-5505-42e3-9705-ea4098cf4a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680591980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.1680591980
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.3372265896
Short name T458
Test name
Test status
Simulation time 5595992669 ps
CPU time 4.81 seconds
Started Jun 11 03:44:52 PM PDT 24
Finished Jun 11 03:44:58 PM PDT 24
Peak memory 201660 kb
Host smart-cfc0bb03-fb8a-4075-937a-4e62fc1cdac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372265896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.3372265896
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.2185310854
Short name T531
Test name
Test status
Simulation time 265958974591 ps
CPU time 324.82 seconds
Started Jun 11 03:44:59 PM PDT 24
Finished Jun 11 03:50:25 PM PDT 24
Peak memory 201844 kb
Host smart-173a272a-c8d0-45a2-923a-243f8e70da1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185310854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.2185310854
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.981390952
Short name T619
Test name
Test status
Simulation time 34532962441 ps
CPU time 96.27 seconds
Started Jun 11 03:45:01 PM PDT 24
Finished Jun 11 03:46:39 PM PDT 24
Peak memory 210416 kb
Host smart-dde93c5f-750c-4452-ae52-33a62fa7448a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981390952 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.981390952
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.3026251995
Short name T506
Test name
Test status
Simulation time 368180777 ps
CPU time 1.43 seconds
Started Jun 11 03:44:59 PM PDT 24
Finished Jun 11 03:45:02 PM PDT 24
Peak memory 201496 kb
Host smart-c1668ca5-a262-4e20-a9b3-db8bb773131c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026251995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.3026251995
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.2410252057
Short name T561
Test name
Test status
Simulation time 426039956450 ps
CPU time 206.76 seconds
Started Jun 11 03:44:59 PM PDT 24
Finished Jun 11 03:48:27 PM PDT 24
Peak memory 201724 kb
Host smart-c63aee09-fabb-4bf1-bc45-00ceadea7e03
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410252057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.2410252057
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.966302815
Short name T145
Test name
Test status
Simulation time 164549494168 ps
CPU time 370.42 seconds
Started Jun 11 03:45:00 PM PDT 24
Finished Jun 11 03:51:12 PM PDT 24
Peak memory 201864 kb
Host smart-df03f3c1-14c4-4913-9daf-e3d112ca8f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966302815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.966302815
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.3124638484
Short name T89
Test name
Test status
Simulation time 492254521431 ps
CPU time 336.46 seconds
Started Jun 11 03:45:02 PM PDT 24
Finished Jun 11 03:50:40 PM PDT 24
Peak memory 201816 kb
Host smart-bb5ed6f5-4fea-4879-b902-de17ad4da43d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124638484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.3124638484
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.2220666337
Short name T334
Test name
Test status
Simulation time 499207098757 ps
CPU time 286.99 seconds
Started Jun 11 03:45:01 PM PDT 24
Finished Jun 11 03:49:50 PM PDT 24
Peak memory 201860 kb
Host smart-6935a9d7-4010-4273-9c06-62e083c7878f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220666337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.2220666337
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.1446744177
Short name T7
Test name
Test status
Simulation time 163444323805 ps
CPU time 104.58 seconds
Started Jun 11 03:44:58 PM PDT 24
Finished Jun 11 03:46:44 PM PDT 24
Peak memory 201796 kb
Host smart-28cfaf3c-439f-4746-8d89-0e3b6883b8c9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446744177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.1446744177
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.655816383
Short name T726
Test name
Test status
Simulation time 190226634794 ps
CPU time 175.09 seconds
Started Jun 11 03:45:02 PM PDT 24
Finished Jun 11 03:47:58 PM PDT 24
Peak memory 201852 kb
Host smart-711d2c7f-b2fb-4963-850f-a162eeda3d05
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655816383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_
wakeup.655816383
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.1838426147
Short name T551
Test name
Test status
Simulation time 408931798555 ps
CPU time 997.69 seconds
Started Jun 11 03:44:59 PM PDT 24
Finished Jun 11 04:01:38 PM PDT 24
Peak memory 201796 kb
Host smart-26e0f904-453b-4d3a-9c9a-5b7d33718802
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838426147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.1838426147
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.564078218
Short name T501
Test name
Test status
Simulation time 98879020572 ps
CPU time 435.06 seconds
Started Jun 11 03:45:02 PM PDT 24
Finished Jun 11 03:52:18 PM PDT 24
Peak memory 202092 kb
Host smart-76c3f3db-267a-4e2f-be52-98aa94a7dea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564078218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.564078218
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.346281773
Short name T797
Test name
Test status
Simulation time 21734203480 ps
CPU time 14.72 seconds
Started Jun 11 03:44:58 PM PDT 24
Finished Jun 11 03:45:13 PM PDT 24
Peak memory 201584 kb
Host smart-a786ad96-ef65-4436-ae25-0597cfe58b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346281773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.346281773
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.2297466495
Short name T755
Test name
Test status
Simulation time 4625960851 ps
CPU time 12.17 seconds
Started Jun 11 03:45:04 PM PDT 24
Finished Jun 11 03:45:17 PM PDT 24
Peak memory 201476 kb
Host smart-f7f8b2c3-8a29-4410-ac39-bacb26876940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297466495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.2297466495
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.1086216751
Short name T620
Test name
Test status
Simulation time 5649972917 ps
CPU time 14.47 seconds
Started Jun 11 03:45:00 PM PDT 24
Finished Jun 11 03:45:16 PM PDT 24
Peak memory 201652 kb
Host smart-83c1da29-d65a-4d4d-a2c7-0dd396f6b440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086216751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.1086216751
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.3542562150
Short name T20
Test name
Test status
Simulation time 167391993828 ps
CPU time 214.92 seconds
Started Jun 11 03:44:59 PM PDT 24
Finished Jun 11 03:48:35 PM PDT 24
Peak memory 210196 kb
Host smart-fb616fd2-344d-4138-8964-04a4a287b161
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542562150 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.3542562150
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.3994945467
Short name T692
Test name
Test status
Simulation time 385156577 ps
CPU time 0.91 seconds
Started Jun 11 03:45:08 PM PDT 24
Finished Jun 11 03:45:10 PM PDT 24
Peak memory 201488 kb
Host smart-bf231c8b-112d-4759-9b75-20d27d0a675d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994945467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.3994945467
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.2813871818
Short name T157
Test name
Test status
Simulation time 343318355932 ps
CPU time 96.23 seconds
Started Jun 11 03:45:08 PM PDT 24
Finished Jun 11 03:46:45 PM PDT 24
Peak memory 201984 kb
Host smart-9aa07faf-9f9f-4602-b999-90efb2636526
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813871818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.2813871818
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.382053162
Short name T259
Test name
Test status
Simulation time 166857093693 ps
CPU time 389.66 seconds
Started Jun 11 03:45:07 PM PDT 24
Finished Jun 11 03:51:39 PM PDT 24
Peak memory 201936 kb
Host smart-f24aeb14-3040-43f8-9622-680a0c218190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382053162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.382053162
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.1442027504
Short name T673
Test name
Test status
Simulation time 320088236149 ps
CPU time 765.8 seconds
Started Jun 11 03:45:09 PM PDT 24
Finished Jun 11 03:57:56 PM PDT 24
Peak memory 201820 kb
Host smart-f164a75f-28ab-456c-997d-a4a716846cd5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442027504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.1442027504
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.2988133901
Short name T333
Test name
Test status
Simulation time 501500066731 ps
CPU time 603.39 seconds
Started Jun 11 03:44:59 PM PDT 24
Finished Jun 11 03:55:03 PM PDT 24
Peak memory 201808 kb
Host smart-9673b1ba-ec89-4743-8564-e14c2bcdcdcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988133901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.2988133901
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.3869021451
Short name T648
Test name
Test status
Simulation time 483370534647 ps
CPU time 1234.46 seconds
Started Jun 11 03:45:07 PM PDT 24
Finished Jun 11 04:05:43 PM PDT 24
Peak memory 201744 kb
Host smart-d452f202-68e3-4ce9-b8bd-99dee914f969
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869021451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.3869021451
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.3175430725
Short name T305
Test name
Test status
Simulation time 548605826990 ps
CPU time 642.72 seconds
Started Jun 11 03:45:08 PM PDT 24
Finished Jun 11 03:55:52 PM PDT 24
Peak memory 201808 kb
Host smart-ee182b1c-e893-4883-8757-2aed4af87348
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175430725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.3175430725
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.4174945523
Short name T26
Test name
Test status
Simulation time 620649990345 ps
CPU time 353.09 seconds
Started Jun 11 03:45:08 PM PDT 24
Finished Jun 11 03:51:03 PM PDT 24
Peak memory 201892 kb
Host smart-22ae8c3d-2792-4228-90d4-de59a06c3641
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174945523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.4174945523
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.419136524
Short name T348
Test name
Test status
Simulation time 82319701392 ps
CPU time 341.79 seconds
Started Jun 11 03:45:06 PM PDT 24
Finished Jun 11 03:50:48 PM PDT 24
Peak memory 202048 kb
Host smart-2e611ada-7fa5-4855-bd38-c9e0b90d2116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419136524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.419136524
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.1509490177
Short name T787
Test name
Test status
Simulation time 46041378883 ps
CPU time 29.84 seconds
Started Jun 11 03:45:07 PM PDT 24
Finished Jun 11 03:45:38 PM PDT 24
Peak memory 201644 kb
Host smart-0725a406-5b3a-4fb5-a793-efd440eeab63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509490177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.1509490177
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.1681717684
Short name T678
Test name
Test status
Simulation time 2884967507 ps
CPU time 1.72 seconds
Started Jun 11 03:45:09 PM PDT 24
Finished Jun 11 03:45:12 PM PDT 24
Peak memory 201612 kb
Host smart-58b2fd54-1c10-4f1f-9b58-506bbe579f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681717684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.1681717684
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.3619053721
Short name T734
Test name
Test status
Simulation time 5865302946 ps
CPU time 2.01 seconds
Started Jun 11 03:45:02 PM PDT 24
Finished Jun 11 03:45:05 PM PDT 24
Peak memory 201640 kb
Host smart-23c0dfe6-5ee9-4f87-aac4-b5dc46c40726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619053721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.3619053721
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.2560212159
Short name T785
Test name
Test status
Simulation time 1262286981570 ps
CPU time 1932 seconds
Started Jun 11 03:45:10 PM PDT 24
Finished Jun 11 04:17:24 PM PDT 24
Peak memory 210300 kb
Host smart-8ca13782-4190-4117-b83d-fae589549a4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560212159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.2560212159
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.322283466
Short name T67
Test name
Test status
Simulation time 14550534052 ps
CPU time 48.64 seconds
Started Jun 11 03:45:08 PM PDT 24
Finished Jun 11 03:45:58 PM PDT 24
Peak memory 210504 kb
Host smart-f3df69b8-b82d-4536-a666-90e81de5ae90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322283466 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.322283466
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.1018678054
Short name T649
Test name
Test status
Simulation time 327516508349 ps
CPU time 114.5 seconds
Started Jun 11 03:45:07 PM PDT 24
Finished Jun 11 03:47:03 PM PDT 24
Peak memory 201908 kb
Host smart-e9ec8737-69ee-4b30-a909-51f19353585d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018678054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.1018678054
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.3803076792
Short name T312
Test name
Test status
Simulation time 173856533133 ps
CPU time 78.55 seconds
Started Jun 11 03:45:10 PM PDT 24
Finished Jun 11 03:46:30 PM PDT 24
Peak memory 201692 kb
Host smart-022aa01e-731a-4674-87e9-78a5b1999144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803076792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.3803076792
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.3922866896
Short name T281
Test name
Test status
Simulation time 161104347306 ps
CPU time 90.89 seconds
Started Jun 11 03:45:08 PM PDT 24
Finished Jun 11 03:46:41 PM PDT 24
Peak memory 202044 kb
Host smart-5b77b625-30c3-4f3f-97b5-1da043f5faa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922866896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.3922866896
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.31407395
Short name T691
Test name
Test status
Simulation time 165521969806 ps
CPU time 91.89 seconds
Started Jun 11 03:45:08 PM PDT 24
Finished Jun 11 03:46:42 PM PDT 24
Peak memory 201816 kb
Host smart-3fd9c089-ab1a-43c9-b037-f949e3643499
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=31407395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt
_fixed.31407395
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.292161835
Short name T537
Test name
Test status
Simulation time 163865494578 ps
CPU time 363.26 seconds
Started Jun 11 03:45:07 PM PDT 24
Finished Jun 11 03:51:12 PM PDT 24
Peak memory 201820 kb
Host smart-75efeb8c-fa1e-4a49-9a5f-1aa05bd5538f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292161835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.292161835
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.2533446668
Short name T676
Test name
Test status
Simulation time 487545191651 ps
CPU time 617.21 seconds
Started Jun 11 03:45:07 PM PDT 24
Finished Jun 11 03:55:25 PM PDT 24
Peak memory 201756 kb
Host smart-ea16074f-8eaf-4a43-9cb6-41fdc08e492e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533446668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.2533446668
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.123686460
Short name T54
Test name
Test status
Simulation time 390338379057 ps
CPU time 940.47 seconds
Started Jun 11 03:45:09 PM PDT 24
Finished Jun 11 04:00:51 PM PDT 24
Peak memory 201936 kb
Host smart-b9bf9eb4-4a8c-4047-a04c-b0c683cb4283
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123686460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_
wakeup.123686460
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.3309992771
Short name T712
Test name
Test status
Simulation time 625559752955 ps
CPU time 361.52 seconds
Started Jun 11 03:45:08 PM PDT 24
Finished Jun 11 03:51:11 PM PDT 24
Peak memory 201836 kb
Host smart-73557192-9720-418b-9a06-77a8d19dd086
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309992771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.3309992771
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.1622699050
Short name T536
Test name
Test status
Simulation time 75057493564 ps
CPU time 224.76 seconds
Started Jun 11 03:45:09 PM PDT 24
Finished Jun 11 03:48:55 PM PDT 24
Peak memory 202200 kb
Host smart-a93b24e1-fd84-4f22-b3e9-a4e36a51ea38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622699050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.1622699050
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.3721052286
Short name T465
Test name
Test status
Simulation time 22908629169 ps
CPU time 26.97 seconds
Started Jun 11 03:45:09 PM PDT 24
Finished Jun 11 03:45:37 PM PDT 24
Peak memory 201664 kb
Host smart-44111844-04bb-4794-9ea4-c969143dbdd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721052286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.3721052286
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.298606957
Short name T754
Test name
Test status
Simulation time 5422071642 ps
CPU time 14.09 seconds
Started Jun 11 03:45:08 PM PDT 24
Finished Jun 11 03:45:24 PM PDT 24
Peak memory 201656 kb
Host smart-9132358a-9a74-41d9-ac2d-f19d8d3dd392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298606957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.298606957
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.3233362181
Short name T784
Test name
Test status
Simulation time 5627002981 ps
CPU time 7.98 seconds
Started Jun 11 03:45:10 PM PDT 24
Finished Jun 11 03:45:19 PM PDT 24
Peak memory 201620 kb
Host smart-403f20de-db50-4bfa-9307-2cb3963933fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233362181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.3233362181
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.3499783566
Short name T35
Test name
Test status
Simulation time 4603255133 ps
CPU time 8.83 seconds
Started Jun 11 03:45:09 PM PDT 24
Finished Jun 11 03:45:19 PM PDT 24
Peak memory 201676 kb
Host smart-fd0e5072-9b65-49d2-9ecb-312476ff409d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499783566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.3499783566
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.2602967093
Short name T23
Test name
Test status
Simulation time 65537638853 ps
CPU time 118.94 seconds
Started Jun 11 03:45:07 PM PDT 24
Finished Jun 11 03:47:08 PM PDT 24
Peak memory 210100 kb
Host smart-75893758-5394-47a6-afe8-9fbdf75829c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602967093 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.2602967093
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.769904815
Short name T386
Test name
Test status
Simulation time 536664494 ps
CPU time 0.71 seconds
Started Jun 11 03:45:15 PM PDT 24
Finished Jun 11 03:45:17 PM PDT 24
Peak memory 201504 kb
Host smart-74afda8a-b492-4d68-a64b-8bc2d0bc223e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769904815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.769904815
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.2240775427
Short name T321
Test name
Test status
Simulation time 490417840291 ps
CPU time 297.76 seconds
Started Jun 11 03:45:16 PM PDT 24
Finished Jun 11 03:50:15 PM PDT 24
Peak memory 201892 kb
Host smart-eb0a38b3-da09-46c9-a5bb-3383379a0c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240775427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.2240775427
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.2837768180
Short name T460
Test name
Test status
Simulation time 164842399080 ps
CPU time 404.12 seconds
Started Jun 11 03:45:14 PM PDT 24
Finished Jun 11 03:51:59 PM PDT 24
Peak memory 201840 kb
Host smart-83927632-b5bc-401a-9b66-4535c71b80d6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837768180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.2837768180
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.65849370
Short name T279
Test name
Test status
Simulation time 334189097003 ps
CPU time 813.66 seconds
Started Jun 11 03:45:18 PM PDT 24
Finished Jun 11 03:58:53 PM PDT 24
Peak memory 201812 kb
Host smart-32ca48cc-1e3a-432f-a1d5-2ff291ae9637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65849370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.65849370
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.4130563718
Short name T426
Test name
Test status
Simulation time 489011439220 ps
CPU time 296.57 seconds
Started Jun 11 03:45:15 PM PDT 24
Finished Jun 11 03:50:12 PM PDT 24
Peak memory 201860 kb
Host smart-c7aac80c-ce52-47c8-86ce-d9c461b0a1a6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130563718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.4130563718
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.337092882
Short name T412
Test name
Test status
Simulation time 206279327516 ps
CPU time 112.27 seconds
Started Jun 11 03:45:15 PM PDT 24
Finished Jun 11 03:47:09 PM PDT 24
Peak memory 201716 kb
Host smart-2602e76e-6d09-4176-83e6-db936a697d11
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337092882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
adc_ctrl_filters_wakeup_fixed.337092882
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.3473079071
Short name T29
Test name
Test status
Simulation time 102076759556 ps
CPU time 565.77 seconds
Started Jun 11 03:45:18 PM PDT 24
Finished Jun 11 03:54:46 PM PDT 24
Peak memory 202192 kb
Host smart-172028f6-f9ac-40dc-b449-39dc12b2532e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473079071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.3473079071
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.115868741
Short name T413
Test name
Test status
Simulation time 23801703371 ps
CPU time 58.7 seconds
Started Jun 11 03:45:14 PM PDT 24
Finished Jun 11 03:46:14 PM PDT 24
Peak memory 201644 kb
Host smart-62be0832-4556-48f8-aee9-ccb6bc56e514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115868741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.115868741
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.2810078482
Short name T667
Test name
Test status
Simulation time 3698383462 ps
CPU time 3.62 seconds
Started Jun 11 03:45:18 PM PDT 24
Finished Jun 11 03:45:23 PM PDT 24
Peak memory 201620 kb
Host smart-b7fa6ed7-5896-4a93-8374-29701ebb1eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810078482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.2810078482
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.3989537004
Short name T533
Test name
Test status
Simulation time 6134855951 ps
CPU time 2.84 seconds
Started Jun 11 03:45:15 PM PDT 24
Finished Jun 11 03:45:18 PM PDT 24
Peak memory 201640 kb
Host smart-9125d345-9108-4220-8704-e54948178a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989537004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.3989537004
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.2428901854
Short name T158
Test name
Test status
Simulation time 164526379158 ps
CPU time 103.12 seconds
Started Jun 11 03:45:16 PM PDT 24
Finished Jun 11 03:47:00 PM PDT 24
Peak memory 201828 kb
Host smart-79af74cf-eb45-401c-b5c7-1eac0324f22a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428901854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.2428901854
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.3887505354
Short name T191
Test name
Test status
Simulation time 70222007319 ps
CPU time 147.55 seconds
Started Jun 11 03:45:14 PM PDT 24
Finished Jun 11 03:47:43 PM PDT 24
Peak memory 212144 kb
Host smart-01361ae1-ba29-4c7a-8a91-f3a701d06031
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887505354 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.3887505354
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.2337679270
Short name T99
Test name
Test status
Simulation time 452353925 ps
CPU time 0.99 seconds
Started Jun 11 03:45:25 PM PDT 24
Finished Jun 11 03:45:27 PM PDT 24
Peak memory 201504 kb
Host smart-4366d342-33d1-4a73-a3b4-1ec3b70ba9be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337679270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.2337679270
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.3673540797
Short name T617
Test name
Test status
Simulation time 381127811819 ps
CPU time 434.4 seconds
Started Jun 11 03:45:25 PM PDT 24
Finished Jun 11 03:52:41 PM PDT 24
Peak memory 201864 kb
Host smart-1fd8623c-fc32-4a8c-acbf-77bf3d106079
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673540797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.3673540797
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.4084292625
Short name T595
Test name
Test status
Simulation time 159946337154 ps
CPU time 199.93 seconds
Started Jun 11 03:45:25 PM PDT 24
Finished Jun 11 03:48:46 PM PDT 24
Peak memory 201756 kb
Host smart-a5227489-7ae4-42a1-8679-c0a5aa7861a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084292625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.4084292625
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.1656283625
Short name T304
Test name
Test status
Simulation time 482590910016 ps
CPU time 1228.35 seconds
Started Jun 11 03:45:24 PM PDT 24
Finished Jun 11 04:05:54 PM PDT 24
Peak memory 201896 kb
Host smart-f74b9f78-f751-485f-b41c-8858d621d65a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656283625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.1656283625
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.133902775
Short name T40
Test name
Test status
Simulation time 326410968472 ps
CPU time 745.27 seconds
Started Jun 11 03:45:25 PM PDT 24
Finished Jun 11 03:57:51 PM PDT 24
Peak memory 201840 kb
Host smart-85108a1c-173a-4d3b-ac1d-ac952dd6c88f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=133902775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrup
t_fixed.133902775
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.3857452508
Short name T98
Test name
Test status
Simulation time 320547954772 ps
CPU time 165.71 seconds
Started Jun 11 03:45:17 PM PDT 24
Finished Jun 11 03:48:03 PM PDT 24
Peak memory 201856 kb
Host smart-90d0ce4e-2d52-4b08-9d9d-f7794330cfdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857452508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.3857452508
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.248288120
Short name T632
Test name
Test status
Simulation time 163459670144 ps
CPU time 396.73 seconds
Started Jun 11 03:45:26 PM PDT 24
Finished Jun 11 03:52:04 PM PDT 24
Peak memory 201804 kb
Host smart-311d1724-4de5-4314-8727-d3f2d5210156
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=248288120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fixe
d.248288120
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.2708202789
Short name T237
Test name
Test status
Simulation time 689742438473 ps
CPU time 1662.17 seconds
Started Jun 11 03:45:25 PM PDT 24
Finished Jun 11 04:13:08 PM PDT 24
Peak memory 201804 kb
Host smart-4be295d0-fefa-4c35-90ab-bae502d3cccf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708202789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.2708202789
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.106275499
Short name T476
Test name
Test status
Simulation time 421967683429 ps
CPU time 1045.93 seconds
Started Jun 11 03:45:26 PM PDT 24
Finished Jun 11 04:02:53 PM PDT 24
Peak memory 201836 kb
Host smart-7f76328a-2b9a-47e5-a686-95f5592a7f0e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106275499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
adc_ctrl_filters_wakeup_fixed.106275499
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.2115640347
Short name T171
Test name
Test status
Simulation time 37335660891 ps
CPU time 87.33 seconds
Started Jun 11 03:45:25 PM PDT 24
Finished Jun 11 03:46:54 PM PDT 24
Peak memory 201612 kb
Host smart-9991d933-62f4-4b5b-8467-2a2cec67f0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115640347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.2115640347
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.3063890337
Short name T425
Test name
Test status
Simulation time 4289251654 ps
CPU time 2.99 seconds
Started Jun 11 03:45:25 PM PDT 24
Finished Jun 11 03:45:29 PM PDT 24
Peak memory 201548 kb
Host smart-1cb594da-5625-4f7c-a5dd-46ec09f0223d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063890337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.3063890337
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.2571761622
Short name T446
Test name
Test status
Simulation time 6017112801 ps
CPU time 14.79 seconds
Started Jun 11 03:45:14 PM PDT 24
Finished Jun 11 03:45:30 PM PDT 24
Peak memory 201664 kb
Host smart-2291c55d-b7a5-47d5-ab73-319d5268ceac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571761622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.2571761622
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.909475953
Short name T633
Test name
Test status
Simulation time 222898728758 ps
CPU time 273.03 seconds
Started Jun 11 03:45:27 PM PDT 24
Finished Jun 11 03:50:01 PM PDT 24
Peak memory 201812 kb
Host smart-6d7995e0-5ce8-47fb-9361-d2b460b9f66e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909475953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all.
909475953
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.3309524828
Short name T437
Test name
Test status
Simulation time 331323523 ps
CPU time 1.02 seconds
Started Jun 11 03:45:33 PM PDT 24
Finished Jun 11 03:45:36 PM PDT 24
Peak memory 201508 kb
Host smart-7c506f7f-35ce-478c-b069-68d93556ffa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309524828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.3309524828
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.3890559260
Short name T133
Test name
Test status
Simulation time 532534967085 ps
CPU time 1227.99 seconds
Started Jun 11 03:45:33 PM PDT 24
Finished Jun 11 04:06:02 PM PDT 24
Peak memory 201760 kb
Host smart-87e0c4a3-5153-4785-b050-7c78b452dc59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890559260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.3890559260
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.4041415319
Short name T582
Test name
Test status
Simulation time 170375903726 ps
CPU time 196.55 seconds
Started Jun 11 03:45:33 PM PDT 24
Finished Jun 11 03:48:51 PM PDT 24
Peak memory 201848 kb
Host smart-88182169-24d0-423b-92b7-6a4f6990a6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041415319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.4041415319
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.369788410
Short name T672
Test name
Test status
Simulation time 325889094200 ps
CPU time 761.27 seconds
Started Jun 11 03:45:34 PM PDT 24
Finished Jun 11 03:58:17 PM PDT 24
Peak memory 201824 kb
Host smart-689efcbc-5ac7-4bfe-a27a-cc35331f1c94
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=369788410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrup
t_fixed.369788410
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.2951385444
Short name T166
Test name
Test status
Simulation time 333950542518 ps
CPU time 147.79 seconds
Started Jun 11 03:45:26 PM PDT 24
Finished Jun 11 03:47:55 PM PDT 24
Peak memory 201896 kb
Host smart-adc58deb-22e7-4db6-b277-2eb77762a045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951385444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.2951385444
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.1416529237
Short name T616
Test name
Test status
Simulation time 164620533559 ps
CPU time 192.31 seconds
Started Jun 11 03:45:26 PM PDT 24
Finished Jun 11 03:48:39 PM PDT 24
Peak memory 201800 kb
Host smart-d9b0347d-3053-4d05-b6fa-2de6d8edcbda
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416529237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.1416529237
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.1355513311
Short name T317
Test name
Test status
Simulation time 345021552664 ps
CPU time 160.5 seconds
Started Jun 11 03:45:32 PM PDT 24
Finished Jun 11 03:48:13 PM PDT 24
Peak memory 201764 kb
Host smart-047b85e5-6bc5-45af-b2e4-bb4f2399bae9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355513311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.1355513311
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.1209944045
Short name T750
Test name
Test status
Simulation time 600190864078 ps
CPU time 237.14 seconds
Started Jun 11 03:45:35 PM PDT 24
Finished Jun 11 03:49:33 PM PDT 24
Peak memory 201796 kb
Host smart-bcee8ebd-55b5-4187-a6f8-aabbd2825338
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209944045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.1209944045
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.3824432981
Short name T447
Test name
Test status
Simulation time 34783613559 ps
CPU time 77.77 seconds
Started Jun 11 03:45:34 PM PDT 24
Finished Jun 11 03:46:53 PM PDT 24
Peak memory 201584 kb
Host smart-989e90df-48eb-4f93-97d2-2dcbc57651a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824432981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.3824432981
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.1611063190
Short name T509
Test name
Test status
Simulation time 5120442942 ps
CPU time 12.14 seconds
Started Jun 11 03:45:33 PM PDT 24
Finished Jun 11 03:45:46 PM PDT 24
Peak memory 201612 kb
Host smart-86d268c3-f306-4cb8-be5e-1c9f1a5440a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611063190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.1611063190
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.2818659293
Short name T505
Test name
Test status
Simulation time 5754584551 ps
CPU time 9.61 seconds
Started Jun 11 03:45:25 PM PDT 24
Finished Jun 11 03:45:36 PM PDT 24
Peak memory 201648 kb
Host smart-2fb88ae5-22a0-4e1d-99c1-464dc2bc84b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818659293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.2818659293
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.4028433169
Short name T430
Test name
Test status
Simulation time 507427280 ps
CPU time 0.91 seconds
Started Jun 11 03:45:40 PM PDT 24
Finished Jun 11 03:45:42 PM PDT 24
Peak memory 201528 kb
Host smart-b4a7c960-6b27-4786-a96b-7f5f5bc263f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028433169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.4028433169
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.969621352
Short name T61
Test name
Test status
Simulation time 394286495425 ps
CPU time 308.53 seconds
Started Jun 11 03:45:41 PM PDT 24
Finished Jun 11 03:50:50 PM PDT 24
Peak memory 201836 kb
Host smart-6bbacb0a-fc00-4fc1-ac12-bfd33bd04cba
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969621352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gati
ng.969621352
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.3163724821
Short name T219
Test name
Test status
Simulation time 513512462911 ps
CPU time 574.37 seconds
Started Jun 11 03:45:44 PM PDT 24
Finished Jun 11 03:55:19 PM PDT 24
Peak memory 201824 kb
Host smart-b1457ee0-3b07-4909-a5a3-18da6ec090b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163724821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.3163724821
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.2605169228
Short name T336
Test name
Test status
Simulation time 165703621785 ps
CPU time 78.35 seconds
Started Jun 11 03:45:39 PM PDT 24
Finished Jun 11 03:46:59 PM PDT 24
Peak memory 201848 kb
Host smart-544f036f-45ad-46a4-b7ee-d3bcd0ff6f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605169228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.2605169228
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.3894356366
Short name T375
Test name
Test status
Simulation time 329800027450 ps
CPU time 189.46 seconds
Started Jun 11 03:45:42 PM PDT 24
Finished Jun 11 03:48:53 PM PDT 24
Peak memory 201736 kb
Host smart-ea7b9fce-9ead-4588-aab6-d28b50a4aa19
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894356366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.3894356366
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.3092797927
Short name T523
Test name
Test status
Simulation time 506386817894 ps
CPU time 1299.29 seconds
Started Jun 11 03:45:31 PM PDT 24
Finished Jun 11 04:07:12 PM PDT 24
Peak memory 201744 kb
Host smart-36f993bc-57bc-4ca6-8afb-56fbef9b2878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092797927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.3092797927
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.189745191
Short name T637
Test name
Test status
Simulation time 489192767703 ps
CPU time 162.68 seconds
Started Jun 11 03:45:41 PM PDT 24
Finished Jun 11 03:48:24 PM PDT 24
Peak memory 201820 kb
Host smart-590a9c41-85c3-48cc-86d4-f12ce66671e3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=189745191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fixe
d.189745191
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.2535093246
Short name T228
Test name
Test status
Simulation time 519706110241 ps
CPU time 181.39 seconds
Started Jun 11 03:45:41 PM PDT 24
Finished Jun 11 03:48:43 PM PDT 24
Peak memory 201864 kb
Host smart-dd18c843-2f47-4d4c-a0e1-b36cfff9dbc3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535093246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.2535093246
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.1817094548
Short name T556
Test name
Test status
Simulation time 591153681873 ps
CPU time 1552.92 seconds
Started Jun 11 03:45:41 PM PDT 24
Finished Jun 11 04:11:35 PM PDT 24
Peak memory 201900 kb
Host smart-b71b8983-ff23-49c1-a899-266ae3a12a72
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817094548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.1817094548
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.3635133640
Short name T709
Test name
Test status
Simulation time 100157734033 ps
CPU time 317.12 seconds
Started Jun 11 03:45:44 PM PDT 24
Finished Jun 11 03:51:01 PM PDT 24
Peak memory 202136 kb
Host smart-c868f337-5c7f-4046-9aa3-5bc35e8cd4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635133640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.3635133640
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.2388828816
Short name T793
Test name
Test status
Simulation time 29515647430 ps
CPU time 70.53 seconds
Started Jun 11 03:45:44 PM PDT 24
Finished Jun 11 03:46:55 PM PDT 24
Peak memory 201616 kb
Host smart-0b86c0e8-9343-43a5-b970-119135bff615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388828816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.2388828816
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.1503078829
Short name T456
Test name
Test status
Simulation time 3407484847 ps
CPU time 4.6 seconds
Started Jun 11 03:45:40 PM PDT 24
Finished Jun 11 03:45:45 PM PDT 24
Peak memory 201640 kb
Host smart-b1bdbb08-8548-4440-9cd6-7cd8861c3baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503078829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.1503078829
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.4260132920
Short name T491
Test name
Test status
Simulation time 5715143850 ps
CPU time 6.97 seconds
Started Jun 11 03:45:33 PM PDT 24
Finished Jun 11 03:45:41 PM PDT 24
Peak memory 201648 kb
Host smart-d09bff1b-d0bb-4934-b305-6347eb15fa08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260132920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.4260132920
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.3547484013
Short name T657
Test name
Test status
Simulation time 170783036383 ps
CPU time 412.72 seconds
Started Jun 11 03:45:44 PM PDT 24
Finished Jun 11 03:52:37 PM PDT 24
Peak memory 201868 kb
Host smart-48022a0a-3744-47c7-ac41-c43c2b021179
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547484013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.3547484013
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.3017635133
Short name T204
Test name
Test status
Simulation time 632702680404 ps
CPU time 395.45 seconds
Started Jun 11 03:45:40 PM PDT 24
Finished Jun 11 03:52:17 PM PDT 24
Peak memory 210556 kb
Host smart-f46f56a1-f1da-4a43-8330-dde4d8eedf8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017635133 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.3017635133
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.3607510083
Short name T408
Test name
Test status
Simulation time 357333321 ps
CPU time 0.82 seconds
Started Jun 11 03:44:27 PM PDT 24
Finished Jun 11 03:44:29 PM PDT 24
Peak memory 201504 kb
Host smart-1998a245-adeb-4c21-8a94-cb4c60e1a468
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607510083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.3607510083
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.3738112602
Short name T758
Test name
Test status
Simulation time 343720707139 ps
CPU time 144.54 seconds
Started Jun 11 03:44:21 PM PDT 24
Finished Jun 11 03:46:47 PM PDT 24
Peak memory 201804 kb
Host smart-c7dbdedd-fa47-46ab-aad9-888bf39c8321
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738112602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.3738112602
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.3992397624
Short name T428
Test name
Test status
Simulation time 162552961273 ps
CPU time 353.02 seconds
Started Jun 11 03:44:18 PM PDT 24
Finished Jun 11 03:50:12 PM PDT 24
Peak memory 201820 kb
Host smart-35c14406-7d8b-43a7-9bdb-24ecdc1df7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992397624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.3992397624
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.2629547731
Short name T215
Test name
Test status
Simulation time 324003140994 ps
CPU time 750.28 seconds
Started Jun 11 03:44:20 PM PDT 24
Finished Jun 11 03:56:51 PM PDT 24
Peak memory 201804 kb
Host smart-0a47f4e3-7d47-4593-baca-42e448c734f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629547731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.2629547731
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.3438134992
Short name T512
Test name
Test status
Simulation time 487705218790 ps
CPU time 298.69 seconds
Started Jun 11 03:44:18 PM PDT 24
Finished Jun 11 03:49:18 PM PDT 24
Peak memory 201776 kb
Host smart-e105c88c-84b8-4ce6-9a19-b79be148aa90
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438134992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.3438134992
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.2815169885
Short name T167
Test name
Test status
Simulation time 329027589694 ps
CPU time 161.51 seconds
Started Jun 11 03:44:17 PM PDT 24
Finished Jun 11 03:47:00 PM PDT 24
Peak memory 201916 kb
Host smart-d671c612-a17d-44ee-8b19-367bef40cc8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815169885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.2815169885
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.3232968802
Short name T707
Test name
Test status
Simulation time 165539133782 ps
CPU time 88.09 seconds
Started Jun 11 03:44:23 PM PDT 24
Finished Jun 11 03:45:52 PM PDT 24
Peak memory 201828 kb
Host smart-2e35b31a-7fed-4513-b06c-a490ac0f5ba8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232968802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.3232968802
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.4193490922
Short name T239
Test name
Test status
Simulation time 556261516495 ps
CPU time 1272.42 seconds
Started Jun 11 03:44:20 PM PDT 24
Finished Jun 11 04:05:33 PM PDT 24
Peak memory 201860 kb
Host smart-80d6a509-1355-41cc-902d-8b93b95f4a22
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193490922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.4193490922
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.2298854706
Short name T367
Test name
Test status
Simulation time 391366487038 ps
CPU time 506.62 seconds
Started Jun 11 03:44:20 PM PDT 24
Finished Jun 11 03:52:48 PM PDT 24
Peak memory 201836 kb
Host smart-f72c84a5-513d-44a9-b0ab-f93284f1c4b9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298854706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.2298854706
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.416483045
Short name T211
Test name
Test status
Simulation time 76229761873 ps
CPU time 196.76 seconds
Started Jun 11 03:44:30 PM PDT 24
Finished Jun 11 03:47:48 PM PDT 24
Peak memory 202124 kb
Host smart-fdd83f07-bd46-4c7a-9215-ac662eec8e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416483045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.416483045
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.3062799294
Short name T393
Test name
Test status
Simulation time 35461627392 ps
CPU time 20.35 seconds
Started Jun 11 03:44:29 PM PDT 24
Finished Jun 11 03:44:51 PM PDT 24
Peak memory 201628 kb
Host smart-8f3f6d3e-cc6f-43f8-ab55-58a89936de5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062799294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.3062799294
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.73736432
Short name T441
Test name
Test status
Simulation time 5240990963 ps
CPU time 13.57 seconds
Started Jun 11 03:44:19 PM PDT 24
Finished Jun 11 03:44:34 PM PDT 24
Peak memory 201648 kb
Host smart-bb35cefa-335d-4725-af50-078c6749382c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73736432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.73736432
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.2190108950
Short name T661
Test name
Test status
Simulation time 5917166547 ps
CPU time 3.91 seconds
Started Jun 11 03:44:20 PM PDT 24
Finished Jun 11 03:44:24 PM PDT 24
Peak memory 201620 kb
Host smart-48beb724-388f-4c6c-af71-2e2a178e5da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190108950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.2190108950
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.2758936749
Short name T37
Test name
Test status
Simulation time 4369224122 ps
CPU time 5.95 seconds
Started Jun 11 03:44:26 PM PDT 24
Finished Jun 11 03:44:33 PM PDT 24
Peak memory 201616 kb
Host smart-b6c16ccc-fcb9-47ce-a17a-bbdc11f0e796
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758936749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
2758936749
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.1537509906
Short name T192
Test name
Test status
Simulation time 227970873346 ps
CPU time 396.13 seconds
Started Jun 11 03:44:27 PM PDT 24
Finished Jun 11 03:51:05 PM PDT 24
Peak memory 218512 kb
Host smart-01c1489c-bf03-46b0-bea4-ee15abfe9fef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537509906 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.1537509906
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.3367763415
Short name T546
Test name
Test status
Simulation time 510693629 ps
CPU time 1.19 seconds
Started Jun 11 03:45:52 PM PDT 24
Finished Jun 11 03:45:54 PM PDT 24
Peak memory 201484 kb
Host smart-f898438f-5073-4ec7-8354-4562df6a6626
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367763415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.3367763415
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.2393000836
Short name T735
Test name
Test status
Simulation time 497519925998 ps
CPU time 1143.42 seconds
Started Jun 11 03:45:50 PM PDT 24
Finished Jun 11 04:04:55 PM PDT 24
Peak memory 201788 kb
Host smart-4158a5d4-1b46-4541-b065-a825aade9548
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393000836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.2393000836
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.2764119881
Short name T764
Test name
Test status
Simulation time 171310215399 ps
CPU time 104.3 seconds
Started Jun 11 03:45:53 PM PDT 24
Finished Jun 11 03:47:38 PM PDT 24
Peak memory 201820 kb
Host smart-2ee201ba-922d-4fa8-9aee-c4eb01a0ff19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764119881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.2764119881
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.926263879
Short name T405
Test name
Test status
Simulation time 492436252718 ps
CPU time 321.6 seconds
Started Jun 11 03:45:42 PM PDT 24
Finished Jun 11 03:51:05 PM PDT 24
Peak memory 201728 kb
Host smart-5446675a-f19d-42d6-ba35-dfb9dd34baf0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=926263879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrup
t_fixed.926263879
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.2167012709
Short name T250
Test name
Test status
Simulation time 319961212361 ps
CPU time 738.46 seconds
Started Jun 11 03:45:42 PM PDT 24
Finished Jun 11 03:58:01 PM PDT 24
Peak memory 201904 kb
Host smart-d61d3ef3-24c1-4e56-af36-050659d37f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167012709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.2167012709
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.3933092625
Short name T542
Test name
Test status
Simulation time 166316311146 ps
CPU time 365.3 seconds
Started Jun 11 03:45:40 PM PDT 24
Finished Jun 11 03:51:47 PM PDT 24
Peak memory 201760 kb
Host smart-54a13203-a471-454f-a1a6-16208e7a87b7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933092625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.3933092625
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.690604876
Short name T233
Test name
Test status
Simulation time 184295218324 ps
CPU time 105.16 seconds
Started Jun 11 03:45:40 PM PDT 24
Finished Jun 11 03:47:26 PM PDT 24
Peak memory 201820 kb
Host smart-442f1584-0edb-44e9-8901-b0d798f44589
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690604876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_
wakeup.690604876
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.2142380468
Short name T507
Test name
Test status
Simulation time 191473564433 ps
CPU time 467.1 seconds
Started Jun 11 03:45:41 PM PDT 24
Finished Jun 11 03:53:29 PM PDT 24
Peak memory 201824 kb
Host smart-aa0e986e-b833-41d5-a11c-b7fe1c64b170
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142380468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.2142380468
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.3988250440
Short name T527
Test name
Test status
Simulation time 80773506834 ps
CPU time 363.51 seconds
Started Jun 11 03:45:51 PM PDT 24
Finished Jun 11 03:51:56 PM PDT 24
Peak memory 202236 kb
Host smart-47799f48-aaba-48ae-a817-59a917382bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988250440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.3988250440
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.2679105030
Short name T647
Test name
Test status
Simulation time 42764097853 ps
CPU time 51.99 seconds
Started Jun 11 03:45:51 PM PDT 24
Finished Jun 11 03:46:44 PM PDT 24
Peak memory 201616 kb
Host smart-5e84bd81-8209-4a13-b696-15488c66fe69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679105030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.2679105030
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.2600797984
Short name T361
Test name
Test status
Simulation time 4200583047 ps
CPU time 2.17 seconds
Started Jun 11 03:45:51 PM PDT 24
Finished Jun 11 03:45:54 PM PDT 24
Peak memory 201612 kb
Host smart-f641f63e-ce2f-40a5-a687-41d01675e794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600797984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.2600797984
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.1934398053
Short name T655
Test name
Test status
Simulation time 5912850714 ps
CPU time 4.2 seconds
Started Jun 11 03:45:41 PM PDT 24
Finished Jun 11 03:45:46 PM PDT 24
Peak memory 201620 kb
Host smart-f9f8ef0e-0ad1-44fe-b6b5-9d2931758fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934398053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.1934398053
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.81187897
Short name T202
Test name
Test status
Simulation time 444537854591 ps
CPU time 508.3 seconds
Started Jun 11 03:45:51 PM PDT 24
Finished Jun 11 03:54:21 PM PDT 24
Peak memory 202124 kb
Host smart-6fa63634-2926-40a6-a45b-fc5e3d631272
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81187897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all.81187897
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.593886674
Short name T600
Test name
Test status
Simulation time 285591369350 ps
CPU time 194.86 seconds
Started Jun 11 03:45:51 PM PDT 24
Finished Jun 11 03:49:07 PM PDT 24
Peak memory 210084 kb
Host smart-421dfbf0-3f4b-44c6-9bf5-144ca1f86172
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593886674 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.593886674
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.1110489852
Short name T697
Test name
Test status
Simulation time 445371593 ps
CPU time 1.14 seconds
Started Jun 11 03:45:58 PM PDT 24
Finished Jun 11 03:46:01 PM PDT 24
Peak memory 201504 kb
Host smart-4c9883a6-3068-4413-b9bc-6638f5e342d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110489852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.1110489852
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.2037268184
Short name T223
Test name
Test status
Simulation time 349578004799 ps
CPU time 176.65 seconds
Started Jun 11 03:45:58 PM PDT 24
Finished Jun 11 03:48:56 PM PDT 24
Peak memory 201868 kb
Host smart-7a25710d-94b3-42a1-8a1d-3487a5df1dc7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037268184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.2037268184
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.1497741739
Short name T182
Test name
Test status
Simulation time 162930522379 ps
CPU time 97.53 seconds
Started Jun 11 03:45:50 PM PDT 24
Finished Jun 11 03:47:29 PM PDT 24
Peak memory 201836 kb
Host smart-52b3e20c-3389-4435-9e8d-ac699587dfd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497741739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.1497741739
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.1970252081
Short name T370
Test name
Test status
Simulation time 489784543742 ps
CPU time 1261.35 seconds
Started Jun 11 03:45:51 PM PDT 24
Finished Jun 11 04:06:53 PM PDT 24
Peak memory 201824 kb
Host smart-c8cc8734-0ace-40d4-bb9f-65751b5fad3b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970252081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.1970252081
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.1192944269
Short name T339
Test name
Test status
Simulation time 162418208466 ps
CPU time 403.27 seconds
Started Jun 11 03:45:52 PM PDT 24
Finished Jun 11 03:52:36 PM PDT 24
Peak memory 201884 kb
Host smart-606b577b-47c0-447f-ad4c-e1494e756bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192944269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.1192944269
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.1306607142
Short name T592
Test name
Test status
Simulation time 163935194645 ps
CPU time 96.19 seconds
Started Jun 11 03:45:50 PM PDT 24
Finished Jun 11 03:47:27 PM PDT 24
Peak memory 201784 kb
Host smart-8b9a5c54-5dc0-43eb-9d7a-7637884d4012
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306607142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.1306607142
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.2526863474
Short name T283
Test name
Test status
Simulation time 538785447504 ps
CPU time 1257.89 seconds
Started Jun 11 03:45:50 PM PDT 24
Finished Jun 11 04:06:49 PM PDT 24
Peak memory 201792 kb
Host smart-56c3b9d4-862a-420c-a2f2-9aca0e4918fa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526863474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.2526863474
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.4063153908
Short name T351
Test name
Test status
Simulation time 410219771514 ps
CPU time 950.51 seconds
Started Jun 11 03:45:57 PM PDT 24
Finished Jun 11 04:01:49 PM PDT 24
Peak memory 201768 kb
Host smart-c2939f5b-32ae-4e5f-82c2-99a8bd8d2fb8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063153908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.4063153908
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.3974811821
Short name T733
Test name
Test status
Simulation time 120815871708 ps
CPU time 408.36 seconds
Started Jun 11 03:45:57 PM PDT 24
Finished Jun 11 03:52:47 PM PDT 24
Peak memory 202132 kb
Host smart-76601100-6291-4324-8e29-67612f430387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974811821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.3974811821
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.3339162822
Short name T398
Test name
Test status
Simulation time 33760406933 ps
CPU time 9.94 seconds
Started Jun 11 03:45:59 PM PDT 24
Finished Jun 11 03:46:10 PM PDT 24
Peak memory 201592 kb
Host smart-f434c52b-5f31-4b2a-8b7e-c5701191db70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339162822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.3339162822
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.3183604593
Short name T481
Test name
Test status
Simulation time 4538326110 ps
CPU time 3.51 seconds
Started Jun 11 03:45:57 PM PDT 24
Finished Jun 11 03:46:02 PM PDT 24
Peak memory 201632 kb
Host smart-c686b0cc-0e5d-466f-8702-2a4f113fc29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183604593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.3183604593
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.1845076053
Short name T721
Test name
Test status
Simulation time 5722433633 ps
CPU time 6.83 seconds
Started Jun 11 03:45:52 PM PDT 24
Finished Jun 11 03:46:00 PM PDT 24
Peak memory 201640 kb
Host smart-b9a55344-99a8-434d-afaf-e961619bf4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845076053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.1845076053
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.3210657231
Short name T210
Test name
Test status
Simulation time 583873522802 ps
CPU time 993.1 seconds
Started Jun 11 03:45:58 PM PDT 24
Finished Jun 11 04:02:32 PM PDT 24
Peak memory 210292 kb
Host smart-271cbb2d-b10e-40e1-9610-030a91cf1a1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210657231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.3210657231
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.3636131656
Short name T328
Test name
Test status
Simulation time 17030698325 ps
CPU time 16.04 seconds
Started Jun 11 03:45:58 PM PDT 24
Finished Jun 11 03:46:15 PM PDT 24
Peak memory 201972 kb
Host smart-82763d6a-690f-4c44-9318-3512a8cac732
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636131656 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.3636131656
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.4278911030
Short name T786
Test name
Test status
Simulation time 344008877 ps
CPU time 1 seconds
Started Jun 11 03:46:06 PM PDT 24
Finished Jun 11 03:46:08 PM PDT 24
Peak memory 201524 kb
Host smart-1c12204c-c5a0-44c0-82d7-0103ef46e1c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278911030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.4278911030
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.3547084288
Short name T130
Test name
Test status
Simulation time 352518430805 ps
CPU time 327.33 seconds
Started Jun 11 03:46:08 PM PDT 24
Finished Jun 11 03:51:36 PM PDT 24
Peak memory 202056 kb
Host smart-abbd5b86-cbf5-4a74-a569-47639b25eb7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547084288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.3547084288
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.1369679179
Short name T777
Test name
Test status
Simulation time 328254333989 ps
CPU time 223.92 seconds
Started Jun 11 03:45:58 PM PDT 24
Finished Jun 11 03:49:43 PM PDT 24
Peak memory 201912 kb
Host smart-c46ae3ca-055f-41d0-b81e-6ee709c11499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369679179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.1369679179
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.1604768762
Short name T486
Test name
Test status
Simulation time 327375538004 ps
CPU time 850.56 seconds
Started Jun 11 03:45:58 PM PDT 24
Finished Jun 11 04:00:10 PM PDT 24
Peak memory 201832 kb
Host smart-cfcb6b73-fa71-4697-b95e-7c349cf89e47
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604768762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.1604768762
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.4119890462
Short name T147
Test name
Test status
Simulation time 322182830196 ps
CPU time 806.43 seconds
Started Jun 11 03:45:58 PM PDT 24
Finished Jun 11 03:59:26 PM PDT 24
Peak memory 201692 kb
Host smart-f62047bd-8d39-46c3-8a61-425f75f37d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119890462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.4119890462
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.3175497690
Short name T455
Test name
Test status
Simulation time 325561025362 ps
CPU time 178.22 seconds
Started Jun 11 03:45:58 PM PDT 24
Finished Jun 11 03:48:57 PM PDT 24
Peak memory 201824 kb
Host smart-f705f84e-9d4b-427f-9dd9-09437d138916
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175497690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.3175497690
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.3810244686
Short name T324
Test name
Test status
Simulation time 524604794100 ps
CPU time 605.78 seconds
Started Jun 11 03:46:09 PM PDT 24
Finished Jun 11 03:56:15 PM PDT 24
Peak memory 201668 kb
Host smart-b9440daf-6748-4fff-84c5-91f697871f9d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810244686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.3810244686
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.1139180716
Short name T771
Test name
Test status
Simulation time 401701163416 ps
CPU time 243.31 seconds
Started Jun 11 03:46:06 PM PDT 24
Finished Jun 11 03:50:10 PM PDT 24
Peak memory 201748 kb
Host smart-08ed97bc-1a63-468b-8c55-3d235202e0ca
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139180716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.1139180716
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.3265191420
Short name T409
Test name
Test status
Simulation time 119520095477 ps
CPU time 638.72 seconds
Started Jun 11 03:46:06 PM PDT 24
Finished Jun 11 03:56:46 PM PDT 24
Peak memory 202200 kb
Host smart-02af9005-df65-4845-9167-1891a73c32a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265191420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.3265191420
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.2014940067
Short name T397
Test name
Test status
Simulation time 39071927233 ps
CPU time 61.23 seconds
Started Jun 11 03:46:06 PM PDT 24
Finished Jun 11 03:47:08 PM PDT 24
Peak memory 201648 kb
Host smart-ef6b0f97-02ec-4076-a992-a611293f62de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014940067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.2014940067
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.555527298
Short name T427
Test name
Test status
Simulation time 3035207882 ps
CPU time 7.93 seconds
Started Jun 11 03:46:07 PM PDT 24
Finished Jun 11 03:46:15 PM PDT 24
Peak memory 201664 kb
Host smart-652b8543-9c59-415d-a2cc-b312304b6cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555527298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.555527298
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.398531103
Short name T6
Test name
Test status
Simulation time 5647337062 ps
CPU time 3.48 seconds
Started Jun 11 03:45:58 PM PDT 24
Finished Jun 11 03:46:03 PM PDT 24
Peak memory 201652 kb
Host smart-00098707-2845-4940-9675-75754401a5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398531103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.398531103
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.3192115491
Short name T466
Test name
Test status
Simulation time 244448648686 ps
CPU time 800.24 seconds
Started Jun 11 03:46:06 PM PDT 24
Finished Jun 11 03:59:28 PM PDT 24
Peak memory 210308 kb
Host smart-ab028992-0031-4773-8a8e-ee998390e869
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192115491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.3192115491
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.2012934942
Short name T209
Test name
Test status
Simulation time 167845598941 ps
CPU time 313.76 seconds
Started Jun 11 03:46:06 PM PDT 24
Finished Jun 11 03:51:21 PM PDT 24
Peak memory 210492 kb
Host smart-e4b94c54-7865-4cf6-b071-d5246459c30e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012934942 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.2012934942
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.716508296
Short name T496
Test name
Test status
Simulation time 476348808 ps
CPU time 0.91 seconds
Started Jun 11 03:46:15 PM PDT 24
Finished Jun 11 03:46:18 PM PDT 24
Peak memory 201376 kb
Host smart-3f971f4d-bb07-437f-b6df-35481ec801a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716508296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.716508296
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.384911600
Short name T276
Test name
Test status
Simulation time 194523859017 ps
CPU time 180.54 seconds
Started Jun 11 03:46:15 PM PDT 24
Finished Jun 11 03:49:17 PM PDT 24
Peak memory 201872 kb
Host smart-c29fb320-f994-4638-9af6-fe5f1727c0ff
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384911600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gati
ng.384911600
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.2807374584
Short name T227
Test name
Test status
Simulation time 491711648318 ps
CPU time 1094.18 seconds
Started Jun 11 03:46:16 PM PDT 24
Finished Jun 11 04:04:32 PM PDT 24
Peak memory 201828 kb
Host smart-a4ba379a-5ead-480e-b812-cb7c3e8ad04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807374584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.2807374584
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.3566966380
Short name T454
Test name
Test status
Simulation time 323997929596 ps
CPU time 107.6 seconds
Started Jun 11 03:46:16 PM PDT 24
Finished Jun 11 03:48:06 PM PDT 24
Peak memory 201796 kb
Host smart-0e747496-fd94-4b89-8db7-e2b98e3ec450
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566966380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.3566966380
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.179592549
Short name T322
Test name
Test status
Simulation time 323351517600 ps
CPU time 100.16 seconds
Started Jun 11 03:46:16 PM PDT 24
Finished Jun 11 03:47:58 PM PDT 24
Peak memory 201852 kb
Host smart-9730e204-a680-486f-bcea-af3ace89f36e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179592549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.179592549
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.922658549
Short name T663
Test name
Test status
Simulation time 166991480373 ps
CPU time 43.54 seconds
Started Jun 11 03:46:17 PM PDT 24
Finished Jun 11 03:47:03 PM PDT 24
Peak memory 201768 kb
Host smart-914208e7-6643-4ee0-aee1-5b74155c7c14
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=922658549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fixe
d.922658549
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.1456615792
Short name T732
Test name
Test status
Simulation time 188880285191 ps
CPU time 227.85 seconds
Started Jun 11 03:46:14 PM PDT 24
Finished Jun 11 03:50:04 PM PDT 24
Peak memory 201804 kb
Host smart-fef52969-14e8-4f60-bbdf-4026ce294e79
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456615792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.1456615792
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.816174951
Short name T658
Test name
Test status
Simulation time 214100546034 ps
CPU time 241.63 seconds
Started Jun 11 03:46:16 PM PDT 24
Finished Jun 11 03:50:19 PM PDT 24
Peak memory 201760 kb
Host smart-cc612659-4bc3-4fc0-bb0d-36fc04aaaffb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816174951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
adc_ctrl_filters_wakeup_fixed.816174951
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.3754684027
Short name T656
Test name
Test status
Simulation time 39403689809 ps
CPU time 23.99 seconds
Started Jun 11 03:46:15 PM PDT 24
Finished Jun 11 03:46:41 PM PDT 24
Peak memory 201632 kb
Host smart-28e2cb50-757d-4406-8bce-1ae64b3149ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754684027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.3754684027
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.3724523440
Short name T449
Test name
Test status
Simulation time 3063301350 ps
CPU time 1.61 seconds
Started Jun 11 03:46:16 PM PDT 24
Finished Jun 11 03:46:19 PM PDT 24
Peak memory 201624 kb
Host smart-58c76cd9-03a8-48b6-a3d2-00cb75a550a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724523440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.3724523440
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.79154673
Short name T706
Test name
Test status
Simulation time 5658037753 ps
CPU time 7.23 seconds
Started Jun 11 03:46:07 PM PDT 24
Finished Jun 11 03:46:15 PM PDT 24
Peak memory 201644 kb
Host smart-d3a969a7-001d-4ccd-963c-a15fd3414170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79154673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.79154673
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.192514994
Short name T212
Test name
Test status
Simulation time 262661845372 ps
CPU time 633.55 seconds
Started Jun 11 03:46:16 PM PDT 24
Finished Jun 11 03:56:52 PM PDT 24
Peak memory 210352 kb
Host smart-988d9e39-5347-4570-956d-c440380d90e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192514994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all.
192514994
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.2469358985
Short name T610
Test name
Test status
Simulation time 517619448 ps
CPU time 1.18 seconds
Started Jun 11 03:46:32 PM PDT 24
Finished Jun 11 03:46:34 PM PDT 24
Peak memory 201488 kb
Host smart-9d849243-89af-4247-b49d-8f8037e2ca85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469358985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.2469358985
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.1385422491
Short name T762
Test name
Test status
Simulation time 164084092614 ps
CPU time 99.93 seconds
Started Jun 11 03:46:23 PM PDT 24
Finished Jun 11 03:48:05 PM PDT 24
Peak memory 201868 kb
Host smart-450fc18c-8342-4290-96a7-c5ce2d4fb4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385422491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.1385422491
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.2624343206
Short name T725
Test name
Test status
Simulation time 167993499259 ps
CPU time 103.95 seconds
Started Jun 11 03:46:23 PM PDT 24
Finished Jun 11 03:48:08 PM PDT 24
Peak memory 201812 kb
Host smart-5e2a1ce2-d73c-4667-a653-9b4e2d7e01a8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624343206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.2624343206
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.2482303398
Short name T185
Test name
Test status
Simulation time 162394753590 ps
CPU time 97.61 seconds
Started Jun 11 03:46:28 PM PDT 24
Finished Jun 11 03:48:06 PM PDT 24
Peak memory 201884 kb
Host smart-63a301f3-2682-4368-ae8d-1587191ce507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482303398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.2482303398
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.4003848698
Short name T423
Test name
Test status
Simulation time 168154421773 ps
CPU time 434.62 seconds
Started Jun 11 03:46:24 PM PDT 24
Finished Jun 11 03:53:40 PM PDT 24
Peak memory 201796 kb
Host smart-3f52faec-c9e8-4538-8562-097ba4535789
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003848698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.4003848698
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.794671989
Short name T759
Test name
Test status
Simulation time 193504278462 ps
CPU time 118.32 seconds
Started Jun 11 03:46:23 PM PDT 24
Finished Jun 11 03:48:23 PM PDT 24
Peak memory 201880 kb
Host smart-d14435d5-0a60-4d85-b558-e6e51ceae58f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794671989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_
wakeup.794671989
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.2907713475
Short name T410
Test name
Test status
Simulation time 402712441986 ps
CPU time 1019.38 seconds
Started Jun 11 03:46:23 PM PDT 24
Finished Jun 11 04:03:24 PM PDT 24
Peak memory 201800 kb
Host smart-e1518949-bec5-4af9-affd-4994a1ab41c8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907713475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.2907713475
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.212940142
Short name T593
Test name
Test status
Simulation time 94157941597 ps
CPU time 346.4 seconds
Started Jun 11 03:46:30 PM PDT 24
Finished Jun 11 03:52:18 PM PDT 24
Peak memory 202120 kb
Host smart-ce852b36-b050-4484-834c-7787c000fc39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212940142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.212940142
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.1443595045
Short name T358
Test name
Test status
Simulation time 30366656319 ps
CPU time 65.49 seconds
Started Jun 11 03:46:31 PM PDT 24
Finished Jun 11 03:47:38 PM PDT 24
Peak memory 201620 kb
Host smart-8ffd1561-10ec-43e3-864a-0ba3682c8918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443595045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.1443595045
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.3906786561
Short name T677
Test name
Test status
Simulation time 5201487215 ps
CPU time 3.47 seconds
Started Jun 11 03:46:31 PM PDT 24
Finished Jun 11 03:46:36 PM PDT 24
Peak memory 201620 kb
Host smart-c9c451a4-3679-4436-875e-4e547f37d40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906786561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.3906786561
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.1880180080
Short name T604
Test name
Test status
Simulation time 5794504463 ps
CPU time 14.59 seconds
Started Jun 11 03:46:17 PM PDT 24
Finished Jun 11 03:46:33 PM PDT 24
Peak memory 201596 kb
Host smart-d2821e31-0ef7-4f6f-8e88-3979190e7d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880180080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.1880180080
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.3294077056
Short name T753
Test name
Test status
Simulation time 170723756611 ps
CPU time 27 seconds
Started Jun 11 03:46:31 PM PDT 24
Finished Jun 11 03:46:59 PM PDT 24
Peak memory 201776 kb
Host smart-83349ebc-ac8b-42bc-8470-03d094cfe800
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294077056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.3294077056
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.604550160
Short name T2
Test name
Test status
Simulation time 49489817625 ps
CPU time 30.95 seconds
Started Jun 11 03:46:30 PM PDT 24
Finished Jun 11 03:47:01 PM PDT 24
Peak memory 210104 kb
Host smart-5f26a164-ce8d-497f-99ea-e950bb036ab1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604550160 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.604550160
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.1065225546
Short name T365
Test name
Test status
Simulation time 425385039 ps
CPU time 1.57 seconds
Started Jun 11 03:46:40 PM PDT 24
Finished Jun 11 03:46:42 PM PDT 24
Peak memory 201504 kb
Host smart-9dcddeda-6291-4b01-8e94-42119a126f46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065225546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.1065225546
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.2727045698
Short name T330
Test name
Test status
Simulation time 403849806667 ps
CPU time 852.68 seconds
Started Jun 11 03:46:38 PM PDT 24
Finished Jun 11 04:00:52 PM PDT 24
Peak memory 201840 kb
Host smart-acbf7707-a867-485c-8641-00800048a2f7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727045698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.2727045698
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.2709076074
Short name T639
Test name
Test status
Simulation time 497575524556 ps
CPU time 1237.58 seconds
Started Jun 11 03:46:38 PM PDT 24
Finished Jun 11 04:07:16 PM PDT 24
Peak memory 201812 kb
Host smart-e1409d14-9c01-46b1-ae31-b3d0521506d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709076074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.2709076074
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.735584031
Short name T682
Test name
Test status
Simulation time 155152027716 ps
CPU time 73.5 seconds
Started Jun 11 03:46:31 PM PDT 24
Finished Jun 11 03:47:45 PM PDT 24
Peak memory 201732 kb
Host smart-97beddf9-4129-4805-9383-c1fae67166b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735584031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.735584031
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.4092453273
Short name T538
Test name
Test status
Simulation time 340722715082 ps
CPU time 156.34 seconds
Started Jun 11 03:46:30 PM PDT 24
Finished Jun 11 03:49:08 PM PDT 24
Peak memory 201804 kb
Host smart-680401a6-79da-49e6-9e58-c133ce1960db
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092453273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.4092453273
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.2460682753
Short name T606
Test name
Test status
Simulation time 163726269084 ps
CPU time 368.5 seconds
Started Jun 11 03:46:30 PM PDT 24
Finished Jun 11 03:52:39 PM PDT 24
Peak memory 201840 kb
Host smart-ba25e567-4ca5-4716-b02f-c2d33b4e4fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460682753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.2460682753
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.3932027488
Short name T30
Test name
Test status
Simulation time 157642322814 ps
CPU time 92.06 seconds
Started Jun 11 03:46:32 PM PDT 24
Finished Jun 11 03:48:05 PM PDT 24
Peak memory 201824 kb
Host smart-37032cf3-7865-4658-95f7-6a4ef9146239
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932027488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.3932027488
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.1489182365
Short name T141
Test name
Test status
Simulation time 525012136417 ps
CPU time 1254.12 seconds
Started Jun 11 03:46:39 PM PDT 24
Finished Jun 11 04:07:34 PM PDT 24
Peak memory 201872 kb
Host smart-2885c497-0941-4edc-8e47-ddd7edbd5f7a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489182365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.1489182365
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.2065592762
Short name T549
Test name
Test status
Simulation time 388354562490 ps
CPU time 149.48 seconds
Started Jun 11 03:46:38 PM PDT 24
Finished Jun 11 03:49:08 PM PDT 24
Peak memory 201828 kb
Host smart-374ba99a-09a0-4004-bac3-d389144124ef
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065592762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.2065592762
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.705626893
Short name T41
Test name
Test status
Simulation time 81841814285 ps
CPU time 337.5 seconds
Started Jun 11 03:46:38 PM PDT 24
Finished Jun 11 03:52:16 PM PDT 24
Peak memory 202104 kb
Host smart-a3525585-e848-445a-8874-7f8b600863ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705626893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.705626893
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.1650139827
Short name T586
Test name
Test status
Simulation time 46049872804 ps
CPU time 29.54 seconds
Started Jun 11 03:46:41 PM PDT 24
Finished Jun 11 03:47:12 PM PDT 24
Peak memory 201628 kb
Host smart-7f88e1a9-2ff4-4ae9-904b-e1be7e035666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650139827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.1650139827
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.775213130
Short name T419
Test name
Test status
Simulation time 4296327798 ps
CPU time 10.82 seconds
Started Jun 11 03:46:40 PM PDT 24
Finished Jun 11 03:46:51 PM PDT 24
Peak memory 201644 kb
Host smart-c2f507e9-9e89-4a07-bf82-2447c6f4f8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775213130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.775213130
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.3897096247
Short name T489
Test name
Test status
Simulation time 5575994456 ps
CPU time 3.1 seconds
Started Jun 11 03:46:31 PM PDT 24
Finished Jun 11 03:46:35 PM PDT 24
Peak memory 201668 kb
Host smart-be585225-9243-4cbf-a289-5f5952e86ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897096247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.3897096247
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.4171138410
Short name T590
Test name
Test status
Simulation time 239617907460 ps
CPU time 986.56 seconds
Started Jun 11 03:46:38 PM PDT 24
Finished Jun 11 04:03:05 PM PDT 24
Peak memory 202112 kb
Host smart-15aa2430-496e-4045-abc3-e78a6b1f24c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171138410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.4171138410
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.1969952266
Short name T587
Test name
Test status
Simulation time 389019619 ps
CPU time 1.65 seconds
Started Jun 11 03:47:02 PM PDT 24
Finished Jun 11 03:47:04 PM PDT 24
Peak memory 201500 kb
Host smart-0f9925e4-0171-477b-bae2-1e2691630b80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969952266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.1969952266
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.3928141166
Short name T340
Test name
Test status
Simulation time 533556078245 ps
CPU time 1178.65 seconds
Started Jun 11 03:46:47 PM PDT 24
Finished Jun 11 04:06:27 PM PDT 24
Peak memory 201824 kb
Host smart-ff705058-ef81-414a-8e44-6a59536a7222
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928141166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.3928141166
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.851613924
Short name T48
Test name
Test status
Simulation time 330458918268 ps
CPU time 753.35 seconds
Started Jun 11 03:46:46 PM PDT 24
Finished Jun 11 03:59:21 PM PDT 24
Peak memory 201856 kb
Host smart-bc5331bc-8232-4d60-b4c4-72e874156c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851613924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.851613924
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.3335009115
Short name T660
Test name
Test status
Simulation time 492652062401 ps
CPU time 1161.82 seconds
Started Jun 11 03:46:37 PM PDT 24
Finished Jun 11 04:06:00 PM PDT 24
Peak memory 201816 kb
Host smart-22a9fbee-5df1-43c6-a96f-85832a8c0b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335009115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.3335009115
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.2076922440
Short name T641
Test name
Test status
Simulation time 337603541741 ps
CPU time 823.68 seconds
Started Jun 11 03:46:48 PM PDT 24
Finished Jun 11 04:00:32 PM PDT 24
Peak memory 201772 kb
Host smart-e49b8188-24f8-4439-a07a-ecbbb64099c2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076922440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.2076922440
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.4202030192
Short name T27
Test name
Test status
Simulation time 326630612681 ps
CPU time 367.74 seconds
Started Jun 11 03:46:39 PM PDT 24
Finished Jun 11 03:52:48 PM PDT 24
Peak memory 201844 kb
Host smart-47eb6d51-f4cc-4889-a150-1f80e00f5754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202030192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.4202030192
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.1912303489
Short name T175
Test name
Test status
Simulation time 158578167304 ps
CPU time 97.54 seconds
Started Jun 11 03:46:39 PM PDT 24
Finished Jun 11 03:48:18 PM PDT 24
Peak memory 201704 kb
Host smart-ad7addc5-91b1-4551-b4c6-15835cfa640b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912303489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.1912303489
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.2800863559
Short name T296
Test name
Test status
Simulation time 552457932686 ps
CPU time 341.32 seconds
Started Jun 11 03:46:46 PM PDT 24
Finished Jun 11 03:52:29 PM PDT 24
Peak memory 201788 kb
Host smart-b2ebcc4a-4963-4e00-91bf-a9b6a59db8f5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800863559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.2800863559
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.3517829849
Short name T493
Test name
Test status
Simulation time 203314724760 ps
CPU time 288.4 seconds
Started Jun 11 03:46:47 PM PDT 24
Finished Jun 11 03:51:36 PM PDT 24
Peak memory 201836 kb
Host smart-6f8ca385-fcb6-4224-b8e5-34eb79428538
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517829849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.3517829849
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.3636441862
Short name T528
Test name
Test status
Simulation time 93899493435 ps
CPU time 396.23 seconds
Started Jun 11 03:46:46 PM PDT 24
Finished Jun 11 03:53:23 PM PDT 24
Peak memory 202116 kb
Host smart-688e5be8-0eb4-43e7-9a7a-da78c7245bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636441862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.3636441862
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.1233347299
Short name T603
Test name
Test status
Simulation time 31419408065 ps
CPU time 17.6 seconds
Started Jun 11 03:46:48 PM PDT 24
Finished Jun 11 03:47:07 PM PDT 24
Peak memory 201620 kb
Host smart-d4c0ed6b-2be3-40c0-8d3b-29c1ab0ceaff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233347299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.1233347299
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.3042195849
Short name T598
Test name
Test status
Simulation time 4948512135 ps
CPU time 3.64 seconds
Started Jun 11 03:46:48 PM PDT 24
Finished Jun 11 03:46:53 PM PDT 24
Peak memory 201504 kb
Host smart-14393b21-2be1-4ede-919b-e4546166e6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042195849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.3042195849
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.73091248
Short name T101
Test name
Test status
Simulation time 5805027418 ps
CPU time 7.39 seconds
Started Jun 11 03:46:37 PM PDT 24
Finished Jun 11 03:46:45 PM PDT 24
Peak memory 201640 kb
Host smart-d0e800c2-9fcc-45cc-b9f6-a01143677e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73091248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.73091248
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.2596640756
Short name T174
Test name
Test status
Simulation time 361294115311 ps
CPU time 866.84 seconds
Started Jun 11 03:46:55 PM PDT 24
Finished Jun 11 04:01:23 PM PDT 24
Peak memory 201832 kb
Host smart-5cd9beef-be40-46b0-bfc8-a4bc6b2d30c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596640756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.2596640756
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.1791137645
Short name T311
Test name
Test status
Simulation time 63744702589 ps
CPU time 80.87 seconds
Started Jun 11 03:46:57 PM PDT 24
Finished Jun 11 03:48:19 PM PDT 24
Peak memory 210132 kb
Host smart-3a4c5c4c-5fdb-44a0-85d4-6233b7bfeea9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791137645 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.1791137645
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.1538631092
Short name T564
Test name
Test status
Simulation time 318055430 ps
CPU time 1.37 seconds
Started Jun 11 03:47:04 PM PDT 24
Finished Jun 11 03:47:07 PM PDT 24
Peak memory 201376 kb
Host smart-c5c584b8-a169-4a15-b0a0-6c639d1d35d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538631092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.1538631092
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.3258764091
Short name T315
Test name
Test status
Simulation time 165618239411 ps
CPU time 113.55 seconds
Started Jun 11 03:47:03 PM PDT 24
Finished Jun 11 03:48:57 PM PDT 24
Peak memory 202060 kb
Host smart-7f9d5307-d6ff-4a66-aaa1-f23c35702336
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258764091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.3258764091
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.1617686014
Short name T332
Test name
Test status
Simulation time 345618925021 ps
CPU time 829.31 seconds
Started Jun 11 03:47:03 PM PDT 24
Finished Jun 11 04:00:53 PM PDT 24
Peak memory 201848 kb
Host smart-56673625-4886-46d2-abd7-463612d49a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617686014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.1617686014
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.2047315849
Short name T274
Test name
Test status
Simulation time 163127827969 ps
CPU time 113.58 seconds
Started Jun 11 03:47:02 PM PDT 24
Finished Jun 11 03:48:56 PM PDT 24
Peak memory 201812 kb
Host smart-8b6949db-9906-4ed8-acfa-af3b64b7a7d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047315849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.2047315849
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.3781603075
Short name T416
Test name
Test status
Simulation time 161189184685 ps
CPU time 195.42 seconds
Started Jun 11 03:46:53 PM PDT 24
Finished Jun 11 03:50:10 PM PDT 24
Peak memory 201848 kb
Host smart-41be4006-3801-4a97-ab39-5fe8e8e5cbd6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781603075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.3781603075
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.2777380137
Short name T153
Test name
Test status
Simulation time 492174364646 ps
CPU time 96.1 seconds
Started Jun 11 03:46:56 PM PDT 24
Finished Jun 11 03:48:33 PM PDT 24
Peak memory 201840 kb
Host smart-301f3972-80f8-420f-98ff-c10b57dae28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777380137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.2777380137
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.3858779804
Short name T457
Test name
Test status
Simulation time 165504985350 ps
CPU time 101.38 seconds
Started Jun 11 03:46:55 PM PDT 24
Finished Jun 11 03:48:37 PM PDT 24
Peak memory 201804 kb
Host smart-6b0fc142-add7-421c-ba74-fa4e606a2df7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858779804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.3858779804
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.1833514762
Short name T737
Test name
Test status
Simulation time 179549851654 ps
CPU time 234.64 seconds
Started Jun 11 03:46:56 PM PDT 24
Finished Jun 11 03:50:52 PM PDT 24
Peak memory 201836 kb
Host smart-1f0f3610-0ddd-405c-b6fd-9dd955000a55
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833514762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.1833514762
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.1287375483
Short name T368
Test name
Test status
Simulation time 201210455791 ps
CPU time 220.97 seconds
Started Jun 11 03:46:56 PM PDT 24
Finished Jun 11 03:50:38 PM PDT 24
Peak memory 201800 kb
Host smart-2dcd4d91-9ad0-422f-962f-0e5ffb2da7df
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287375483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.1287375483
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.2119591937
Short name T622
Test name
Test status
Simulation time 103517242895 ps
CPU time 501.58 seconds
Started Jun 11 03:47:03 PM PDT 24
Finished Jun 11 03:55:25 PM PDT 24
Peak memory 202100 kb
Host smart-e749cc3e-1c46-4d3d-b66a-b74d43d718d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119591937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.2119591937
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.1262367912
Short name T572
Test name
Test status
Simulation time 43436778932 ps
CPU time 27.9 seconds
Started Jun 11 03:47:03 PM PDT 24
Finished Jun 11 03:47:32 PM PDT 24
Peak memory 201640 kb
Host smart-f7abee01-7a86-409e-98f3-bf1e09037ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262367912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.1262367912
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.3204745417
Short name T126
Test name
Test status
Simulation time 4768870341 ps
CPU time 6.55 seconds
Started Jun 11 03:47:03 PM PDT 24
Finished Jun 11 03:47:10 PM PDT 24
Peak memory 201592 kb
Host smart-8f7a6e85-625e-44db-8adb-02dba53a8480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204745417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.3204745417
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.1063503277
Short name T355
Test name
Test status
Simulation time 6111891867 ps
CPU time 7.72 seconds
Started Jun 11 03:46:56 PM PDT 24
Finished Jun 11 03:47:05 PM PDT 24
Peak memory 201528 kb
Host smart-ccd0021a-bf93-49fa-a47a-dadceb558c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063503277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.1063503277
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.3816541106
Short name T532
Test name
Test status
Simulation time 1297262540 ps
CPU time 1.38 seconds
Started Jun 11 03:47:03 PM PDT 24
Finished Jun 11 03:47:05 PM PDT 24
Peak memory 201532 kb
Host smart-bae4664a-3127-4f9e-b035-c6a3ff823a59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816541106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.3816541106
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.2269504751
Short name T662
Test name
Test status
Simulation time 33366726743 ps
CPU time 26.49 seconds
Started Jun 11 03:47:04 PM PDT 24
Finished Jun 11 03:47:31 PM PDT 24
Peak memory 211200 kb
Host smart-97a9e066-a8f5-449e-8e33-22fb69a04528
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269504751 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.2269504751
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.1173716679
Short name T384
Test name
Test status
Simulation time 491500608 ps
CPU time 0.88 seconds
Started Jun 11 03:47:11 PM PDT 24
Finished Jun 11 03:47:12 PM PDT 24
Peak memory 201464 kb
Host smart-4fc29cbe-e75f-4dd1-b0ec-cac764f43f2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173716679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.1173716679
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.563308537
Short name T596
Test name
Test status
Simulation time 352812627838 ps
CPU time 437.07 seconds
Started Jun 11 03:47:20 PM PDT 24
Finished Jun 11 03:54:38 PM PDT 24
Peak memory 201896 kb
Host smart-6e1aa9ad-038b-4283-a63f-e8294d4dfd4c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563308537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gati
ng.563308537
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.3227812057
Short name T789
Test name
Test status
Simulation time 372274503763 ps
CPU time 201.52 seconds
Started Jun 11 03:47:12 PM PDT 24
Finished Jun 11 03:50:35 PM PDT 24
Peak memory 201824 kb
Host smart-813cdbf7-afe6-43c1-98c8-981b2d8148c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227812057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.3227812057
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.2929502308
Short name T702
Test name
Test status
Simulation time 329880533049 ps
CPU time 199.59 seconds
Started Jun 11 03:47:12 PM PDT 24
Finished Jun 11 03:50:32 PM PDT 24
Peak memory 201796 kb
Host smart-30f460d3-4451-4963-a986-d1a8decd583b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929502308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.2929502308
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.2710422525
Short name T585
Test name
Test status
Simulation time 495829341423 ps
CPU time 194.53 seconds
Started Jun 11 03:47:20 PM PDT 24
Finished Jun 11 03:50:36 PM PDT 24
Peak memory 201816 kb
Host smart-9917bea5-1e42-4596-954d-59daca95a7e9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710422525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.2710422525
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.1328803379
Short name T303
Test name
Test status
Simulation time 329968531978 ps
CPU time 103.01 seconds
Started Jun 11 03:47:11 PM PDT 24
Finished Jun 11 03:48:55 PM PDT 24
Peak memory 201836 kb
Host smart-4b154797-db1f-45e7-8511-935c55d19a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328803379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.1328803379
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.2860144248
Short name T630
Test name
Test status
Simulation time 164947003600 ps
CPU time 92.66 seconds
Started Jun 11 03:47:11 PM PDT 24
Finished Jun 11 03:48:44 PM PDT 24
Peak memory 201780 kb
Host smart-ee95c704-e30b-4e78-af31-987639887ae6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860144248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.2860144248
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.172530291
Short name T269
Test name
Test status
Simulation time 179366601778 ps
CPU time 453.57 seconds
Started Jun 11 03:47:12 PM PDT 24
Finished Jun 11 03:54:46 PM PDT 24
Peak memory 202044 kb
Host smart-2b3a6972-4692-4085-a7d9-a84af6cd4505
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172530291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_
wakeup.172530291
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.3216706297
Short name T421
Test name
Test status
Simulation time 191779734155 ps
CPU time 114.85 seconds
Started Jun 11 03:47:11 PM PDT 24
Finished Jun 11 03:49:07 PM PDT 24
Peak memory 201796 kb
Host smart-a8712953-4509-4525-9d9b-538f781ff255
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216706297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.3216706297
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.2805445806
Short name T565
Test name
Test status
Simulation time 94886272089 ps
CPU time 309.56 seconds
Started Jun 11 03:47:13 PM PDT 24
Finished Jun 11 03:52:23 PM PDT 24
Peak memory 202076 kb
Host smart-5654fff7-609b-4246-b8eb-fc0b9e0701d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805445806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.2805445806
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.3801141566
Short name T704
Test name
Test status
Simulation time 33350234497 ps
CPU time 42.2 seconds
Started Jun 11 03:47:12 PM PDT 24
Finished Jun 11 03:47:55 PM PDT 24
Peak memory 201632 kb
Host smart-52fe2b4a-24ea-4d3c-bb63-20ddaa32d708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801141566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.3801141566
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.3424854170
Short name T181
Test name
Test status
Simulation time 3901816646 ps
CPU time 3.25 seconds
Started Jun 11 03:47:20 PM PDT 24
Finished Jun 11 03:47:24 PM PDT 24
Peak memory 201636 kb
Host smart-963390d8-fcd4-4ba1-a08e-ebb863fbaa87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424854170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.3424854170
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.4143403413
Short name T28
Test name
Test status
Simulation time 5803593851 ps
CPU time 13.55 seconds
Started Jun 11 03:47:10 PM PDT 24
Finished Jun 11 03:47:24 PM PDT 24
Peak memory 201640 kb
Host smart-87f6b5a5-ce65-4b2f-a56d-2630dbabc12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143403413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.4143403413
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.2717744084
Short name T577
Test name
Test status
Simulation time 336575728457 ps
CPU time 198.24 seconds
Started Jun 11 03:47:11 PM PDT 24
Finished Jun 11 03:50:30 PM PDT 24
Peak memory 201812 kb
Host smart-e38d0c9b-bec7-4565-87fa-be6bed6355ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717744084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.2717744084
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.1058656926
Short name T625
Test name
Test status
Simulation time 26243218343 ps
CPU time 34.12 seconds
Started Jun 11 03:47:11 PM PDT 24
Finished Jun 11 03:47:46 PM PDT 24
Peak memory 210532 kb
Host smart-ee45fa1e-3f0b-44cf-8e01-d106770caa11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058656926 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.1058656926
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.4092165052
Short name T187
Test name
Test status
Simulation time 534169598 ps
CPU time 0.96 seconds
Started Jun 11 03:47:29 PM PDT 24
Finished Jun 11 03:47:31 PM PDT 24
Peak memory 201440 kb
Host smart-c20a4379-8e37-478d-b1a3-1bd26ccdd9ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092165052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.4092165052
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.1206599653
Short name T659
Test name
Test status
Simulation time 176418172404 ps
CPU time 111.54 seconds
Started Jun 11 03:47:20 PM PDT 24
Finished Jun 11 03:49:13 PM PDT 24
Peak memory 201808 kb
Host smart-d7f60b3d-aa8d-42fa-aa31-300fe0379783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206599653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.1206599653
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.793938425
Short name T230
Test name
Test status
Simulation time 330421441601 ps
CPU time 462.87 seconds
Started Jun 11 03:47:23 PM PDT 24
Finished Jun 11 03:55:07 PM PDT 24
Peak memory 201820 kb
Host smart-f2c0df8b-e376-4bb4-81ca-ba0eb4a4e605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793938425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.793938425
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.3158988832
Short name T490
Test name
Test status
Simulation time 328745293062 ps
CPU time 519.67 seconds
Started Jun 11 03:47:20 PM PDT 24
Finished Jun 11 03:56:01 PM PDT 24
Peak memory 201848 kb
Host smart-40260406-d27f-48d6-bfe6-5d1475f37d1d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158988832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.3158988832
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.3965097922
Short name T335
Test name
Test status
Simulation time 156181789172 ps
CPU time 175.17 seconds
Started Jun 11 03:47:14 PM PDT 24
Finished Jun 11 03:50:10 PM PDT 24
Peak memory 201912 kb
Host smart-e5ce4a8c-4f82-46f1-ad06-aface2fda7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965097922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.3965097922
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.977432822
Short name T534
Test name
Test status
Simulation time 161619195859 ps
CPU time 389.82 seconds
Started Jun 11 03:47:23 PM PDT 24
Finished Jun 11 03:53:54 PM PDT 24
Peak memory 201812 kb
Host smart-f49d51f5-c233-40ee-af5c-90e2fea07d97
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=977432822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fixe
d.977432822
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.3402316141
Short name T284
Test name
Test status
Simulation time 539712256360 ps
CPU time 596 seconds
Started Jun 11 03:47:22 PM PDT 24
Finished Jun 11 03:57:19 PM PDT 24
Peak memory 201796 kb
Host smart-ae994dc7-e2cb-4388-8462-02c801212ffb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402316141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.3402316141
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.2847526708
Short name T638
Test name
Test status
Simulation time 396115873372 ps
CPU time 281.99 seconds
Started Jun 11 03:47:21 PM PDT 24
Finished Jun 11 03:52:04 PM PDT 24
Peak memory 201840 kb
Host smart-c1d0bbfe-35f8-4918-b44d-b7791b3190f2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847526708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.2847526708
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.4280826534
Short name T730
Test name
Test status
Simulation time 79036143567 ps
CPU time 409.31 seconds
Started Jun 11 03:47:29 PM PDT 24
Finished Jun 11 03:54:20 PM PDT 24
Peak memory 202108 kb
Host smart-ceca403d-df8b-4743-be02-8a5d39eb42ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280826534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.4280826534
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.879020363
Short name T189
Test name
Test status
Simulation time 30775281129 ps
CPU time 75.73 seconds
Started Jun 11 03:47:24 PM PDT 24
Finished Jun 11 03:48:41 PM PDT 24
Peak memory 201632 kb
Host smart-3fde8e8b-fd5c-45b5-af67-b60d6c43764e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879020363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.879020363
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.1953689910
Short name T541
Test name
Test status
Simulation time 5328327668 ps
CPU time 3.71 seconds
Started Jun 11 03:47:25 PM PDT 24
Finished Jun 11 03:47:30 PM PDT 24
Peak memory 201628 kb
Host smart-ee7ceb16-160e-4955-9394-4848da1f967d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953689910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.1953689910
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.2273247823
Short name T470
Test name
Test status
Simulation time 5981488036 ps
CPU time 4.9 seconds
Started Jun 11 03:47:12 PM PDT 24
Finished Jun 11 03:47:18 PM PDT 24
Peak memory 201632 kb
Host smart-d33a1782-c241-4c9f-bdba-1568ae8c466c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273247823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.2273247823
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.3522358143
Short name T571
Test name
Test status
Simulation time 517143658118 ps
CPU time 302.07 seconds
Started Jun 11 03:47:28 PM PDT 24
Finished Jun 11 03:52:31 PM PDT 24
Peak memory 201832 kb
Host smart-7230aef3-e434-4859-aaf1-317e15bcfba6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522358143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.3522358143
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.4227686083
Short name T238
Test name
Test status
Simulation time 474025275672 ps
CPU time 221.59 seconds
Started Jun 11 03:47:29 PM PDT 24
Finished Jun 11 03:51:12 PM PDT 24
Peak memory 217624 kb
Host smart-36837d00-a247-459f-979e-5d77bd3d8eb8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227686083 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.4227686083
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.664800815
Short name T743
Test name
Test status
Simulation time 489554417 ps
CPU time 1.21 seconds
Started Jun 11 03:44:28 PM PDT 24
Finished Jun 11 03:44:30 PM PDT 24
Peak memory 201532 kb
Host smart-d6dbde0b-1f56-4cec-8c62-fd070e2b887c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664800815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.664800815
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.2527247034
Short name T271
Test name
Test status
Simulation time 540214322259 ps
CPU time 487.78 seconds
Started Jun 11 03:44:27 PM PDT 24
Finished Jun 11 03:52:36 PM PDT 24
Peak memory 201816 kb
Host smart-acf20f82-86ed-44fa-b3ac-c63c8b9044c7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527247034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.2527247034
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.2800049833
Short name T188
Test name
Test status
Simulation time 333261741805 ps
CPU time 213.13 seconds
Started Jun 11 03:44:27 PM PDT 24
Finished Jun 11 03:48:01 PM PDT 24
Peak memory 201808 kb
Host smart-bf5efee3-e357-4961-bd74-267ffd302ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800049833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.2800049833
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.3695061170
Short name T575
Test name
Test status
Simulation time 492637122794 ps
CPU time 1215.12 seconds
Started Jun 11 03:44:28 PM PDT 24
Finished Jun 11 04:04:45 PM PDT 24
Peak memory 201792 kb
Host smart-a4420438-b69c-4b39-916d-8ce4cd7109cc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695061170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.3695061170
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.1944742131
Short name T131
Test name
Test status
Simulation time 489417676057 ps
CPU time 287.81 seconds
Started Jun 11 03:44:27 PM PDT 24
Finished Jun 11 03:49:17 PM PDT 24
Peak memory 201916 kb
Host smart-d48a0bd6-0d96-4bae-b288-e0d2c75daf82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944742131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.1944742131
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.3031626612
Short name T740
Test name
Test status
Simulation time 328834832808 ps
CPU time 387.64 seconds
Started Jun 11 03:44:29 PM PDT 24
Finished Jun 11 03:50:58 PM PDT 24
Peak memory 201832 kb
Host smart-f25399a1-b477-452f-934a-62ed579c3c1b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031626612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.3031626612
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.2287732954
Short name T178
Test name
Test status
Simulation time 367606872579 ps
CPU time 215.37 seconds
Started Jun 11 03:44:29 PM PDT 24
Finished Jun 11 03:48:05 PM PDT 24
Peak memory 201888 kb
Host smart-04a6b2bd-a2d0-4b1a-8f43-be8d7acfc43e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287732954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.2287732954
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.1426106427
Short name T139
Test name
Test status
Simulation time 209519982174 ps
CPU time 37.02 seconds
Started Jun 11 03:44:27 PM PDT 24
Finished Jun 11 03:45:05 PM PDT 24
Peak memory 201916 kb
Host smart-91638ad0-d8cf-469b-9a62-6be6f166e8d8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426106427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.1426106427
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.3741178422
Short name T722
Test name
Test status
Simulation time 126097434455 ps
CPU time 650.76 seconds
Started Jun 11 03:44:28 PM PDT 24
Finished Jun 11 03:55:20 PM PDT 24
Peak memory 202200 kb
Host smart-755c5909-0def-4861-b96f-9cb8042daf53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741178422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.3741178422
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.3682403883
Short name T548
Test name
Test status
Simulation time 29525131098 ps
CPU time 33.85 seconds
Started Jun 11 03:44:27 PM PDT 24
Finished Jun 11 03:45:02 PM PDT 24
Peak memory 201620 kb
Host smart-007b90bc-7f59-4986-a4e6-0b12bdcbee30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682403883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.3682403883
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.1358671425
Short name T716
Test name
Test status
Simulation time 2637459312 ps
CPU time 2.22 seconds
Started Jun 11 03:44:28 PM PDT 24
Finished Jun 11 03:44:32 PM PDT 24
Peak memory 201644 kb
Host smart-2bc3fda3-3b03-4b28-8e27-fa1fe730da99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358671425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.1358671425
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.3806765677
Short name T15
Test name
Test status
Simulation time 7550120466 ps
CPU time 11.62 seconds
Started Jun 11 03:44:27 PM PDT 24
Finished Jun 11 03:44:40 PM PDT 24
Peak memory 217316 kb
Host smart-f756405b-36e5-466a-b5a2-affdfb3233fb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806765677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.3806765677
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.593114136
Short name T363
Test name
Test status
Simulation time 5858973921 ps
CPU time 15.16 seconds
Started Jun 11 03:44:27 PM PDT 24
Finished Jun 11 03:44:43 PM PDT 24
Peak memory 201576 kb
Host smart-d505ae1c-c102-4fb3-8c7e-c210afa2e668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593114136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.593114136
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.552960969
Short name T195
Test name
Test status
Simulation time 130200956956 ps
CPU time 629.15 seconds
Started Jun 11 03:44:28 PM PDT 24
Finished Jun 11 03:54:58 PM PDT 24
Peak memory 202140 kb
Host smart-5b1d504e-2e4d-4864-b1f8-c8341ea1c628
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552960969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.552960969
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.1722510916
Short name T483
Test name
Test status
Simulation time 356806180 ps
CPU time 1.46 seconds
Started Jun 11 03:47:37 PM PDT 24
Finished Jun 11 03:47:39 PM PDT 24
Peak memory 201520 kb
Host smart-8105d876-3f29-40af-9a1d-9b5da6af1471
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722510916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.1722510916
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.3092621548
Short name T176
Test name
Test status
Simulation time 163509984985 ps
CPU time 384.67 seconds
Started Jun 11 03:47:38 PM PDT 24
Finished Jun 11 03:54:03 PM PDT 24
Peak memory 201816 kb
Host smart-b4074e81-1368-4dc1-b28d-3d2f9c710ec6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092621548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.3092621548
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.2614983072
Short name T287
Test name
Test status
Simulation time 507176071202 ps
CPU time 1311.39 seconds
Started Jun 11 03:47:38 PM PDT 24
Finished Jun 11 04:09:31 PM PDT 24
Peak memory 201808 kb
Host smart-50a4da5d-fc5e-4079-8c53-b6414cb2d681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614983072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.2614983072
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.2968581536
Short name T494
Test name
Test status
Simulation time 165997847205 ps
CPU time 106.76 seconds
Started Jun 11 03:47:28 PM PDT 24
Finished Jun 11 03:49:16 PM PDT 24
Peak memory 201804 kb
Host smart-b828d479-4df2-45cc-bb8e-da0debe63eac
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968581536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.2968581536
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.1714155422
Short name T580
Test name
Test status
Simulation time 336037676891 ps
CPU time 185.48 seconds
Started Jun 11 03:47:30 PM PDT 24
Finished Jun 11 03:50:36 PM PDT 24
Peak memory 201832 kb
Host smart-ce75c46e-87f0-4b5c-83da-40e10c5d22e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714155422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.1714155422
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.1051549225
Short name T435
Test name
Test status
Simulation time 494643161127 ps
CPU time 266.52 seconds
Started Jun 11 03:47:29 PM PDT 24
Finished Jun 11 03:51:57 PM PDT 24
Peak memory 201872 kb
Host smart-8ba9b228-aad6-438d-a63a-e2a7d267de9d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051549225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.1051549225
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.3143647716
Short name T594
Test name
Test status
Simulation time 204330184910 ps
CPU time 169.82 seconds
Started Jun 11 03:47:33 PM PDT 24
Finished Jun 11 03:50:24 PM PDT 24
Peak memory 201808 kb
Host smart-f7743695-9e8e-447c-bc61-9a4d96928203
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143647716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.3143647716
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.4272183151
Short name T94
Test name
Test status
Simulation time 64937519042 ps
CPU time 291.24 seconds
Started Jun 11 03:47:38 PM PDT 24
Finished Jun 11 03:52:31 PM PDT 24
Peak memory 202000 kb
Host smart-7b17eeb0-93e4-41c3-93cc-94f30277887f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272183151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.4272183151
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.959770390
Short name T792
Test name
Test status
Simulation time 31745228663 ps
CPU time 35.69 seconds
Started Jun 11 03:47:37 PM PDT 24
Finished Jun 11 03:48:14 PM PDT 24
Peak memory 201800 kb
Host smart-e5295d4e-e386-45e6-a650-1572356f5a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959770390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.959770390
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.3021178042
Short name T464
Test name
Test status
Simulation time 4205812900 ps
CPU time 3.14 seconds
Started Jun 11 03:47:39 PM PDT 24
Finished Jun 11 03:47:43 PM PDT 24
Peak memory 201628 kb
Host smart-b84f3c83-468e-445e-a1a5-cdcd7cde72c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021178042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.3021178042
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.2030363951
Short name T87
Test name
Test status
Simulation time 6034043307 ps
CPU time 4.3 seconds
Started Jun 11 03:47:31 PM PDT 24
Finished Jun 11 03:47:36 PM PDT 24
Peak memory 201652 kb
Host smart-887b6f7c-2982-4e0d-a286-0b415e6e16d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030363951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.2030363951
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.1959965274
Short name T770
Test name
Test status
Simulation time 674098173249 ps
CPU time 522.37 seconds
Started Jun 11 03:47:36 PM PDT 24
Finished Jun 11 03:56:19 PM PDT 24
Peak memory 202092 kb
Host smart-f648d70a-7a0a-4d98-9928-f23eebebffda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959965274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.1959965274
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.165285638
Short name T418
Test name
Test status
Simulation time 518260062 ps
CPU time 1.84 seconds
Started Jun 11 03:47:53 PM PDT 24
Finished Jun 11 03:47:56 PM PDT 24
Peak memory 201492 kb
Host smart-b440da4d-e337-4b57-a39c-0e3d83dc98ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165285638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.165285638
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.1016242823
Short name T517
Test name
Test status
Simulation time 321006976930 ps
CPU time 367.53 seconds
Started Jun 11 03:47:45 PM PDT 24
Finished Jun 11 03:53:53 PM PDT 24
Peak memory 201800 kb
Host smart-77c40458-bbb2-4cbe-8256-6816f59e5f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016242823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.1016242823
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.2746240453
Short name T513
Test name
Test status
Simulation time 486600033114 ps
CPU time 304.79 seconds
Started Jun 11 03:47:44 PM PDT 24
Finished Jun 11 03:52:50 PM PDT 24
Peak memory 201804 kb
Host smart-2e127389-5442-42df-a6a3-6a0f46ad2abd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746240453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.2746240453
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.1916951009
Short name T696
Test name
Test status
Simulation time 162755304237 ps
CPU time 207.36 seconds
Started Jun 11 03:47:43 PM PDT 24
Finished Jun 11 03:51:11 PM PDT 24
Peak memory 201904 kb
Host smart-7c29b26d-6a49-4c0f-bec8-329180f7901e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916951009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.1916951009
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.2483355726
Short name T700
Test name
Test status
Simulation time 320563218369 ps
CPU time 699.12 seconds
Started Jun 11 03:47:45 PM PDT 24
Finished Jun 11 03:59:26 PM PDT 24
Peak memory 201776 kb
Host smart-f0002aaf-10cf-4b04-b69f-db79c2fac2cc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483355726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.2483355726
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.1201900010
Short name T520
Test name
Test status
Simulation time 202284304128 ps
CPU time 449.45 seconds
Started Jun 11 03:47:45 PM PDT 24
Finished Jun 11 03:55:15 PM PDT 24
Peak memory 202044 kb
Host smart-1d1a22bf-8128-4450-ab97-998a00a091b1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201900010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.1201900010
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.557940306
Short name T359
Test name
Test status
Simulation time 592292483748 ps
CPU time 667.45 seconds
Started Jun 11 03:47:46 PM PDT 24
Finished Jun 11 03:58:54 PM PDT 24
Peak memory 201816 kb
Host smart-4876d2c7-a0b0-4e28-a359-360ad2db2b00
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557940306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
adc_ctrl_filters_wakeup_fixed.557940306
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.185859677
Short name T773
Test name
Test status
Simulation time 105159200139 ps
CPU time 443.91 seconds
Started Jun 11 03:47:44 PM PDT 24
Finished Jun 11 03:55:09 PM PDT 24
Peak memory 202112 kb
Host smart-f81d1607-63dc-433f-a212-4c5139080fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185859677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.185859677
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.168827142
Short name T492
Test name
Test status
Simulation time 36594881969 ps
CPU time 11.71 seconds
Started Jun 11 03:47:47 PM PDT 24
Finished Jun 11 03:47:59 PM PDT 24
Peak memory 201640 kb
Host smart-dd6f9038-8fc9-407e-8a5d-39c1eafca48e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168827142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.168827142
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.3883393287
Short name T626
Test name
Test status
Simulation time 4606255984 ps
CPU time 11.73 seconds
Started Jun 11 03:47:46 PM PDT 24
Finished Jun 11 03:47:58 PM PDT 24
Peak memory 201624 kb
Host smart-8b4db40b-f8fc-419b-b9fd-502082c74c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883393287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.3883393287
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.2277504579
Short name T184
Test name
Test status
Simulation time 5897700501 ps
CPU time 8.78 seconds
Started Jun 11 03:47:46 PM PDT 24
Finished Jun 11 03:47:55 PM PDT 24
Peak memory 201524 kb
Host smart-d471f218-6161-428c-a9f8-cd975785090b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277504579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.2277504579
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.4233986546
Short name T645
Test name
Test status
Simulation time 308243163502 ps
CPU time 392.14 seconds
Started Jun 11 03:47:53 PM PDT 24
Finished Jun 11 03:54:26 PM PDT 24
Peak memory 210332 kb
Host smart-db6cf8b0-2b93-4329-85f6-d1434736f75d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233986546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.4233986546
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.3905040153
Short name T775
Test name
Test status
Simulation time 398949985 ps
CPU time 1.05 seconds
Started Jun 11 03:48:11 PM PDT 24
Finished Jun 11 03:48:13 PM PDT 24
Peak memory 201492 kb
Host smart-8040128d-575d-45c2-adef-e67c65c2cc47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905040153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.3905040153
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.3908989168
Short name T602
Test name
Test status
Simulation time 163239818612 ps
CPU time 362.64 seconds
Started Jun 11 03:48:01 PM PDT 24
Finished Jun 11 03:54:05 PM PDT 24
Peak memory 201828 kb
Host smart-548f2ca6-b2cb-4344-9c4b-7e7204d197f9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908989168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.3908989168
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.1285671416
Short name T294
Test name
Test status
Simulation time 357410690128 ps
CPU time 398.18 seconds
Started Jun 11 03:48:03 PM PDT 24
Finished Jun 11 03:54:43 PM PDT 24
Peak memory 201780 kb
Host smart-79446b2a-d18a-4bbe-9f49-9dc075c567f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285671416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.1285671416
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.785162275
Short name T169
Test name
Test status
Simulation time 332077844945 ps
CPU time 86.03 seconds
Started Jun 11 03:48:03 PM PDT 24
Finished Jun 11 03:49:31 PM PDT 24
Peak memory 201796 kb
Host smart-d8f5c5fb-f8bd-4ece-8986-40eed0a9a97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785162275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.785162275
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.1148953099
Short name T791
Test name
Test status
Simulation time 158230676444 ps
CPU time 339.1 seconds
Started Jun 11 03:48:05 PM PDT 24
Finished Jun 11 03:53:45 PM PDT 24
Peak memory 201752 kb
Host smart-d0d086a9-2559-46dd-9f53-fe15148e442a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148953099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.1148953099
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.3963400076
Short name T503
Test name
Test status
Simulation time 325422561776 ps
CPU time 120.03 seconds
Started Jun 11 03:47:55 PM PDT 24
Finished Jun 11 03:49:56 PM PDT 24
Peak memory 201692 kb
Host smart-2fb6c419-3307-4d2a-8191-8e2f114e27c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963400076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.3963400076
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.2241205602
Short name T156
Test name
Test status
Simulation time 327820445543 ps
CPU time 186.82 seconds
Started Jun 11 03:47:55 PM PDT 24
Finished Jun 11 03:51:03 PM PDT 24
Peak memory 201760 kb
Host smart-1b6426a7-52ee-4c45-bd51-a26271a187ab
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241205602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.2241205602
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.2344130510
Short name T170
Test name
Test status
Simulation time 343303646357 ps
CPU time 188.81 seconds
Started Jun 11 03:48:04 PM PDT 24
Finished Jun 11 03:51:14 PM PDT 24
Peak memory 201836 kb
Host smart-45f4ccf6-6b51-4d0d-8049-6c47c46e0eb1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344130510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.2344130510
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.2313005509
Short name T86
Test name
Test status
Simulation time 618431834455 ps
CPU time 384.65 seconds
Started Jun 11 03:48:03 PM PDT 24
Finished Jun 11 03:54:29 PM PDT 24
Peak memory 201884 kb
Host smart-576b57f4-b1ab-4a46-a1d2-7a1c4029e694
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313005509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.2313005509
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.892637990
Short name T708
Test name
Test status
Simulation time 116700277171 ps
CPU time 643.75 seconds
Started Jun 11 03:48:03 PM PDT 24
Finished Jun 11 03:58:48 PM PDT 24
Peak memory 202188 kb
Host smart-9830e74b-e00a-407c-873f-99e2c5388535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892637990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.892637990
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.2404803519
Short name T717
Test name
Test status
Simulation time 28089202193 ps
CPU time 17.07 seconds
Started Jun 11 03:48:02 PM PDT 24
Finished Jun 11 03:48:20 PM PDT 24
Peak memory 201628 kb
Host smart-43989f01-e025-46fb-a38f-ba42089fd275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404803519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.2404803519
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.1295459483
Short name T718
Test name
Test status
Simulation time 3330727434 ps
CPU time 2.91 seconds
Started Jun 11 03:48:03 PM PDT 24
Finished Jun 11 03:48:08 PM PDT 24
Peak memory 201648 kb
Host smart-acdf66d6-3291-4e2a-bec3-959f4e19b10d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295459483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.1295459483
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.793599004
Short name T684
Test name
Test status
Simulation time 5737832006 ps
CPU time 13.65 seconds
Started Jun 11 03:47:54 PM PDT 24
Finished Jun 11 03:48:08 PM PDT 24
Peak memory 201636 kb
Host smart-1aa6e937-46c0-4714-8166-caee5b9b44b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793599004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.793599004
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.1678531142
Short name T705
Test name
Test status
Simulation time 47748816207 ps
CPU time 26.96 seconds
Started Jun 11 03:48:13 PM PDT 24
Finished Jun 11 03:48:41 PM PDT 24
Peak memory 201628 kb
Host smart-c8d4ccf5-f86d-48ab-b4a9-2c474d74f957
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678531142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.1678531142
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.2515921883
Short name T72
Test name
Test status
Simulation time 539504301 ps
CPU time 1.25 seconds
Started Jun 11 03:48:18 PM PDT 24
Finished Jun 11 03:48:21 PM PDT 24
Peak memory 201512 kb
Host smart-908b84ff-abfa-41d0-ac89-534ecd3b0069
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515921883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.2515921883
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.4264815652
Short name T741
Test name
Test status
Simulation time 186412827402 ps
CPU time 59.44 seconds
Started Jun 11 03:48:10 PM PDT 24
Finished Jun 11 03:49:10 PM PDT 24
Peak memory 201860 kb
Host smart-f1b91217-775d-4a33-8f1b-577f2c45b0f0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264815652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.4264815652
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.1382047710
Short name T699
Test name
Test status
Simulation time 391913708198 ps
CPU time 440.61 seconds
Started Jun 11 03:48:18 PM PDT 24
Finished Jun 11 03:55:40 PM PDT 24
Peak memory 201808 kb
Host smart-84777764-a6c9-4ded-afc5-c446e435099f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382047710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.1382047710
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.1924296886
Short name T683
Test name
Test status
Simulation time 163244365273 ps
CPU time 110.86 seconds
Started Jun 11 03:48:10 PM PDT 24
Finished Jun 11 03:50:02 PM PDT 24
Peak memory 201792 kb
Host smart-d70ec844-7df3-4f4b-8432-41d6643c832e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924296886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.1924296886
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.2871517306
Short name T32
Test name
Test status
Simulation time 317776357410 ps
CPU time 757.43 seconds
Started Jun 11 03:48:12 PM PDT 24
Finished Jun 11 04:00:50 PM PDT 24
Peak memory 201820 kb
Host smart-dae3b169-f2e1-429f-91b4-43a7a47cbf77
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871517306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.2871517306
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.835624749
Short name T165
Test name
Test status
Simulation time 484655063967 ps
CPU time 137.82 seconds
Started Jun 11 03:48:14 PM PDT 24
Finished Jun 11 03:50:32 PM PDT 24
Peak memory 201804 kb
Host smart-730e5d83-eccb-43bf-b552-7543587f1015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835624749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.835624749
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.412934000
Short name T349
Test name
Test status
Simulation time 325221265280 ps
CPU time 385.01 seconds
Started Jun 11 03:48:13 PM PDT 24
Finished Jun 11 03:54:39 PM PDT 24
Peak memory 201812 kb
Host smart-b580dc1e-656a-4097-8426-2e3a0c1d45ba
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=412934000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fixe
d.412934000
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.3664525672
Short name T39
Test name
Test status
Simulation time 363126973344 ps
CPU time 89.64 seconds
Started Jun 11 03:48:11 PM PDT 24
Finished Jun 11 03:49:41 PM PDT 24
Peak memory 201812 kb
Host smart-37f5828b-d6a9-437d-9195-7c9d55c58787
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664525672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.3664525672
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.1395943611
Short name T694
Test name
Test status
Simulation time 600632494199 ps
CPU time 1618.1 seconds
Started Jun 11 03:48:12 PM PDT 24
Finished Jun 11 04:15:11 PM PDT 24
Peak memory 201812 kb
Host smart-4bc6d3d0-8b1f-428b-94bd-050e78f05b07
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395943611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.1395943611
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.906284552
Short name T540
Test name
Test status
Simulation time 80913233327 ps
CPU time 319.11 seconds
Started Jun 11 03:48:19 PM PDT 24
Finished Jun 11 03:53:40 PM PDT 24
Peak memory 202156 kb
Host smart-2c2a4d7d-f9a9-416d-bb5f-5ad507fb6fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906284552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.906284552
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.2451734659
Short name T555
Test name
Test status
Simulation time 29691108251 ps
CPU time 15.67 seconds
Started Jun 11 03:48:18 PM PDT 24
Finished Jun 11 03:48:36 PM PDT 24
Peak memory 201604 kb
Host smart-4e0cb236-3507-445c-b57d-3e6450d8062f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451734659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.2451734659
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.1807746298
Short name T440
Test name
Test status
Simulation time 3552821309 ps
CPU time 8.91 seconds
Started Jun 11 03:48:18 PM PDT 24
Finished Jun 11 03:48:28 PM PDT 24
Peak memory 201612 kb
Host smart-46df8c19-1497-474b-8698-efbde835156f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807746298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.1807746298
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.4202767467
Short name T669
Test name
Test status
Simulation time 5888416221 ps
CPU time 16.14 seconds
Started Jun 11 03:48:11 PM PDT 24
Finished Jun 11 03:48:28 PM PDT 24
Peak memory 201632 kb
Host smart-30598577-ad03-4176-9f76-07fa2583a078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202767467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.4202767467
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.1821480780
Short name T525
Test name
Test status
Simulation time 124297685548 ps
CPU time 493.49 seconds
Started Jun 11 03:48:18 PM PDT 24
Finished Jun 11 03:56:33 PM PDT 24
Peak memory 202076 kb
Host smart-aff3dc10-439d-4314-afb7-da7fd2795c90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821480780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.1821480780
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.1990743042
Short name T31
Test name
Test status
Simulation time 228012945742 ps
CPU time 109.57 seconds
Started Jun 11 03:48:19 PM PDT 24
Finished Jun 11 03:50:11 PM PDT 24
Peak memory 210432 kb
Host smart-74453551-b7e2-4af7-af48-f010482d203a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990743042 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.1990743042
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.128751164
Short name T443
Test name
Test status
Simulation time 356535609 ps
CPU time 1.01 seconds
Started Jun 11 03:48:33 PM PDT 24
Finished Jun 11 03:48:35 PM PDT 24
Peak memory 201428 kb
Host smart-572a95d8-1625-403a-b6af-7cd454b080c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128751164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.128751164
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.3471866907
Short name T231
Test name
Test status
Simulation time 324045742062 ps
CPU time 395.7 seconds
Started Jun 11 03:48:24 PM PDT 24
Finished Jun 11 03:55:00 PM PDT 24
Peak memory 201844 kb
Host smart-698c9a32-9514-472d-9e75-23c6c7694425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471866907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.3471866907
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.3679398505
Short name T570
Test name
Test status
Simulation time 489199153474 ps
CPU time 1288.03 seconds
Started Jun 11 03:48:26 PM PDT 24
Finished Jun 11 04:09:55 PM PDT 24
Peak memory 201736 kb
Host smart-296a8fce-5505-41cb-9d4c-8166bad40361
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679398505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.3679398505
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.2580762743
Short name T154
Test name
Test status
Simulation time 323085411146 ps
CPU time 104.51 seconds
Started Jun 11 03:48:27 PM PDT 24
Finished Jun 11 03:50:12 PM PDT 24
Peak memory 201824 kb
Host smart-73cfcd6a-6abc-4baf-ac22-73d5b532697c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580762743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.2580762743
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.1358232979
Short name T774
Test name
Test status
Simulation time 487942351267 ps
CPU time 125.53 seconds
Started Jun 11 03:48:26 PM PDT 24
Finished Jun 11 03:50:32 PM PDT 24
Peak memory 201768 kb
Host smart-f5a65b5e-dc79-4c22-8676-79662ac23397
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358232979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.1358232979
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.3705475348
Short name T462
Test name
Test status
Simulation time 184162677387 ps
CPU time 165.38 seconds
Started Jun 11 03:48:25 PM PDT 24
Finished Jun 11 03:51:12 PM PDT 24
Peak memory 201732 kb
Host smart-855fafb1-0d69-4d81-8bbe-7f487f8eeaa8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705475348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.3705475348
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.4068397492
Short name T601
Test name
Test status
Simulation time 600240187731 ps
CPU time 1513.61 seconds
Started Jun 11 03:48:25 PM PDT 24
Finished Jun 11 04:13:40 PM PDT 24
Peak memory 201868 kb
Host smart-dcd01a84-4837-4920-8d85-0545e14f9852
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068397492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.4068397492
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.2235869916
Short name T482
Test name
Test status
Simulation time 81811516994 ps
CPU time 259.97 seconds
Started Jun 11 03:48:25 PM PDT 24
Finished Jun 11 03:52:46 PM PDT 24
Peak memory 202148 kb
Host smart-d3608990-1917-41b1-bd97-c31d2eafd159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235869916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.2235869916
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.837703119
Short name T710
Test name
Test status
Simulation time 31591215798 ps
CPU time 71.53 seconds
Started Jun 11 03:48:26 PM PDT 24
Finished Jun 11 03:49:38 PM PDT 24
Peak memory 201628 kb
Host smart-7aefab3e-049a-4b19-af51-a755b4324b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837703119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.837703119
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.1633434396
Short name T798
Test name
Test status
Simulation time 3532522391 ps
CPU time 2.72 seconds
Started Jun 11 03:48:26 PM PDT 24
Finished Jun 11 03:48:30 PM PDT 24
Peak memory 201636 kb
Host smart-775d1ee7-0e85-47b1-8dcd-56c201e67316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633434396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.1633434396
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.2399837129
Short name T429
Test name
Test status
Simulation time 6109784611 ps
CPU time 8.33 seconds
Started Jun 11 03:48:21 PM PDT 24
Finished Jun 11 03:48:31 PM PDT 24
Peak memory 201652 kb
Host smart-65480290-8eac-4a90-9e71-23990e0af867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399837129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.2399837129
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.2614999277
Short name T310
Test name
Test status
Simulation time 255570834241 ps
CPU time 905.04 seconds
Started Jun 11 03:48:33 PM PDT 24
Finished Jun 11 04:03:39 PM PDT 24
Peak memory 210312 kb
Host smart-706e04c6-3285-4c46-b177-f86fe53b3a61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614999277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.2614999277
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.2135587799
Short name T17
Test name
Test status
Simulation time 248491895129 ps
CPU time 233.79 seconds
Started Jun 11 03:48:34 PM PDT 24
Finished Jun 11 03:52:29 PM PDT 24
Peak memory 210476 kb
Host smart-bc62d3bc-4b8b-47d2-ab69-ff9dc3684a07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135587799 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.2135587799
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.2082228080
Short name T679
Test name
Test status
Simulation time 353176125 ps
CPU time 0.72 seconds
Started Jun 11 03:48:41 PM PDT 24
Finished Jun 11 03:48:43 PM PDT 24
Peak memory 201492 kb
Host smart-6d2a484b-112f-49c4-81e9-28f54dcbc49e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082228080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.2082228080
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.1033941778
Short name T654
Test name
Test status
Simulation time 330236799968 ps
CPU time 430.14 seconds
Started Jun 11 03:48:32 PM PDT 24
Finished Jun 11 03:55:43 PM PDT 24
Peak memory 201784 kb
Host smart-f228f2b3-6fec-4691-9817-e1666926a231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033941778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.1033941778
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.1049665643
Short name T380
Test name
Test status
Simulation time 163808159885 ps
CPU time 64.76 seconds
Started Jun 11 03:48:33 PM PDT 24
Finished Jun 11 03:49:39 PM PDT 24
Peak memory 201760 kb
Host smart-11664a72-750a-4a41-812a-31380e34a4ca
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049665643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.1049665643
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.2538794804
Short name T390
Test name
Test status
Simulation time 164438223073 ps
CPU time 93.43 seconds
Started Jun 11 03:48:34 PM PDT 24
Finished Jun 11 03:50:08 PM PDT 24
Peak memory 201892 kb
Host smart-cba33c14-674d-4de7-8c01-7a7fc7f35542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538794804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.2538794804
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.534357360
Short name T422
Test name
Test status
Simulation time 167820270778 ps
CPU time 162.77 seconds
Started Jun 11 03:48:32 PM PDT 24
Finished Jun 11 03:51:16 PM PDT 24
Peak memory 201828 kb
Host smart-1b1aeafa-a67b-4080-8bfd-22683b72efa7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=534357360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fixe
d.534357360
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.1401413290
Short name T146
Test name
Test status
Simulation time 613705461005 ps
CPU time 345.59 seconds
Started Jun 11 03:48:32 PM PDT 24
Finished Jun 11 03:54:19 PM PDT 24
Peak memory 201740 kb
Host smart-3ca87acf-fcbb-40f1-b23d-953812d40070
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401413290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.1401413290
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.1413413760
Short name T173
Test name
Test status
Simulation time 598183483935 ps
CPU time 1481.53 seconds
Started Jun 11 03:48:35 PM PDT 24
Finished Jun 11 04:13:18 PM PDT 24
Peak memory 201744 kb
Host smart-e7cd2667-0115-4aa3-8f46-6fe88bd72e59
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413413760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.1413413760
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.1671270845
Short name T200
Test name
Test status
Simulation time 101277784832 ps
CPU time 609.44 seconds
Started Jun 11 03:48:40 PM PDT 24
Finished Jun 11 03:58:50 PM PDT 24
Peak memory 202000 kb
Host smart-730b56e6-451f-459c-90f4-25977059d471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671270845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.1671270845
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.205880162
Short name T544
Test name
Test status
Simulation time 29758192980 ps
CPU time 63.76 seconds
Started Jun 11 03:48:33 PM PDT 24
Finished Jun 11 03:49:38 PM PDT 24
Peak memory 201652 kb
Host smart-9f315fb9-cf40-4e9c-ad63-a25b1c329e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205880162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.205880162
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.2076586994
Short name T402
Test name
Test status
Simulation time 4513227477 ps
CPU time 3.45 seconds
Started Jun 11 03:48:33 PM PDT 24
Finished Jun 11 03:48:38 PM PDT 24
Peak memory 201584 kb
Host smart-bcea2cfd-a5b4-41d3-99bd-cff56ff7c4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076586994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.2076586994
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.2103868291
Short name T671
Test name
Test status
Simulation time 5812395646 ps
CPU time 3.09 seconds
Started Jun 11 03:48:35 PM PDT 24
Finished Jun 11 03:48:39 PM PDT 24
Peak memory 201648 kb
Host smart-58cf3d05-6ca1-4797-a050-484eb39ddbc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103868291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.2103868291
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.3616340265
Short name T463
Test name
Test status
Simulation time 176399187426 ps
CPU time 97.37 seconds
Started Jun 11 03:48:40 PM PDT 24
Finished Jun 11 03:50:19 PM PDT 24
Peak memory 201788 kb
Host smart-8190db43-cf4a-4f92-8bdd-84409cb6181a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616340265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.3616340265
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.3094403288
Short name T47
Test name
Test status
Simulation time 40940517535 ps
CPU time 27.51 seconds
Started Jun 11 03:48:39 PM PDT 24
Finished Jun 11 03:49:08 PM PDT 24
Peak memory 210216 kb
Host smart-40923b82-0509-4bfb-a571-c197e8687e1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094403288 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.3094403288
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.3280537453
Short name T383
Test name
Test status
Simulation time 465493927 ps
CPU time 0.88 seconds
Started Jun 11 03:48:48 PM PDT 24
Finished Jun 11 03:48:50 PM PDT 24
Peak memory 201492 kb
Host smart-a6874a7b-cb7d-49c1-8d26-a2059e0866f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280537453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.3280537453
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.679952485
Short name T578
Test name
Test status
Simulation time 341240183605 ps
CPU time 825.69 seconds
Started Jun 11 03:48:39 PM PDT 24
Finished Jun 11 04:02:25 PM PDT 24
Peak memory 201888 kb
Host smart-bff7a613-6d4f-4a13-8ec4-efd64cb50d7f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679952485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gati
ng.679952485
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.2981016126
Short name T417
Test name
Test status
Simulation time 485537479124 ps
CPU time 283.88 seconds
Started Jun 11 03:48:40 PM PDT 24
Finished Jun 11 03:53:25 PM PDT 24
Peak memory 201816 kb
Host smart-4a6ea1d2-39f6-4d6c-a422-b833bf8802bf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981016126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.2981016126
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.2632358483
Short name T488
Test name
Test status
Simulation time 332440443361 ps
CPU time 185.32 seconds
Started Jun 11 03:48:42 PM PDT 24
Finished Jun 11 03:51:48 PM PDT 24
Peak memory 201768 kb
Host smart-a2c9e608-24d1-4f66-9e51-49cc7c11dd0b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632358483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.2632358483
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.311499123
Short name T688
Test name
Test status
Simulation time 615700018967 ps
CPU time 749.69 seconds
Started Jun 11 03:48:42 PM PDT 24
Finished Jun 11 04:01:13 PM PDT 24
Peak memory 201840 kb
Host smart-0b5d358f-d34e-45bf-b4e4-5f1cb5071130
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311499123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_
wakeup.311499123
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.307262841
Short name T597
Test name
Test status
Simulation time 594709430179 ps
CPU time 284.95 seconds
Started Jun 11 03:48:41 PM PDT 24
Finished Jun 11 03:53:27 PM PDT 24
Peak memory 201880 kb
Host smart-c6a4381b-9fc5-420b-83f5-0ace5e1fec0d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307262841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
adc_ctrl_filters_wakeup_fixed.307262841
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.2598695577
Short name T436
Test name
Test status
Simulation time 79788202812 ps
CPU time 335.86 seconds
Started Jun 11 03:48:50 PM PDT 24
Finished Jun 11 03:54:26 PM PDT 24
Peak memory 202180 kb
Host smart-49e436b1-e096-4abf-b955-62771212bceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598695577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.2598695577
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.998621241
Short name T3
Test name
Test status
Simulation time 23079568069 ps
CPU time 28.58 seconds
Started Jun 11 03:48:48 PM PDT 24
Finished Jun 11 03:49:18 PM PDT 24
Peak memory 201628 kb
Host smart-014f83c3-44ee-4bf1-8920-57704c4443b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998621241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.998621241
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.3997391566
Short name T723
Test name
Test status
Simulation time 3513106584 ps
CPU time 2.62 seconds
Started Jun 11 03:48:41 PM PDT 24
Finished Jun 11 03:48:45 PM PDT 24
Peak memory 201544 kb
Host smart-02892437-d746-4401-a4f6-1e77e7079b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997391566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.3997391566
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.2188103949
Short name T686
Test name
Test status
Simulation time 5634090977 ps
CPU time 6.66 seconds
Started Jun 11 03:48:43 PM PDT 24
Finished Jun 11 03:48:51 PM PDT 24
Peak memory 201628 kb
Host smart-f54e4197-7998-41c8-ac9f-0577a16bc095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188103949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.2188103949
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.3499766209
Short name T769
Test name
Test status
Simulation time 369414898855 ps
CPU time 916.01 seconds
Started Jun 11 03:48:49 PM PDT 24
Finished Jun 11 04:04:06 PM PDT 24
Peak memory 201832 kb
Host smart-37b87070-03d6-4353-8254-9ca53931be34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499766209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.3499766209
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.153107635
Short name T500
Test name
Test status
Simulation time 37657885335 ps
CPU time 54.65 seconds
Started Jun 11 03:48:49 PM PDT 24
Finished Jun 11 03:49:44 PM PDT 24
Peak memory 210412 kb
Host smart-49eda912-ecc5-436e-830a-0d730933f540
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153107635 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.153107635
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.4073086782
Short name T73
Test name
Test status
Simulation time 402481555 ps
CPU time 1.45 seconds
Started Jun 11 03:49:04 PM PDT 24
Finished Jun 11 03:49:07 PM PDT 24
Peak memory 201484 kb
Host smart-39dce361-5ac3-413d-a760-d8e9500c03aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073086782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.4073086782
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.1369659172
Short name T246
Test name
Test status
Simulation time 654624616687 ps
CPU time 281.85 seconds
Started Jun 11 03:48:56 PM PDT 24
Finished Jun 11 03:53:39 PM PDT 24
Peak memory 201800 kb
Host smart-b1c614e7-94a5-4db5-805d-e5eb2427c052
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369659172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.1369659172
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.457224346
Short name T295
Test name
Test status
Simulation time 523487198707 ps
CPU time 703.44 seconds
Started Jun 11 03:48:55 PM PDT 24
Finished Jun 11 04:00:40 PM PDT 24
Peak memory 201840 kb
Host smart-ca30fc40-1691-4761-ac2c-544577f0a728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457224346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.457224346
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.2179150550
Short name T522
Test name
Test status
Simulation time 166271675380 ps
CPU time 107.58 seconds
Started Jun 11 03:48:48 PM PDT 24
Finished Jun 11 03:50:37 PM PDT 24
Peak memory 201820 kb
Host smart-832c7cd2-0f55-410e-a780-2c4f413bddf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179150550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.2179150550
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.1982622275
Short name T563
Test name
Test status
Simulation time 492139728282 ps
CPU time 75.4 seconds
Started Jun 11 03:48:47 PM PDT 24
Finished Jun 11 03:50:03 PM PDT 24
Peak memory 201956 kb
Host smart-5d0fcb31-e520-4d67-b9e1-52c52a2a2b72
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982622275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.1982622275
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.1277223402
Short name T377
Test name
Test status
Simulation time 324700278182 ps
CPU time 66.83 seconds
Started Jun 11 03:48:50 PM PDT 24
Finished Jun 11 03:49:58 PM PDT 24
Peak memory 201780 kb
Host smart-6c8c5327-3e28-4d4a-80f6-e0f85ae892ef
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277223402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.1277223402
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.90760094
Short name T162
Test name
Test status
Simulation time 522977049369 ps
CPU time 1302.89 seconds
Started Jun 11 03:48:56 PM PDT 24
Finished Jun 11 04:10:40 PM PDT 24
Peak memory 201816 kb
Host smart-2bd066b7-32e5-47ff-9de6-61a7aed00df2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90760094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_w
akeup.90760094
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.2493290281
Short name T760
Test name
Test status
Simulation time 621409719081 ps
CPU time 1412.29 seconds
Started Jun 11 03:48:56 PM PDT 24
Finished Jun 11 04:12:30 PM PDT 24
Peak memory 201852 kb
Host smart-c3951f2c-20b0-4327-99d2-7eef816ee0d0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493290281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.2493290281
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.2434222026
Short name T345
Test name
Test status
Simulation time 109762218119 ps
CPU time 612.44 seconds
Started Jun 11 03:48:56 PM PDT 24
Finished Jun 11 03:59:10 PM PDT 24
Peak memory 202084 kb
Host smart-3fb63495-3a9e-4af0-8c87-2922312f119b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434222026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.2434222026
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.1150287379
Short name T364
Test name
Test status
Simulation time 30868160710 ps
CPU time 74.19 seconds
Started Jun 11 03:48:57 PM PDT 24
Finished Jun 11 03:50:12 PM PDT 24
Peak memory 201536 kb
Host smart-22450d2a-613f-4150-a8c8-4de292aafb72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150287379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.1150287379
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.762449246
Short name T407
Test name
Test status
Simulation time 3715417558 ps
CPU time 9.68 seconds
Started Jun 11 03:48:56 PM PDT 24
Finished Jun 11 03:49:07 PM PDT 24
Peak memory 201600 kb
Host smart-78b26a23-96fe-4859-862c-36c5ab077c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762449246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.762449246
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.3285683778
Short name T781
Test name
Test status
Simulation time 5978947642 ps
CPU time 14.81 seconds
Started Jun 11 03:48:48 PM PDT 24
Finished Jun 11 03:49:04 PM PDT 24
Peak memory 201632 kb
Host smart-9a6941f8-ba50-4a53-87bd-45fe26bcd12e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285683778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.3285683778
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.3430234549
Short name T217
Test name
Test status
Simulation time 53557180799 ps
CPU time 124.43 seconds
Started Jun 11 03:48:55 PM PDT 24
Finished Jun 11 03:51:01 PM PDT 24
Peak memory 201984 kb
Host smart-3b54f031-1397-4418-97e4-c868eccfde6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430234549 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.3430234549
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.3202034256
Short name T516
Test name
Test status
Simulation time 317401378 ps
CPU time 0.81 seconds
Started Jun 11 03:49:11 PM PDT 24
Finished Jun 11 03:49:13 PM PDT 24
Peak memory 201484 kb
Host smart-f9d71e4b-76cf-4edc-8acc-943f939b5037
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202034256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.3202034256
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.2014374787
Short name T338
Test name
Test status
Simulation time 166047582982 ps
CPU time 401.51 seconds
Started Jun 11 03:49:04 PM PDT 24
Finished Jun 11 03:55:47 PM PDT 24
Peak memory 201836 kb
Host smart-1167b377-9b6f-48ee-9e81-c8322d45fff1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014374787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.2014374787
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.1008536306
Short name T256
Test name
Test status
Simulation time 187322263136 ps
CPU time 58.96 seconds
Started Jun 11 03:49:05 PM PDT 24
Finished Jun 11 03:50:05 PM PDT 24
Peak memory 201732 kb
Host smart-a9ee8a66-3dbc-43b5-af23-2e091258cf8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008536306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.1008536306
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.2977382063
Short name T214
Test name
Test status
Simulation time 497908082532 ps
CPU time 1182.66 seconds
Started Jun 11 03:49:05 PM PDT 24
Finished Jun 11 04:08:49 PM PDT 24
Peak memory 201888 kb
Host smart-06fb3e2d-2359-435c-b3ef-d4c0d2bc5d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977382063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.2977382063
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.2806362808
Short name T96
Test name
Test status
Simulation time 493986432370 ps
CPU time 558.08 seconds
Started Jun 11 03:49:03 PM PDT 24
Finished Jun 11 03:58:23 PM PDT 24
Peak memory 201812 kb
Host smart-23ca8298-e6fe-4691-a6cd-7b10b32b64ed
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806362808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.2806362808
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.3031860100
Short name T591
Test name
Test status
Simulation time 165436356377 ps
CPU time 101.12 seconds
Started Jun 11 03:49:04 PM PDT 24
Finished Jun 11 03:50:46 PM PDT 24
Peak memory 201800 kb
Host smart-6f06882e-c6e6-48a5-a748-dbd83812f3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031860100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.3031860100
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.1767608455
Short name T765
Test name
Test status
Simulation time 324827192114 ps
CPU time 770.6 seconds
Started Jun 11 03:49:03 PM PDT 24
Finished Jun 11 04:01:55 PM PDT 24
Peak memory 201760 kb
Host smart-65633b90-975a-47d6-9b24-e4a2e7c34e77
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767608455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.1767608455
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.3676810895
Short name T502
Test name
Test status
Simulation time 534548669321 ps
CPU time 1305.36 seconds
Started Jun 11 03:49:04 PM PDT 24
Finished Jun 11 04:10:51 PM PDT 24
Peak memory 201792 kb
Host smart-5f414b68-b4d8-42db-850e-1281d7615abf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676810895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.3676810895
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.1546344205
Short name T642
Test name
Test status
Simulation time 407553231955 ps
CPU time 511.43 seconds
Started Jun 11 03:49:04 PM PDT 24
Finished Jun 11 03:57:37 PM PDT 24
Peak memory 201816 kb
Host smart-862f2177-ca11-4a94-aa0f-fad963782217
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546344205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.1546344205
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.3059219714
Short name T194
Test name
Test status
Simulation time 117718992144 ps
CPU time 503.42 seconds
Started Jun 11 03:49:12 PM PDT 24
Finished Jun 11 03:57:36 PM PDT 24
Peak memory 202128 kb
Host smart-32f8a444-ce21-431f-94d6-30a177d222d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059219714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.3059219714
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.2945387243
Short name T33
Test name
Test status
Simulation time 27419665512 ps
CPU time 59.53 seconds
Started Jun 11 03:49:12 PM PDT 24
Finished Jun 11 03:50:12 PM PDT 24
Peak memory 201624 kb
Host smart-1c0a24c4-d203-4920-bf47-c9100bf7d915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945387243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.2945387243
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.4207163466
Short name T701
Test name
Test status
Simulation time 5323507946 ps
CPU time 7.14 seconds
Started Jun 11 03:49:03 PM PDT 24
Finished Jun 11 03:49:11 PM PDT 24
Peak memory 201644 kb
Host smart-0299e457-9167-4a6d-b4a1-38dc61c59991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207163466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.4207163466
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.601163361
Short name T729
Test name
Test status
Simulation time 5813042121 ps
CPU time 13.91 seconds
Started Jun 11 03:49:04 PM PDT 24
Finished Jun 11 03:49:19 PM PDT 24
Peak memory 201636 kb
Host smart-ab25268a-8cd2-49d9-a000-8f68f0a8b051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601163361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.601163361
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.3197687605
Short name T392
Test name
Test status
Simulation time 544644882 ps
CPU time 0.91 seconds
Started Jun 11 03:49:20 PM PDT 24
Finished Jun 11 03:49:22 PM PDT 24
Peak memory 201492 kb
Host smart-fdeb5b64-cb81-4e3b-9dec-412da20c3e49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197687605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.3197687605
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.3499796666
Short name T221
Test name
Test status
Simulation time 469623752648 ps
CPU time 1114.15 seconds
Started Jun 11 03:49:21 PM PDT 24
Finished Jun 11 04:07:56 PM PDT 24
Peak memory 201804 kb
Host smart-dd12a23c-4426-4bfa-9622-81e53f724d34
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499796666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.3499796666
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.2397766267
Short name T97
Test name
Test status
Simulation time 165558855843 ps
CPU time 334.97 seconds
Started Jun 11 03:49:21 PM PDT 24
Finished Jun 11 03:54:57 PM PDT 24
Peak memory 201820 kb
Host smart-5bf77965-fe73-486b-ab41-9f3027349da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397766267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.2397766267
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.2538988688
Short name T45
Test name
Test status
Simulation time 162586300519 ps
CPU time 113.65 seconds
Started Jun 11 03:49:20 PM PDT 24
Finished Jun 11 03:51:15 PM PDT 24
Peak memory 201792 kb
Host smart-26e41b5a-dc60-4e92-a9a9-bb432216eef7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538988688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.2538988688
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.1961401230
Short name T778
Test name
Test status
Simulation time 333176082759 ps
CPU time 785.21 seconds
Started Jun 11 03:49:13 PM PDT 24
Finished Jun 11 04:02:19 PM PDT 24
Peak memory 201732 kb
Host smart-9e821fa8-27e8-4cbf-985e-44925de7151a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961401230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.1961401230
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.1002120375
Short name T105
Test name
Test status
Simulation time 328550885255 ps
CPU time 852.89 seconds
Started Jun 11 03:49:21 PM PDT 24
Finished Jun 11 04:03:35 PM PDT 24
Peak memory 201776 kb
Host smart-26c1d24b-51be-454f-918f-ea4f83782a00
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002120375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.1002120375
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.2020642134
Short name T399
Test name
Test status
Simulation time 596831227627 ps
CPU time 599.01 seconds
Started Jun 11 03:49:20 PM PDT 24
Finished Jun 11 03:59:21 PM PDT 24
Peak memory 201912 kb
Host smart-86befd00-fe25-4d65-83ff-4bc425929c9d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020642134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.2020642134
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.33921390
Short name T461
Test name
Test status
Simulation time 101190724144 ps
CPU time 449.93 seconds
Started Jun 11 03:49:20 PM PDT 24
Finished Jun 11 03:56:51 PM PDT 24
Peak memory 202100 kb
Host smart-16f72fe2-54d0-4e19-acfc-6ef70e061ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33921390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.33921390
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.1893611893
Short name T681
Test name
Test status
Simulation time 37664680660 ps
CPU time 86.88 seconds
Started Jun 11 03:49:20 PM PDT 24
Finished Jun 11 03:50:48 PM PDT 24
Peak memory 201640 kb
Host smart-0bdbed05-f400-4bdf-ac29-f71c9951fb39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893611893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.1893611893
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.1197673122
Short name T155
Test name
Test status
Simulation time 3253133568 ps
CPU time 5.33 seconds
Started Jun 11 03:49:22 PM PDT 24
Finished Jun 11 03:49:28 PM PDT 24
Peak memory 201612 kb
Host smart-cb8fb6b2-631d-4134-915c-4057a5a97cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197673122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.1197673122
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.156224742
Short name T644
Test name
Test status
Simulation time 5812444279 ps
CPU time 3.64 seconds
Started Jun 11 03:49:11 PM PDT 24
Finished Jun 11 03:49:16 PM PDT 24
Peak memory 201652 kb
Host smart-f616c3cd-9a51-45a4-8616-57066e26d6c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156224742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.156224742
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.1901255690
Short name T621
Test name
Test status
Simulation time 525349661294 ps
CPU time 1002.5 seconds
Started Jun 11 03:49:22 PM PDT 24
Finished Jun 11 04:06:06 PM PDT 24
Peak memory 201796 kb
Host smart-5c90a971-68b9-41e5-8b89-cfb0bb4454d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901255690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.1901255690
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.3948243789
Short name T297
Test name
Test status
Simulation time 34915599329 ps
CPU time 56.91 seconds
Started Jun 11 03:49:19 PM PDT 24
Finished Jun 11 03:50:17 PM PDT 24
Peak memory 202000 kb
Host smart-aefb7e24-3d88-481e-8150-30c8eaa9b4c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948243789 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.3948243789
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.1278667499
Short name T579
Test name
Test status
Simulation time 434115368 ps
CPU time 1.09 seconds
Started Jun 11 03:44:37 PM PDT 24
Finished Jun 11 03:44:39 PM PDT 24
Peak memory 201484 kb
Host smart-7590329a-d1ff-40c5-b303-e9ca8db6a1d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278667499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.1278667499
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.1362320864
Short name T286
Test name
Test status
Simulation time 176972922414 ps
CPU time 343.55 seconds
Started Jun 11 03:44:35 PM PDT 24
Finished Jun 11 03:50:20 PM PDT 24
Peak memory 201860 kb
Host smart-2f3b520d-efc0-40e7-81c8-14d982b5eb60
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362320864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.1362320864
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.2587489892
Short name T751
Test name
Test status
Simulation time 331250342820 ps
CPU time 360.7 seconds
Started Jun 11 03:44:35 PM PDT 24
Finished Jun 11 03:50:36 PM PDT 24
Peak memory 201828 kb
Host smart-2030b345-3925-45a4-90be-16bbbeeb9cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587489892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.2587489892
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.2726731242
Short name T776
Test name
Test status
Simulation time 488054542618 ps
CPU time 1165.67 seconds
Started Jun 11 03:44:39 PM PDT 24
Finished Jun 11 04:04:06 PM PDT 24
Peak memory 201788 kb
Host smart-e6463cf6-18d1-48fa-804e-5fe367aa71bf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726731242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.2726731242
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.1143051766
Short name T510
Test name
Test status
Simulation time 330517010021 ps
CPU time 801.9 seconds
Started Jun 11 03:44:34 PM PDT 24
Finished Jun 11 03:57:57 PM PDT 24
Peak memory 201764 kb
Host smart-53dd3e31-1a6e-4674-ae70-2669693727cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143051766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.1143051766
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.1673822811
Short name T381
Test name
Test status
Simulation time 491049783560 ps
CPU time 498 seconds
Started Jun 11 03:44:36 PM PDT 24
Finished Jun 11 03:52:55 PM PDT 24
Peak memory 201792 kb
Host smart-a7725a4f-eada-471d-8fcb-547e09da2fcc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673822811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.1673822811
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.3868071240
Short name T499
Test name
Test status
Simulation time 386888870912 ps
CPU time 919.9 seconds
Started Jun 11 03:44:37 PM PDT 24
Finished Jun 11 03:59:59 PM PDT 24
Peak memory 201796 kb
Host smart-cc57dbe0-a93d-466f-899b-3764561a59b7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868071240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.3868071240
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.1430982231
Short name T566
Test name
Test status
Simulation time 105094147707 ps
CPU time 527.12 seconds
Started Jun 11 03:44:36 PM PDT 24
Finished Jun 11 03:53:25 PM PDT 24
Peak memory 202112 kb
Host smart-f2c3fbdd-df57-46aa-9934-0cc726ffaf60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430982231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.1430982231
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.3984053578
Short name T727
Test name
Test status
Simulation time 39763044511 ps
CPU time 79.19 seconds
Started Jun 11 03:44:36 PM PDT 24
Finished Jun 11 03:45:57 PM PDT 24
Peak memory 201660 kb
Host smart-24ff517d-daf1-4f3b-a744-b9ec62c6505b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984053578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.3984053578
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.3841859855
Short name T438
Test name
Test status
Simulation time 3535360486 ps
CPU time 8.29 seconds
Started Jun 11 03:44:36 PM PDT 24
Finished Jun 11 03:44:46 PM PDT 24
Peak memory 201652 kb
Host smart-b5672f83-4f64-4383-9564-34063cfed62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841859855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.3841859855
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.3765372518
Short name T79
Test name
Test status
Simulation time 4168147334 ps
CPU time 10.14 seconds
Started Jun 11 03:44:35 PM PDT 24
Finished Jun 11 03:44:46 PM PDT 24
Peak memory 217336 kb
Host smart-5e30d596-2714-45fa-b82f-823f12c66358
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765372518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.3765372518
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.2306506646
Short name T779
Test name
Test status
Simulation time 5854189565 ps
CPU time 13.33 seconds
Started Jun 11 03:44:35 PM PDT 24
Finished Jun 11 03:44:49 PM PDT 24
Peak memory 201636 kb
Host smart-c8451725-d8b4-4e3a-9316-7db3dd969530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306506646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.2306506646
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.2501523826
Short name T589
Test name
Test status
Simulation time 104630714642 ps
CPU time 521.39 seconds
Started Jun 11 03:44:36 PM PDT 24
Finished Jun 11 03:53:19 PM PDT 24
Peak memory 210564 kb
Host smart-30fdd7ca-a6e9-4e51-92f2-3611d4aef7cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501523826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
2501523826
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.1460212180
Short name T752
Test name
Test status
Simulation time 188683283180 ps
CPU time 85.61 seconds
Started Jun 11 03:44:38 PM PDT 24
Finished Jun 11 03:46:05 PM PDT 24
Peak memory 210464 kb
Host smart-5a178982-6d2c-4665-a461-082726299b7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460212180 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.1460212180
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.416228151
Short name T690
Test name
Test status
Simulation time 424041475 ps
CPU time 1.5 seconds
Started Jun 11 03:49:36 PM PDT 24
Finished Jun 11 03:49:38 PM PDT 24
Peak memory 201440 kb
Host smart-e9efd7ea-fecc-4c40-83e4-3e0ad30b86f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416228151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.416228151
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.531546306
Short name T85
Test name
Test status
Simulation time 415947408310 ps
CPU time 967.05 seconds
Started Jun 11 03:49:29 PM PDT 24
Finished Jun 11 04:05:38 PM PDT 24
Peak memory 201896 kb
Host smart-7ee39483-1564-4fff-8414-d2905b775f45
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531546306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gati
ng.531546306
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.2242680388
Short name T337
Test name
Test status
Simulation time 337312570945 ps
CPU time 73.75 seconds
Started Jun 11 03:49:31 PM PDT 24
Finished Jun 11 03:50:46 PM PDT 24
Peak memory 201792 kb
Host smart-8d45e248-6215-4781-bb5a-034bfeb92f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242680388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.2242680388
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.3068928032
Short name T685
Test name
Test status
Simulation time 323973458679 ps
CPU time 205.5 seconds
Started Jun 11 03:49:30 PM PDT 24
Finished Jun 11 03:52:56 PM PDT 24
Peak memory 201808 kb
Host smart-08d7c0c8-a42f-4ee3-b419-aca58edf3a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068928032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.3068928032
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.2696454540
Short name T554
Test name
Test status
Simulation time 167293838283 ps
CPU time 200.52 seconds
Started Jun 11 03:49:29 PM PDT 24
Finished Jun 11 03:52:50 PM PDT 24
Peak memory 201796 kb
Host smart-aa543aa2-43c9-4295-9df4-2ff829a82650
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696454540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.2696454540
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.3992811704
Short name T12
Test name
Test status
Simulation time 327819577076 ps
CPU time 199.73 seconds
Started Jun 11 03:49:19 PM PDT 24
Finished Jun 11 03:52:39 PM PDT 24
Peak memory 201824 kb
Host smart-8ba0274c-3a7e-4d6d-9f40-08a1adbd7f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992811704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.3992811704
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.2134860828
Short name T745
Test name
Test status
Simulation time 163063154776 ps
CPU time 203.85 seconds
Started Jun 11 03:49:20 PM PDT 24
Finished Jun 11 03:52:44 PM PDT 24
Peak memory 201860 kb
Host smart-7ab42d2d-f388-43ca-9233-48f674f86f3e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134860828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.2134860828
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.2970636211
Short name T148
Test name
Test status
Simulation time 207834141157 ps
CPU time 82.05 seconds
Started Jun 11 03:49:29 PM PDT 24
Finished Jun 11 03:50:51 PM PDT 24
Peak memory 201820 kb
Host smart-48c8a0d3-9a02-4a24-bf26-be88c9e673f8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970636211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.2970636211
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.1991693363
Short name T199
Test name
Test status
Simulation time 104796188817 ps
CPU time 360.07 seconds
Started Jun 11 03:49:31 PM PDT 24
Finished Jun 11 03:55:32 PM PDT 24
Peak memory 202104 kb
Host smart-f4ba2c12-e2f9-4977-be39-19f6a3d57706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991693363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.1991693363
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.3863016248
Short name T388
Test name
Test status
Simulation time 33292975214 ps
CPU time 17.46 seconds
Started Jun 11 03:49:28 PM PDT 24
Finished Jun 11 03:49:46 PM PDT 24
Peak memory 201576 kb
Host smart-c24fe107-4be0-4656-be4c-dd52d7259469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863016248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.3863016248
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.3455216761
Short name T576
Test name
Test status
Simulation time 4215584008 ps
CPU time 11.31 seconds
Started Jun 11 03:49:29 PM PDT 24
Finished Jun 11 03:49:41 PM PDT 24
Peak memory 201628 kb
Host smart-3615391a-299f-4e09-ae33-1ba5bb6475a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455216761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.3455216761
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.3995664212
Short name T442
Test name
Test status
Simulation time 5794181403 ps
CPU time 3.56 seconds
Started Jun 11 03:49:20 PM PDT 24
Finished Jun 11 03:49:25 PM PDT 24
Peak memory 201640 kb
Host smart-0efe4804-3123-4c2c-8225-667e024accb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995664212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.3995664212
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.3227797593
Short name T432
Test name
Test status
Simulation time 276831479887 ps
CPU time 534.16 seconds
Started Jun 11 03:49:35 PM PDT 24
Finished Jun 11 03:58:31 PM PDT 24
Peak memory 210372 kb
Host smart-59049028-e039-4b8c-9b3d-14fab4ea2b4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227797593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.3227797593
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.2503401511
Short name T16
Test name
Test status
Simulation time 234258606578 ps
CPU time 158.35 seconds
Started Jun 11 03:49:34 PM PDT 24
Finished Jun 11 03:52:13 PM PDT 24
Peak memory 210472 kb
Host smart-8cd3a80a-182d-4bfd-a85c-233248e202bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503401511 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.2503401511
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.835949051
Short name T687
Test name
Test status
Simulation time 513978226 ps
CPU time 1.89 seconds
Started Jun 11 03:49:44 PM PDT 24
Finished Jun 11 03:49:46 PM PDT 24
Peak memory 201484 kb
Host smart-04b8e2aa-20b8-4add-a65f-be4f04fe8487
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835949051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.835949051
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.2383266714
Short name T232
Test name
Test status
Simulation time 343424133390 ps
CPU time 904.14 seconds
Started Jun 11 03:49:44 PM PDT 24
Finished Jun 11 04:04:49 PM PDT 24
Peak memory 201800 kb
Host smart-60ceabe3-acb5-4e28-a91d-0858a04e057a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383266714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.2383266714
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.2993525664
Short name T92
Test name
Test status
Simulation time 316561722226 ps
CPU time 200.35 seconds
Started Jun 11 03:49:36 PM PDT 24
Finished Jun 11 03:52:57 PM PDT 24
Peak memory 201984 kb
Host smart-ee837bf3-9e4b-45e3-bf2c-bf44fa694cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993525664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.2993525664
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.525193466
Short name T695
Test name
Test status
Simulation time 342100983226 ps
CPU time 62.42 seconds
Started Jun 11 03:49:36 PM PDT 24
Finished Jun 11 03:50:39 PM PDT 24
Peak memory 201800 kb
Host smart-29842b6d-f504-4de8-8b3e-e24505485560
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=525193466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrup
t_fixed.525193466
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.4251250900
Short name T521
Test name
Test status
Simulation time 487004435498 ps
CPU time 573.39 seconds
Started Jun 11 03:49:35 PM PDT 24
Finished Jun 11 03:59:10 PM PDT 24
Peak memory 201732 kb
Host smart-248de2ef-4909-4de7-947d-daaacbbb7ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251250900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.4251250900
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.2479515181
Short name T444
Test name
Test status
Simulation time 169599791154 ps
CPU time 212.04 seconds
Started Jun 11 03:49:35 PM PDT 24
Finished Jun 11 03:53:08 PM PDT 24
Peak memory 201856 kb
Host smart-835f39b9-a700-4eb5-a163-e0b3df977f52
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479515181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.2479515181
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.3944378938
Short name T290
Test name
Test status
Simulation time 382979140751 ps
CPU time 238.14 seconds
Started Jun 11 03:49:37 PM PDT 24
Finished Jun 11 03:53:36 PM PDT 24
Peak memory 201796 kb
Host smart-7e78a533-bbe1-4818-b0e5-77828f09fd4c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944378938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.3944378938
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.3308330783
Short name T378
Test name
Test status
Simulation time 401470823821 ps
CPU time 503.78 seconds
Started Jun 11 03:49:35 PM PDT 24
Finished Jun 11 03:58:00 PM PDT 24
Peak memory 201800 kb
Host smart-c7144fd8-c113-4c89-a3f2-6b98818d2afa
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308330783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.3308330783
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.3425016874
Short name T55
Test name
Test status
Simulation time 70792212654 ps
CPU time 392.79 seconds
Started Jun 11 03:49:44 PM PDT 24
Finished Jun 11 03:56:18 PM PDT 24
Peak memory 202184 kb
Host smart-ce51ab75-48df-4d93-826a-3686eb45416f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425016874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.3425016874
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.2495878636
Short name T4
Test name
Test status
Simulation time 39581968030 ps
CPU time 6.36 seconds
Started Jun 11 03:49:44 PM PDT 24
Finished Jun 11 03:49:51 PM PDT 24
Peak memory 201656 kb
Host smart-c51f9497-b3ee-40e6-b0aa-0625b13c5d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495878636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.2495878636
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.2560025334
Short name T724
Test name
Test status
Simulation time 5251036934 ps
CPU time 3.67 seconds
Started Jun 11 03:49:43 PM PDT 24
Finished Jun 11 03:49:48 PM PDT 24
Peak memory 201644 kb
Host smart-4d739c16-0157-4297-8cad-96c364f686b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560025334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.2560025334
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.2817508156
Short name T379
Test name
Test status
Simulation time 6078533912 ps
CPU time 4.32 seconds
Started Jun 11 03:49:35 PM PDT 24
Finished Jun 11 03:49:40 PM PDT 24
Peak memory 201572 kb
Host smart-cfe84006-4dbf-41ac-8ca9-72b2dfb01c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817508156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.2817508156
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.149045082
Short name T316
Test name
Test status
Simulation time 411840693574 ps
CPU time 1239.38 seconds
Started Jun 11 03:49:46 PM PDT 24
Finished Jun 11 04:10:26 PM PDT 24
Peak memory 218524 kb
Host smart-702041d4-6978-460e-aa6f-a8ad6eeee027
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149045082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all.
149045082
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.3482051205
Short name T220
Test name
Test status
Simulation time 29707831056 ps
CPU time 53.63 seconds
Started Jun 11 03:49:45 PM PDT 24
Finished Jun 11 03:50:39 PM PDT 24
Peak memory 217056 kb
Host smart-070dd1ae-d109-4872-b913-eb19a77d22fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482051205 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.3482051205
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.3988184456
Short name T352
Test name
Test status
Simulation time 497367440 ps
CPU time 1.03 seconds
Started Jun 11 03:50:03 PM PDT 24
Finished Jun 11 03:50:05 PM PDT 24
Peak memory 201516 kb
Host smart-a369f23a-cfde-44c0-8382-9c800b894401
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988184456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.3988184456
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.653414368
Short name T278
Test name
Test status
Simulation time 358709305501 ps
CPU time 143.37 seconds
Started Jun 11 03:49:55 PM PDT 24
Finished Jun 11 03:52:19 PM PDT 24
Peak memory 201836 kb
Host smart-6d6fb8d7-e538-4894-85ae-9f4c4880e8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653414368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.653414368
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.1718040327
Short name T736
Test name
Test status
Simulation time 323689771651 ps
CPU time 766.75 seconds
Started Jun 11 03:49:54 PM PDT 24
Finished Jun 11 04:02:42 PM PDT 24
Peak memory 201864 kb
Host smart-e4a321ca-fc9c-4fd4-bf98-c5eb4de1ef88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718040327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.1718040327
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.2137220518
Short name T43
Test name
Test status
Simulation time 168123814857 ps
CPU time 109.06 seconds
Started Jun 11 03:49:55 PM PDT 24
Finished Jun 11 03:51:45 PM PDT 24
Peak memory 201792 kb
Host smart-933453a7-77a4-4a28-8724-2ecf94da63bd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137220518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.2137220518
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.3732522007
Short name T387
Test name
Test status
Simulation time 168936480879 ps
CPU time 98.43 seconds
Started Jun 11 03:49:45 PM PDT 24
Finished Jun 11 03:51:24 PM PDT 24
Peak memory 201884 kb
Host smart-6301d876-38c9-4c1c-87c9-20535f5c754a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732522007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.3732522007
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.3969700364
Short name T612
Test name
Test status
Simulation time 491134150206 ps
CPU time 1246.48 seconds
Started Jun 11 03:49:56 PM PDT 24
Finished Jun 11 04:10:43 PM PDT 24
Peak memory 201808 kb
Host smart-53761d82-7200-47e7-8317-246a673a76b6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969700364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.3969700364
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.831774647
Short name T583
Test name
Test status
Simulation time 594964319032 ps
CPU time 1450.36 seconds
Started Jun 11 03:49:54 PM PDT 24
Finished Jun 11 04:14:06 PM PDT 24
Peak memory 201880 kb
Host smart-f9eca027-a1c4-4c99-9749-d53b1cb0a961
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831774647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
adc_ctrl_filters_wakeup_fixed.831774647
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.2954007987
Short name T434
Test name
Test status
Simulation time 25013671571 ps
CPU time 31.04 seconds
Started Jun 11 03:50:04 PM PDT 24
Finished Jun 11 03:50:36 PM PDT 24
Peak memory 201652 kb
Host smart-3adaac55-88be-4afc-9f34-aa08f038df56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954007987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.2954007987
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.3455969838
Short name T362
Test name
Test status
Simulation time 3766637899 ps
CPU time 5.15 seconds
Started Jun 11 03:49:55 PM PDT 24
Finished Jun 11 03:50:01 PM PDT 24
Peak memory 201632 kb
Host smart-5db9cc39-979a-4057-b6f7-5589a32ef7d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455969838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.3455969838
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.1571098180
Short name T794
Test name
Test status
Simulation time 5867258871 ps
CPU time 14.91 seconds
Started Jun 11 03:49:43 PM PDT 24
Finished Jun 11 03:49:59 PM PDT 24
Peak memory 201676 kb
Host smart-b749ef01-684a-42f2-9209-3cc90a6bf3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571098180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.1571098180
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.2428309797
Short name T480
Test name
Test status
Simulation time 104155876652 ps
CPU time 244.58 seconds
Started Jun 11 03:50:02 PM PDT 24
Finished Jun 11 03:54:08 PM PDT 24
Peak memory 210112 kb
Host smart-9735aea6-d4bb-468a-961a-f764ff87e122
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428309797 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.2428309797
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.1259882435
Short name T452
Test name
Test status
Simulation time 337048211 ps
CPU time 0.77 seconds
Started Jun 11 03:50:10 PM PDT 24
Finished Jun 11 03:50:12 PM PDT 24
Peak memory 201448 kb
Host smart-1cc271e0-b343-43fb-9740-ca71402c30c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259882435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.1259882435
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.3733588679
Short name T226
Test name
Test status
Simulation time 351409269128 ps
CPU time 307.83 seconds
Started Jun 11 03:50:02 PM PDT 24
Finished Jun 11 03:55:10 PM PDT 24
Peak memory 201828 kb
Host smart-00049451-857e-4820-baa0-7b3d1087db7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733588679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.3733588679
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.3934324781
Short name T424
Test name
Test status
Simulation time 161539501319 ps
CPU time 28.75 seconds
Started Jun 11 03:50:03 PM PDT 24
Finished Jun 11 03:50:32 PM PDT 24
Peak memory 201808 kb
Host smart-849e8bd1-f69f-4f03-94f2-693b560d7e42
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934324781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.3934324781
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.3963230636
Short name T264
Test name
Test status
Simulation time 328372770523 ps
CPU time 200.48 seconds
Started Jun 11 03:50:01 PM PDT 24
Finished Jun 11 03:53:22 PM PDT 24
Peak memory 201820 kb
Host smart-154d4505-b5d4-4c71-bad7-0fe80a5e2c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963230636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.3963230636
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.299242487
Short name T391
Test name
Test status
Simulation time 486002223429 ps
CPU time 1274.7 seconds
Started Jun 11 03:50:05 PM PDT 24
Finished Jun 11 04:11:20 PM PDT 24
Peak memory 201860 kb
Host smart-a64d7b15-0b06-4ca6-b880-e94d60e5807c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=299242487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fixe
d.299242487
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.710356387
Short name T282
Test name
Test status
Simulation time 445118515870 ps
CPU time 527.65 seconds
Started Jun 11 03:50:02 PM PDT 24
Finished Jun 11 03:58:50 PM PDT 24
Peak memory 201832 kb
Host smart-b078ec35-2119-4ea4-8d95-ef93fee41da4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710356387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_
wakeup.710356387
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.4130347538
Short name T569
Test name
Test status
Simulation time 395177484075 ps
CPU time 503.09 seconds
Started Jun 11 03:50:01 PM PDT 24
Finished Jun 11 03:58:25 PM PDT 24
Peak memory 201796 kb
Host smart-ae92d387-4011-4057-aa97-ed30bdf92f94
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130347538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.4130347538
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.1412036924
Short name T739
Test name
Test status
Simulation time 117488704115 ps
CPU time 408.84 seconds
Started Jun 11 03:50:14 PM PDT 24
Finished Jun 11 03:57:04 PM PDT 24
Peak memory 202240 kb
Host smart-e216de98-f3bb-4961-8fad-4cab79f8f3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412036924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.1412036924
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.3630093201
Short name T749
Test name
Test status
Simulation time 26846584705 ps
CPU time 19.49 seconds
Started Jun 11 03:50:03 PM PDT 24
Finished Jun 11 03:50:23 PM PDT 24
Peak memory 201672 kb
Host smart-55c5ce04-ddca-449b-a478-77a047d62b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630093201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.3630093201
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.357138370
Short name T127
Test name
Test status
Simulation time 3242440526 ps
CPU time 7.83 seconds
Started Jun 11 03:50:04 PM PDT 24
Finished Jun 11 03:50:12 PM PDT 24
Peak memory 201592 kb
Host smart-e24ea72d-b6b0-427c-bde3-ec4a0c48a374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357138370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.357138370
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.2717818820
Short name T401
Test name
Test status
Simulation time 5491544895 ps
CPU time 13.1 seconds
Started Jun 11 03:50:04 PM PDT 24
Finished Jun 11 03:50:18 PM PDT 24
Peak memory 201664 kb
Host smart-90a386cf-8eaf-4599-a62c-6ed01e5fb250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717818820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.2717818820
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.3188770189
Short name T298
Test name
Test status
Simulation time 171073932537 ps
CPU time 355.44 seconds
Started Jun 11 03:50:11 PM PDT 24
Finished Jun 11 03:56:07 PM PDT 24
Peak memory 201816 kb
Host smart-990fff00-31c5-4809-b45c-832cbc534435
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188770189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.3188770189
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.3112291231
Short name T484
Test name
Test status
Simulation time 454007051 ps
CPU time 1.66 seconds
Started Jun 11 03:50:26 PM PDT 24
Finished Jun 11 03:50:29 PM PDT 24
Peak memory 201528 kb
Host smart-81fc8886-329d-4b5c-b1a4-167e4e61a82a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112291231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.3112291231
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.523320438
Short name T236
Test name
Test status
Simulation time 520309302440 ps
CPU time 1232.35 seconds
Started Jun 11 03:50:19 PM PDT 24
Finished Jun 11 04:10:52 PM PDT 24
Peak memory 201768 kb
Host smart-e5ac539b-6f35-433e-9eb2-cae7565ef23d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523320438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gati
ng.523320438
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.973965067
Short name T631
Test name
Test status
Simulation time 488371951215 ps
CPU time 1229.03 seconds
Started Jun 11 03:50:11 PM PDT 24
Finished Jun 11 04:10:41 PM PDT 24
Peak memory 201800 kb
Host smart-49bb3da0-8b02-45a0-8426-6c9155a14fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973965067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.973965067
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.1833338438
Short name T382
Test name
Test status
Simulation time 328519588720 ps
CPU time 811 seconds
Started Jun 11 03:50:19 PM PDT 24
Finished Jun 11 04:03:52 PM PDT 24
Peak memory 201732 kb
Host smart-7b09ccfd-dc8e-420b-8755-1c9a0e264e1a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833338438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.1833338438
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.2942193413
Short name T140
Test name
Test status
Simulation time 168185595150 ps
CPU time 402.74 seconds
Started Jun 11 03:50:11 PM PDT 24
Finished Jun 11 03:56:54 PM PDT 24
Peak memory 201808 kb
Host smart-51c0dba5-4be6-48ac-b4d1-8fc9c1e2cd99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942193413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.2942193413
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.3514438739
Short name T615
Test name
Test status
Simulation time 491716850984 ps
CPU time 656.76 seconds
Started Jun 11 03:50:12 PM PDT 24
Finished Jun 11 04:01:10 PM PDT 24
Peak memory 201804 kb
Host smart-e643501e-d5ed-4bfd-aabb-fd7340050753
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514438739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.3514438739
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.2477127371
Short name T599
Test name
Test status
Simulation time 167997181652 ps
CPU time 438.03 seconds
Started Jun 11 03:50:19 PM PDT 24
Finished Jun 11 03:57:38 PM PDT 24
Peak memory 201872 kb
Host smart-9e66ab7c-209e-473c-bbf8-3cd5e0342ae1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477127371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.2477127371
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.861555404
Short name T374
Test name
Test status
Simulation time 621210002713 ps
CPU time 746.46 seconds
Started Jun 11 03:50:18 PM PDT 24
Finished Jun 11 04:02:46 PM PDT 24
Peak memory 202024 kb
Host smart-da9030fb-b657-4e5d-b32b-adbd848370f1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861555404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
adc_ctrl_filters_wakeup_fixed.861555404
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.659430891
Short name T539
Test name
Test status
Simulation time 78409617139 ps
CPU time 455.6 seconds
Started Jun 11 03:50:18 PM PDT 24
Finished Jun 11 03:57:56 PM PDT 24
Peak memory 202036 kb
Host smart-bdfaa006-a15f-4fa8-9495-889c7c7c5468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659430891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.659430891
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.1149820572
Short name T653
Test name
Test status
Simulation time 35608029641 ps
CPU time 84.87 seconds
Started Jun 11 03:50:19 PM PDT 24
Finished Jun 11 03:51:45 PM PDT 24
Peak memory 201628 kb
Host smart-8ae38ff0-54ad-4207-87b7-f255423eb4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149820572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.1149820572
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.2108199070
Short name T353
Test name
Test status
Simulation time 5453925321 ps
CPU time 3.05 seconds
Started Jun 11 03:50:18 PM PDT 24
Finished Jun 11 03:50:22 PM PDT 24
Peak memory 201624 kb
Host smart-5a136371-e760-4909-93c8-1a370a59ee78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108199070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.2108199070
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.2969249882
Short name T403
Test name
Test status
Simulation time 6066557612 ps
CPU time 13.9 seconds
Started Jun 11 03:50:13 PM PDT 24
Finished Jun 11 03:50:27 PM PDT 24
Peak memory 201628 kb
Host smart-2af53d80-4679-42e9-a936-aa8edc2d651d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969249882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.2969249882
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.3492080625
Short name T266
Test name
Test status
Simulation time 209895813365 ps
CPU time 507.19 seconds
Started Jun 11 03:50:18 PM PDT 24
Finished Jun 11 03:58:47 PM PDT 24
Peak memory 201828 kb
Host smart-adae413a-94ab-4364-af4f-d2e2c92f3037
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492080625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.3492080625
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.633888195
Short name T389
Test name
Test status
Simulation time 360396928 ps
CPU time 0.82 seconds
Started Jun 11 03:50:46 PM PDT 24
Finished Jun 11 03:50:48 PM PDT 24
Peak memory 201484 kb
Host smart-d9fcf59f-e99e-4f0a-bd51-8a488debec3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633888195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.633888195
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.145745344
Short name T323
Test name
Test status
Simulation time 332654793006 ps
CPU time 49.95 seconds
Started Jun 11 03:50:26 PM PDT 24
Finished Jun 11 03:51:17 PM PDT 24
Peak memory 201760 kb
Host smart-a8747c39-e210-4606-b2b1-0912ff16dd56
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145745344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gati
ng.145745344
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.1784379622
Short name T150
Test name
Test status
Simulation time 488043973448 ps
CPU time 1189.28 seconds
Started Jun 11 03:50:26 PM PDT 24
Finished Jun 11 04:10:17 PM PDT 24
Peak memory 201908 kb
Host smart-0de1e4eb-3df9-41cb-9d1a-88b2f3009f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784379622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.1784379622
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.1407036344
Short name T618
Test name
Test status
Simulation time 494466024626 ps
CPU time 316.4 seconds
Started Jun 11 03:50:28 PM PDT 24
Finished Jun 11 03:55:46 PM PDT 24
Peak memory 201744 kb
Host smart-324e9c98-a2ce-49bf-947d-5d72589710e4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407036344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.1407036344
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.1459773847
Short name T293
Test name
Test status
Simulation time 327779695381 ps
CPU time 771.97 seconds
Started Jun 11 03:50:26 PM PDT 24
Finished Jun 11 04:03:19 PM PDT 24
Peak memory 201816 kb
Host smart-b3a1963f-5ca1-4cc6-bd79-e095a2c55567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459773847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.1459773847
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.411916614
Short name T613
Test name
Test status
Simulation time 326961102853 ps
CPU time 192.49 seconds
Started Jun 11 03:50:28 PM PDT 24
Finished Jun 11 03:53:41 PM PDT 24
Peak memory 201832 kb
Host smart-b4103682-47e7-4406-873f-b0ae522a1e17
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=411916614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fixe
d.411916614
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.2849293409
Short name T132
Test name
Test status
Simulation time 366437756485 ps
CPU time 196.54 seconds
Started Jun 11 03:50:27 PM PDT 24
Finished Jun 11 03:53:45 PM PDT 24
Peak memory 201788 kb
Host smart-8f451281-3dcf-4964-bcb8-32a22e16ea41
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849293409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.2849293409
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.3220222210
Short name T459
Test name
Test status
Simulation time 208810667810 ps
CPU time 309.65 seconds
Started Jun 11 03:50:27 PM PDT 24
Finished Jun 11 03:55:38 PM PDT 24
Peak memory 201972 kb
Host smart-cf636102-f1b3-44fb-b713-2bab34945c39
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220222210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.3220222210
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.2272119209
Short name T674
Test name
Test status
Simulation time 66257272530 ps
CPU time 236.83 seconds
Started Jun 11 03:50:37 PM PDT 24
Finished Jun 11 03:54:35 PM PDT 24
Peak memory 202176 kb
Host smart-2b5b9bdf-4e6c-4515-bd94-2f111d3e9c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272119209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.2272119209
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.1112818573
Short name T668
Test name
Test status
Simulation time 36525335628 ps
CPU time 88.87 seconds
Started Jun 11 03:50:36 PM PDT 24
Finished Jun 11 03:52:06 PM PDT 24
Peak memory 201604 kb
Host smart-81756506-1c9a-45f6-a2ac-f621e15a20b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112818573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.1112818573
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.4035965353
Short name T728
Test name
Test status
Simulation time 2974840403 ps
CPU time 7.47 seconds
Started Jun 11 03:50:37 PM PDT 24
Finished Jun 11 03:50:45 PM PDT 24
Peak memory 201652 kb
Host smart-772d7278-c7a2-40bd-9451-15545e6c78ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035965353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.4035965353
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.1660854148
Short name T719
Test name
Test status
Simulation time 5900473840 ps
CPU time 4.17 seconds
Started Jun 11 03:50:28 PM PDT 24
Finished Jun 11 03:50:33 PM PDT 24
Peak memory 201612 kb
Host smart-d293a367-5934-47c7-9d3d-4c5d3ef965c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660854148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.1660854148
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.1765610292
Short name T1
Test name
Test status
Simulation time 287965373781 ps
CPU time 376.19 seconds
Started Jun 11 03:50:36 PM PDT 24
Finished Jun 11 03:56:53 PM PDT 24
Peak memory 210376 kb
Host smart-04a7d8bf-8795-4eaa-a8b1-f27e1942fa1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765610292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.1765610292
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.1982591352
Short name T83
Test name
Test status
Simulation time 81704360293 ps
CPU time 201.38 seconds
Started Jun 11 03:50:36 PM PDT 24
Finished Jun 11 03:53:59 PM PDT 24
Peak memory 210424 kb
Host smart-e4edd723-f516-4e07-9c28-0cc3ffab4f71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982591352 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.1982591352
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.1405469513
Short name T511
Test name
Test status
Simulation time 491045475 ps
CPU time 1.46 seconds
Started Jun 11 03:50:45 PM PDT 24
Finished Jun 11 03:50:47 PM PDT 24
Peak memory 201492 kb
Host smart-19ba138d-389d-43b8-b7b1-19ce0f45c85a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405469513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.1405469513
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.3344559189
Short name T329
Test name
Test status
Simulation time 166160849497 ps
CPU time 384.89 seconds
Started Jun 11 03:50:45 PM PDT 24
Finished Jun 11 03:57:11 PM PDT 24
Peak memory 201756 kb
Host smart-f705e40d-511c-4777-a77c-2a976b098610
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344559189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.3344559189
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.4097395921
Short name T151
Test name
Test status
Simulation time 492598147664 ps
CPU time 588.63 seconds
Started Jun 11 03:50:43 PM PDT 24
Finished Jun 11 04:00:33 PM PDT 24
Peak memory 201812 kb
Host smart-19cec5a6-6735-4c1f-be95-f647cf5ee7ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097395921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.4097395921
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.3706860197
Short name T487
Test name
Test status
Simulation time 491501771332 ps
CPU time 309.98 seconds
Started Jun 11 03:50:43 PM PDT 24
Finished Jun 11 03:55:54 PM PDT 24
Peak memory 201820 kb
Host smart-b7fa715a-1604-45b7-8afa-25a55043d2ff
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706860197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.3706860197
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.3252844459
Short name T216
Test name
Test status
Simulation time 320137343471 ps
CPU time 788.18 seconds
Started Jun 11 03:50:45 PM PDT 24
Finished Jun 11 04:03:54 PM PDT 24
Peak memory 201820 kb
Host smart-b509ca63-13ec-44e5-8a05-1fa698703202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252844459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.3252844459
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.2966109528
Short name T471
Test name
Test status
Simulation time 494687223931 ps
CPU time 1266.3 seconds
Started Jun 11 03:50:44 PM PDT 24
Finished Jun 11 04:11:51 PM PDT 24
Peak memory 201828 kb
Host smart-bf044114-38fa-4f54-806f-a34ab825eb41
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966109528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.2966109528
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.3707745
Short name T260
Test name
Test status
Simulation time 174173460568 ps
CPU time 458.18 seconds
Started Jun 11 03:50:45 PM PDT 24
Finished Jun 11 03:58:24 PM PDT 24
Peak memory 201836 kb
Host smart-defce3fe-2717-4b96-b190-083c4053cdf1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_w
akeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_wa
keup.3707745
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.2521475242
Short name T420
Test name
Test status
Simulation time 402529947641 ps
CPU time 90.01 seconds
Started Jun 11 03:50:43 PM PDT 24
Finished Jun 11 03:52:14 PM PDT 24
Peak memory 201784 kb
Host smart-1b572ae1-77f0-46dd-a43e-d40080ec72f9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521475242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.2521475242
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.3263328336
Short name T208
Test name
Test status
Simulation time 75194579692 ps
CPU time 336.47 seconds
Started Jun 11 03:50:45 PM PDT 24
Finished Jun 11 03:56:22 PM PDT 24
Peak memory 202164 kb
Host smart-692444f8-1d08-4566-ade1-eeadf265e91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263328336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.3263328336
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.401455572
Short name T38
Test name
Test status
Simulation time 38151450047 ps
CPU time 24.84 seconds
Started Jun 11 03:50:42 PM PDT 24
Finished Jun 11 03:51:08 PM PDT 24
Peak memory 201652 kb
Host smart-fea8a4ed-dbbd-4f2b-ab5d-26c8d39a0d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401455572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.401455572
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.2029541400
Short name T761
Test name
Test status
Simulation time 4085249388 ps
CPU time 2.79 seconds
Started Jun 11 03:50:43 PM PDT 24
Finished Jun 11 03:50:46 PM PDT 24
Peak memory 201640 kb
Host smart-f74e6c9e-15e9-42d0-8369-78e804c013a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029541400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.2029541400
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.3080115477
Short name T650
Test name
Test status
Simulation time 5770539817 ps
CPU time 11.77 seconds
Started Jun 11 03:50:41 PM PDT 24
Finished Jun 11 03:50:53 PM PDT 24
Peak memory 201560 kb
Host smart-08e75998-6804-4098-be95-3c471a55bfe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080115477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.3080115477
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.4027551672
Short name T535
Test name
Test status
Simulation time 81440367891 ps
CPU time 121.83 seconds
Started Jun 11 03:50:45 PM PDT 24
Finished Jun 11 03:52:47 PM PDT 24
Peak memory 201808 kb
Host smart-b83619ee-349c-41be-83d3-5e6222e9ebb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027551672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.4027551672
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.3876739236
Short name T22
Test name
Test status
Simulation time 196878711592 ps
CPU time 97.29 seconds
Started Jun 11 03:50:45 PM PDT 24
Finished Jun 11 03:52:24 PM PDT 24
Peak memory 210084 kb
Host smart-7d4aad96-782a-4693-8b76-951ab01be65c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876739236 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.3876739236
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.2770255213
Short name T795
Test name
Test status
Simulation time 343710637 ps
CPU time 1.41 seconds
Started Jun 11 03:50:53 PM PDT 24
Finished Jun 11 03:50:55 PM PDT 24
Peak memory 201504 kb
Host smart-480c1e16-e41e-4619-9e77-dcb1d44adf20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770255213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.2770255213
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.1488219158
Short name T161
Test name
Test status
Simulation time 176404440015 ps
CPU time 95.58 seconds
Started Jun 11 03:50:52 PM PDT 24
Finished Jun 11 03:52:29 PM PDT 24
Peak memory 201828 kb
Host smart-fe1816e1-0927-42ea-aa9c-76f6ffc2804d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488219158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.1488219158
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.2334028012
Short name T689
Test name
Test status
Simulation time 515715526805 ps
CPU time 1310.67 seconds
Started Jun 11 03:50:51 PM PDT 24
Finished Jun 11 04:12:42 PM PDT 24
Peak memory 201884 kb
Host smart-7442e8df-f06b-40ef-96f0-f8b107417691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334028012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.2334028012
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.994904565
Short name T475
Test name
Test status
Simulation time 324039902879 ps
CPU time 833.15 seconds
Started Jun 11 03:50:55 PM PDT 24
Finished Jun 11 04:04:49 PM PDT 24
Peak memory 201080 kb
Host smart-39962af9-a984-4da9-a2d5-af059810be33
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=994904565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrup
t_fixed.994904565
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.4070605752
Short name T558
Test name
Test status
Simulation time 161576286831 ps
CPU time 372.09 seconds
Started Jun 11 03:50:55 PM PDT 24
Finished Jun 11 03:57:08 PM PDT 24
Peak memory 201184 kb
Host smart-d4846151-daf7-4f52-92e8-eb99b98143e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070605752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.4070605752
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.138542254
Short name T360
Test name
Test status
Simulation time 328441861840 ps
CPU time 65.09 seconds
Started Jun 11 03:50:51 PM PDT 24
Finished Jun 11 03:51:58 PM PDT 24
Peak memory 201776 kb
Host smart-69eb4d74-c2dc-482c-a4a8-30d567fa0675
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=138542254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fixe
d.138542254
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.3152863390
Short name T137
Test name
Test status
Simulation time 365959927047 ps
CPU time 870.84 seconds
Started Jun 11 03:50:51 PM PDT 24
Finished Jun 11 04:05:24 PM PDT 24
Peak memory 201872 kb
Host smart-4fe3c01a-9644-4e14-8f35-59d01f01ad94
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152863390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.3152863390
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.552200902
Short name T715
Test name
Test status
Simulation time 601995169136 ps
CPU time 418.18 seconds
Started Jun 11 03:50:51 PM PDT 24
Finished Jun 11 03:57:51 PM PDT 24
Peak memory 201816 kb
Host smart-3611a997-f25f-487f-8cdc-22af71cd8ce6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552200902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
adc_ctrl_filters_wakeup_fixed.552200902
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.2707613643
Short name T196
Test name
Test status
Simulation time 140523884041 ps
CPU time 796.08 seconds
Started Jun 11 03:50:53 PM PDT 24
Finished Jun 11 04:04:10 PM PDT 24
Peak memory 202140 kb
Host smart-d85a71e2-f552-4057-871e-f0b274686ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707613643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.2707613643
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.2869674565
Short name T395
Test name
Test status
Simulation time 31697927573 ps
CPU time 15.01 seconds
Started Jun 11 03:50:53 PM PDT 24
Finished Jun 11 03:51:09 PM PDT 24
Peak memory 201592 kb
Host smart-832a0087-e14c-43d7-9454-9b95cb7fc308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869674565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.2869674565
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.2599927596
Short name T34
Test name
Test status
Simulation time 3772708013 ps
CPU time 9.53 seconds
Started Jun 11 03:50:52 PM PDT 24
Finished Jun 11 03:51:03 PM PDT 24
Peak memory 201624 kb
Host smart-e3575388-c78e-4160-8621-4c9044614b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599927596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.2599927596
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.4086093952
Short name T473
Test name
Test status
Simulation time 5769741299 ps
CPU time 2.49 seconds
Started Jun 11 03:50:43 PM PDT 24
Finished Jun 11 03:50:46 PM PDT 24
Peak memory 201652 kb
Host smart-70bddea6-09d4-45db-9420-dd86f3cc1d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086093952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.4086093952
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.2104858620
Short name T666
Test name
Test status
Simulation time 170841928698 ps
CPU time 395.48 seconds
Started Jun 11 03:50:52 PM PDT 24
Finished Jun 11 03:57:29 PM PDT 24
Peak memory 201752 kb
Host smart-050a7dd6-9a37-41e7-bd6a-a31fece85f64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104858620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.2104858620
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.229431477
Short name T573
Test name
Test status
Simulation time 639646188646 ps
CPU time 625.8 seconds
Started Jun 11 03:50:51 PM PDT 24
Finished Jun 11 04:01:18 PM PDT 24
Peak memory 210532 kb
Host smart-87eebdd6-cce4-4304-bbf1-9d688c96b0ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229431477 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.229431477
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.1528719932
Short name T782
Test name
Test status
Simulation time 553713884 ps
CPU time 0.89 seconds
Started Jun 11 03:51:07 PM PDT 24
Finished Jun 11 03:51:09 PM PDT 24
Peak memory 201496 kb
Host smart-57f33ad4-604a-4575-a49f-544f109372f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528719932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.1528719932
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.1466252370
Short name T95
Test name
Test status
Simulation time 386617024535 ps
CPU time 638.92 seconds
Started Jun 11 03:51:00 PM PDT 24
Finished Jun 11 04:01:40 PM PDT 24
Peak memory 201876 kb
Host smart-2d11c757-9088-497b-be6e-99edd331ed07
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466252370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.1466252370
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.1921028213
Short name T241
Test name
Test status
Simulation time 164842280849 ps
CPU time 92.39 seconds
Started Jun 11 03:51:02 PM PDT 24
Finished Jun 11 03:52:35 PM PDT 24
Peak memory 201808 kb
Host smart-31399892-ea23-44f8-9368-4e5a392de920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921028213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.1921028213
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.498562921
Short name T448
Test name
Test status
Simulation time 321937827061 ps
CPU time 828.16 seconds
Started Jun 11 03:51:02 PM PDT 24
Finished Jun 11 04:04:51 PM PDT 24
Peak memory 201796 kb
Host smart-0249bef8-3c95-406f-91d9-13a4b39b38e3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=498562921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrup
t_fixed.498562921
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.1127355801
Short name T469
Test name
Test status
Simulation time 159643078917 ps
CPU time 374.02 seconds
Started Jun 11 03:51:00 PM PDT 24
Finished Jun 11 03:57:14 PM PDT 24
Peak memory 201788 kb
Host smart-fd8ad440-20bd-41fa-a6e7-c4c498bbbf17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127355801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.1127355801
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.2160983832
Short name T468
Test name
Test status
Simulation time 326897041173 ps
CPU time 204.17 seconds
Started Jun 11 03:51:02 PM PDT 24
Finished Jun 11 03:54:27 PM PDT 24
Peak memory 201804 kb
Host smart-95dd01cb-89f3-4155-bf58-01ce88eb28d9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160983832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.2160983832
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.3105775351
Short name T309
Test name
Test status
Simulation time 172663029609 ps
CPU time 87.15 seconds
Started Jun 11 03:51:01 PM PDT 24
Finished Jun 11 03:52:29 PM PDT 24
Peak memory 201928 kb
Host smart-4295b776-1730-4fd5-a4e1-502a66b27806
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105775351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.3105775351
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.28326731
Short name T584
Test name
Test status
Simulation time 190622095086 ps
CPU time 436.36 seconds
Started Jun 11 03:51:00 PM PDT 24
Finished Jun 11 03:58:17 PM PDT 24
Peak memory 201800 kb
Host smart-6ef1b61e-cb83-4887-8558-03f6fbc5835d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28326731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.a
dc_ctrl_filters_wakeup_fixed.28326731
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.1219258940
Short name T346
Test name
Test status
Simulation time 128816898170 ps
CPU time 519.24 seconds
Started Jun 11 03:51:01 PM PDT 24
Finished Jun 11 03:59:41 PM PDT 24
Peak memory 202200 kb
Host smart-e10cb196-b13d-4140-9391-423b5d17934b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219258940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.1219258940
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.2286670265
Short name T763
Test name
Test status
Simulation time 33847629725 ps
CPU time 21.62 seconds
Started Jun 11 03:51:02 PM PDT 24
Finished Jun 11 03:51:25 PM PDT 24
Peak memory 201624 kb
Host smart-00ed66d6-4e05-4403-823e-509a328d61c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286670265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.2286670265
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.352219474
Short name T628
Test name
Test status
Simulation time 3097426446 ps
CPU time 2.56 seconds
Started Jun 11 03:51:01 PM PDT 24
Finished Jun 11 03:51:04 PM PDT 24
Peak memory 201656 kb
Host smart-5d513a1c-6301-4c29-9c87-da0a818f10cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352219474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.352219474
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.3880975689
Short name T557
Test name
Test status
Simulation time 6108475209 ps
CPU time 14.97 seconds
Started Jun 11 03:50:51 PM PDT 24
Finished Jun 11 03:51:07 PM PDT 24
Peak memory 201640 kb
Host smart-76443585-8370-4a99-8089-5c2cbbba4196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880975689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.3880975689
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.2977580212
Short name T308
Test name
Test status
Simulation time 377717320903 ps
CPU time 503.62 seconds
Started Jun 11 03:51:01 PM PDT 24
Finished Jun 11 03:59:26 PM PDT 24
Peak memory 201776 kb
Host smart-c1fb4686-b1f7-4e4c-8dde-c3b0aba1890d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977580212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.2977580212
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.3464482449
Short name T50
Test name
Test status
Simulation time 83599226700 ps
CPU time 125.3 seconds
Started Jun 11 03:51:01 PM PDT 24
Finished Jun 11 03:53:08 PM PDT 24
Peak memory 201952 kb
Host smart-b3a7874f-6f76-46d2-b3fb-cc6c5d02580c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464482449 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.3464482449
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.403413422
Short name T524
Test name
Test status
Simulation time 508320682 ps
CPU time 0.82 seconds
Started Jun 11 03:51:17 PM PDT 24
Finished Jun 11 03:51:19 PM PDT 24
Peak memory 201520 kb
Host smart-738f9950-3532-4be3-9d80-c56a927e8292
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403413422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.403413422
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.1894839106
Short name T8
Test name
Test status
Simulation time 227507812311 ps
CPU time 157.69 seconds
Started Jun 11 03:51:18 PM PDT 24
Finished Jun 11 03:53:57 PM PDT 24
Peak memory 201868 kb
Host smart-4feedbee-d031-4308-ada7-05c08dd95ab0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894839106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.1894839106
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.180164822
Short name T245
Test name
Test status
Simulation time 180248711582 ps
CPU time 383.59 seconds
Started Jun 11 03:51:19 PM PDT 24
Finished Jun 11 03:57:44 PM PDT 24
Peak memory 201816 kb
Host smart-932d576e-b52e-4169-9e78-aa15e833c258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180164822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.180164822
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.1963762992
Short name T272
Test name
Test status
Simulation time 505253010856 ps
CPU time 587.44 seconds
Started Jun 11 03:51:08 PM PDT 24
Finished Jun 11 04:00:57 PM PDT 24
Peak memory 201880 kb
Host smart-9299e7a1-0597-4244-9f5b-4766706b20cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963762992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.1963762992
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.1449935621
Short name T504
Test name
Test status
Simulation time 497759753146 ps
CPU time 535.34 seconds
Started Jun 11 03:51:08 PM PDT 24
Finished Jun 11 04:00:05 PM PDT 24
Peak memory 201848 kb
Host smart-012e1b94-e164-4ab2-baf5-411751945fd4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449935621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.1449935621
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.4129661953
Short name T796
Test name
Test status
Simulation time 333725005488 ps
CPU time 206.47 seconds
Started Jun 11 03:51:07 PM PDT 24
Finished Jun 11 03:54:35 PM PDT 24
Peak memory 201912 kb
Host smart-a25620ab-3812-4734-b07a-1bf3ab677b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129661953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.4129661953
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.285208726
Short name T373
Test name
Test status
Simulation time 487244246339 ps
CPU time 657.18 seconds
Started Jun 11 03:51:08 PM PDT 24
Finished Jun 11 04:02:06 PM PDT 24
Peak memory 201804 kb
Host smart-75adc42d-6b01-40e7-a0fb-8d548dd5d33e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=285208726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fixe
d.285208726
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.1229424358
Short name T451
Test name
Test status
Simulation time 586772801906 ps
CPU time 373.63 seconds
Started Jun 11 03:51:16 PM PDT 24
Finished Jun 11 03:57:31 PM PDT 24
Peak memory 201796 kb
Host smart-9d7c2c13-4186-40e5-8459-3fe2e0b1faf3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229424358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.1229424358
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.3611977698
Short name T198
Test name
Test status
Simulation time 110876433243 ps
CPU time 406.53 seconds
Started Jun 11 03:51:17 PM PDT 24
Finished Jun 11 03:58:05 PM PDT 24
Peak memory 202116 kb
Host smart-ac7f875c-57e4-4ee8-b697-55a2ee8157e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611977698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.3611977698
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.1875342056
Short name T515
Test name
Test status
Simulation time 33842178169 ps
CPU time 18.93 seconds
Started Jun 11 03:51:16 PM PDT 24
Finished Jun 11 03:51:36 PM PDT 24
Peak memory 201632 kb
Host smart-db02cb0b-6461-40a1-ab56-f90437a2a915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875342056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.1875342056
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.391062943
Short name T400
Test name
Test status
Simulation time 5118691466 ps
CPU time 12.88 seconds
Started Jun 11 03:51:17 PM PDT 24
Finished Jun 11 03:51:31 PM PDT 24
Peak memory 201608 kb
Host smart-31927bd6-9663-4418-9059-d54020d27d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391062943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.391062943
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.2128033454
Short name T529
Test name
Test status
Simulation time 6029879788 ps
CPU time 4.95 seconds
Started Jun 11 03:51:06 PM PDT 24
Finished Jun 11 03:51:12 PM PDT 24
Peak memory 201660 kb
Host smart-67f89fbd-11a8-4c05-aadc-9ba52b57fd63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128033454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.2128033454
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.1054941940
Short name T629
Test name
Test status
Simulation time 241557885253 ps
CPU time 1116.12 seconds
Started Jun 11 03:51:18 PM PDT 24
Finished Jun 11 04:09:56 PM PDT 24
Peak memory 202132 kb
Host smart-c52f72a8-ec1d-4ff0-81ff-5205b09bfbee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054941940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.1054941940
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.2676381804
Short name T331
Test name
Test status
Simulation time 72415760345 ps
CPU time 174.67 seconds
Started Jun 11 03:51:18 PM PDT 24
Finished Jun 11 03:54:14 PM PDT 24
Peak memory 210056 kb
Host smart-5157647e-f468-4c52-a438-7d2379bab504
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676381804 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.2676381804
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.2148667866
Short name T404
Test name
Test status
Simulation time 315857342 ps
CPU time 0.78 seconds
Started Jun 11 03:44:43 PM PDT 24
Finished Jun 11 03:44:45 PM PDT 24
Peak memory 201528 kb
Host smart-9107b1a7-d65a-4a02-a99b-c3502fa95154
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148667866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.2148667866
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.391358850
Short name T693
Test name
Test status
Simulation time 540708531198 ps
CPU time 1305.66 seconds
Started Jun 11 03:44:36 PM PDT 24
Finished Jun 11 04:06:23 PM PDT 24
Peak memory 201812 kb
Host smart-e230e6b4-2c5d-43d7-afb0-34425ebf6153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391358850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.391358850
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.871718283
Short name T180
Test name
Test status
Simulation time 489813680995 ps
CPU time 266.75 seconds
Started Jun 11 03:44:35 PM PDT 24
Finished Jun 11 03:49:03 PM PDT 24
Peak memory 201872 kb
Host smart-adde1a8a-344e-49be-92d4-19ecd1b142be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871718283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.871718283
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.3508276917
Short name T643
Test name
Test status
Simulation time 166061153074 ps
CPU time 399.03 seconds
Started Jun 11 03:44:38 PM PDT 24
Finished Jun 11 03:51:18 PM PDT 24
Peak memory 201820 kb
Host smart-5f2be911-9a77-4f82-ad3a-32d1032627d2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508276917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.3508276917
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.1516410769
Short name T608
Test name
Test status
Simulation time 161645177924 ps
CPU time 187.04 seconds
Started Jun 11 03:44:36 PM PDT 24
Finished Jun 11 03:47:44 PM PDT 24
Peak memory 201836 kb
Host smart-10ec27f4-38e9-40db-b302-4dd6a3cc8066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516410769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.1516410769
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.2576970335
Short name T636
Test name
Test status
Simulation time 500126465968 ps
CPU time 290.2 seconds
Started Jun 11 03:44:35 PM PDT 24
Finished Jun 11 03:49:26 PM PDT 24
Peak memory 201796 kb
Host smart-b9cf1b8d-d126-49ed-a725-1f9532cfcab0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576970335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.2576970335
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.3048209985
Short name T249
Test name
Test status
Simulation time 171897446469 ps
CPU time 96.84 seconds
Started Jun 11 03:44:37 PM PDT 24
Finished Jun 11 03:46:15 PM PDT 24
Peak memory 201884 kb
Host smart-9490eb69-7a19-4234-9971-4d7a53ca748f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048209985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.3048209985
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.2675059165
Short name T136
Test name
Test status
Simulation time 563399604510 ps
CPU time 807.05 seconds
Started Jun 11 03:44:35 PM PDT 24
Finished Jun 11 03:58:03 PM PDT 24
Peak memory 201824 kb
Host smart-c41b2f1b-c580-4e8f-a5ae-fcc90e0fc396
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675059165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.2675059165
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.1467390698
Short name T550
Test name
Test status
Simulation time 98744957103 ps
CPU time 330.75 seconds
Started Jun 11 03:44:35 PM PDT 24
Finished Jun 11 03:50:07 PM PDT 24
Peak memory 202096 kb
Host smart-2a16c3f6-0eb5-442e-9f87-3dac5db6116a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467390698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.1467390698
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.3776773909
Short name T477
Test name
Test status
Simulation time 22439106089 ps
CPU time 27.53 seconds
Started Jun 11 03:44:37 PM PDT 24
Finished Jun 11 03:45:06 PM PDT 24
Peak memory 201644 kb
Host smart-3615b299-7d03-49a8-bcd4-965c0ff39a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776773909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.3776773909
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.3131044591
Short name T91
Test name
Test status
Simulation time 4380263629 ps
CPU time 10.64 seconds
Started Jun 11 03:44:36 PM PDT 24
Finished Jun 11 03:44:48 PM PDT 24
Peak memory 201640 kb
Host smart-f3632d39-0676-4851-9559-833fb705b769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131044591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.3131044591
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.2860820477
Short name T720
Test name
Test status
Simulation time 5778025097 ps
CPU time 3.41 seconds
Started Jun 11 03:44:37 PM PDT 24
Finished Jun 11 03:44:42 PM PDT 24
Peak memory 201640 kb
Host smart-bdf01b4d-9960-40d8-a737-5d13d2cd7baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860820477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.2860820477
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.2783152921
Short name T742
Test name
Test status
Simulation time 166949636037 ps
CPU time 188.03 seconds
Started Jun 11 03:44:37 PM PDT 24
Finished Jun 11 03:47:47 PM PDT 24
Peak memory 201852 kb
Host smart-f75f2e0e-b3a9-43a4-98da-bd0dde62facb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783152921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
2783152921
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.3546571462
Short name T635
Test name
Test status
Simulation time 89213170753 ps
CPU time 97.84 seconds
Started Jun 11 03:44:38 PM PDT 24
Finished Jun 11 03:46:17 PM PDT 24
Peak memory 210176 kb
Host smart-a0b8a470-5326-4d03-80c8-a3972fe32c26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546571462 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.3546571462
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.1996170670
Short name T713
Test name
Test status
Simulation time 478062802 ps
CPU time 1.59 seconds
Started Jun 11 03:44:42 PM PDT 24
Finished Jun 11 03:44:45 PM PDT 24
Peak memory 201496 kb
Host smart-061f087c-48f0-45ae-af43-99776191e14e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996170670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.1996170670
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.3098314109
Short name T508
Test name
Test status
Simulation time 200756129403 ps
CPU time 432.79 seconds
Started Jun 11 03:44:48 PM PDT 24
Finished Jun 11 03:52:02 PM PDT 24
Peak memory 201884 kb
Host smart-f89da5d2-594f-4070-9673-28070d373035
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098314109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.3098314109
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.3639293539
Short name T242
Test name
Test status
Simulation time 510055728459 ps
CPU time 1209.86 seconds
Started Jun 11 03:44:45 PM PDT 24
Finished Jun 11 04:04:57 PM PDT 24
Peak memory 201916 kb
Host smart-319698b4-eb6d-4981-93cb-47fa25699ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639293539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.3639293539
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.2792308307
Short name T478
Test name
Test status
Simulation time 167878018046 ps
CPU time 405.11 seconds
Started Jun 11 03:44:42 PM PDT 24
Finished Jun 11 03:51:28 PM PDT 24
Peak memory 201816 kb
Host smart-898a98c8-fc50-4280-a5d4-3262ff16cfdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792308307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.2792308307
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.2662439743
Short name T366
Test name
Test status
Simulation time 494148905055 ps
CPU time 546.47 seconds
Started Jun 11 03:44:42 PM PDT 24
Finished Jun 11 03:53:50 PM PDT 24
Peak memory 201800 kb
Host smart-3ef06897-09b9-4052-a968-8af65bbdd2c2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662439743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.2662439743
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.4119775834
Short name T134
Test name
Test status
Simulation time 331128620534 ps
CPU time 190.48 seconds
Started Jun 11 03:44:43 PM PDT 24
Finished Jun 11 03:47:55 PM PDT 24
Peak memory 201828 kb
Host smart-a82a7dc8-8242-479d-bbc3-019d9df2a08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119775834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.4119775834
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.3182644416
Short name T485
Test name
Test status
Simulation time 333404487091 ps
CPU time 184.49 seconds
Started Jun 11 03:44:44 PM PDT 24
Finished Jun 11 03:47:50 PM PDT 24
Peak memory 201724 kb
Host smart-8bab2292-240b-454e-aeca-e18d39f97e6c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182644416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.3182644416
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.1055081398
Short name T325
Test name
Test status
Simulation time 533095033321 ps
CPU time 1004.53 seconds
Started Jun 11 03:44:42 PM PDT 24
Finished Jun 11 04:01:28 PM PDT 24
Peak memory 201832 kb
Host smart-aaa2bf70-7098-4070-825f-6803821f9830
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055081398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.1055081398
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.1369270367
Short name T623
Test name
Test status
Simulation time 604954803765 ps
CPU time 125.34 seconds
Started Jun 11 03:44:43 PM PDT 24
Finished Jun 11 03:46:49 PM PDT 24
Peak memory 201804 kb
Host smart-73203c01-9e47-4a5f-9871-a7509ad8ff16
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369270367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.1369270367
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.1227493342
Short name T746
Test name
Test status
Simulation time 66276272592 ps
CPU time 389.41 seconds
Started Jun 11 03:44:45 PM PDT 24
Finished Jun 11 03:51:16 PM PDT 24
Peak memory 202152 kb
Host smart-96992405-5d26-4e2f-9901-3570da99b977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227493342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.1227493342
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.1319261122
Short name T553
Test name
Test status
Simulation time 32364036912 ps
CPU time 19.82 seconds
Started Jun 11 03:44:48 PM PDT 24
Finished Jun 11 03:45:09 PM PDT 24
Peak memory 201624 kb
Host smart-f2c4efc4-0469-4b07-8dfa-4dab5729d7d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319261122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.1319261122
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.2751942836
Short name T497
Test name
Test status
Simulation time 3999759434 ps
CPU time 9.68 seconds
Started Jun 11 03:44:44 PM PDT 24
Finished Jun 11 03:44:56 PM PDT 24
Peak memory 201632 kb
Host smart-772ff02a-4d16-4c29-8063-eb8ac28a32e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751942836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.2751942836
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.3894409400
Short name T651
Test name
Test status
Simulation time 5847610705 ps
CPU time 7.38 seconds
Started Jun 11 03:44:44 PM PDT 24
Finished Jun 11 03:44:53 PM PDT 24
Peak memory 201652 kb
Host smart-5310cf22-996a-46e7-bf51-aa3ae96078d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894409400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.3894409400
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.808911297
Short name T467
Test name
Test status
Simulation time 24444414494 ps
CPU time 57.55 seconds
Started Jun 11 03:44:42 PM PDT 24
Finished Jun 11 03:45:41 PM PDT 24
Peak memory 201564 kb
Host smart-3bd015c7-eefe-4321-92f9-ec72a71a5ebf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808911297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.808911297
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.2746116598
Short name T767
Test name
Test status
Simulation time 809068480084 ps
CPU time 216.43 seconds
Started Jun 11 03:44:43 PM PDT 24
Finished Jun 11 03:48:20 PM PDT 24
Peak memory 210108 kb
Host smart-e5962305-244d-46f8-a700-ef53e33ff5ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746116598 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.2746116598
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.3884234549
Short name T780
Test name
Test status
Simulation time 429556986 ps
CPU time 0.81 seconds
Started Jun 11 03:44:43 PM PDT 24
Finished Jun 11 03:44:45 PM PDT 24
Peak memory 201512 kb
Host smart-155b4878-86eb-4859-986e-90e760655a32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884234549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.3884234549
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.4074634862
Short name T605
Test name
Test status
Simulation time 341393326389 ps
CPU time 798.95 seconds
Started Jun 11 03:44:43 PM PDT 24
Finished Jun 11 03:58:03 PM PDT 24
Peak memory 201800 kb
Host smart-f67e9042-c428-4e5d-8dee-327df3e018da
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074634862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.4074634862
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.182477939
Short name T783
Test name
Test status
Simulation time 553013148326 ps
CPU time 1505.39 seconds
Started Jun 11 03:44:46 PM PDT 24
Finished Jun 11 04:09:53 PM PDT 24
Peak memory 201860 kb
Host smart-955a0f41-a279-46d4-b401-fff2ad1b148f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182477939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.182477939
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.2816008813
Short name T253
Test name
Test status
Simulation time 167033859680 ps
CPU time 389.2 seconds
Started Jun 11 03:44:45 PM PDT 24
Finished Jun 11 03:51:16 PM PDT 24
Peak memory 201880 kb
Host smart-00e02cb9-eeb0-4e0f-8266-4e63ddb0ebda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816008813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.2816008813
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.2150950533
Short name T738
Test name
Test status
Simulation time 324715242737 ps
CPU time 204.13 seconds
Started Jun 11 03:44:46 PM PDT 24
Finished Jun 11 03:48:12 PM PDT 24
Peak memory 201764 kb
Host smart-abcfb877-7467-4401-9b98-e84c3964cd18
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150950533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.2150950533
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.1487093872
Short name T498
Test name
Test status
Simulation time 163316820676 ps
CPU time 217.4 seconds
Started Jun 11 03:44:45 PM PDT 24
Finished Jun 11 03:48:25 PM PDT 24
Peak memory 201816 kb
Host smart-e3e15b23-c95f-478c-ba4e-fce9189b5f64
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487093872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.1487093872
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.11845306
Short name T273
Test name
Test status
Simulation time 644578752395 ps
CPU time 1410.41 seconds
Started Jun 11 03:44:45 PM PDT 24
Finished Jun 11 04:08:18 PM PDT 24
Peak memory 201840 kb
Host smart-786c37af-e62f-404c-ba5d-b8e9f2610b8a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11845306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_wa
keup.11845306
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.2611843791
Short name T472
Test name
Test status
Simulation time 208736038729 ps
CPU time 456.58 seconds
Started Jun 11 03:44:43 PM PDT 24
Finished Jun 11 03:52:21 PM PDT 24
Peak memory 201820 kb
Host smart-af1db666-d3a2-4854-9897-973295491587
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611843791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.2611843791
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.3294853363
Short name T347
Test name
Test status
Simulation time 67164408532 ps
CPU time 257.45 seconds
Started Jun 11 03:44:42 PM PDT 24
Finished Jun 11 03:49:01 PM PDT 24
Peak memory 202160 kb
Host smart-bdebed08-0c18-46bb-9ab7-988b721ffd14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294853363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.3294853363
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.3154020772
Short name T406
Test name
Test status
Simulation time 23082385558 ps
CPU time 52.87 seconds
Started Jun 11 03:44:43 PM PDT 24
Finished Jun 11 03:45:37 PM PDT 24
Peak memory 201592 kb
Host smart-82a8af7b-fdf3-4e8c-93d2-a365c5aa4a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154020772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.3154020772
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.3985825090
Short name T372
Test name
Test status
Simulation time 3198766142 ps
CPU time 4.14 seconds
Started Jun 11 03:44:44 PM PDT 24
Finished Jun 11 03:44:50 PM PDT 24
Peak memory 201664 kb
Host smart-cc81d3a5-e4b6-48c2-9928-959c05154204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985825090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.3985825090
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.2447242620
Short name T714
Test name
Test status
Simulation time 5791134444 ps
CPU time 13.85 seconds
Started Jun 11 03:44:45 PM PDT 24
Finished Jun 11 03:45:01 PM PDT 24
Peak memory 201632 kb
Host smart-cd1d9eec-dd2d-4013-850e-eda323362513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447242620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.2447242620
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.816933938
Short name T44
Test name
Test status
Simulation time 494052630457 ps
CPU time 1061.87 seconds
Started Jun 11 03:44:46 PM PDT 24
Finished Jun 11 04:02:30 PM PDT 24
Peak memory 210356 kb
Host smart-28731777-058b-4b72-b73b-2cbbf0c98208
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816933938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.816933938
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.1842721936
Short name T248
Test name
Test status
Simulation time 124572381582 ps
CPU time 179.77 seconds
Started Jun 11 03:44:45 PM PDT 24
Finished Jun 11 03:47:47 PM PDT 24
Peak memory 210636 kb
Host smart-5ecf37d9-f171-4bdf-bdc5-c5e30355c6ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842721936 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.1842721936
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.2704488236
Short name T545
Test name
Test status
Simulation time 455760253 ps
CPU time 0.68 seconds
Started Jun 11 03:44:49 PM PDT 24
Finished Jun 11 03:44:50 PM PDT 24
Peak memory 200792 kb
Host smart-36afaa15-2a3f-48dd-ad39-45f4ce970dcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704488236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.2704488236
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.3671709705
Short name T302
Test name
Test status
Simulation time 328736709046 ps
CPU time 175.25 seconds
Started Jun 11 03:44:47 PM PDT 24
Finished Jun 11 03:47:44 PM PDT 24
Peak memory 201824 kb
Host smart-4526cd6f-724e-45f3-884e-5d9b7c13d42e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671709705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.3671709705
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.1910281572
Short name T265
Test name
Test status
Simulation time 329926085256 ps
CPU time 411.58 seconds
Started Jun 11 03:44:43 PM PDT 24
Finished Jun 11 03:51:36 PM PDT 24
Peak memory 201824 kb
Host smart-e7eed0bd-8487-4565-8654-01d7c552f5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910281572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.1910281572
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.3611419089
Short name T254
Test name
Test status
Simulation time 164409348545 ps
CPU time 100.99 seconds
Started Jun 11 03:44:46 PM PDT 24
Finished Jun 11 03:46:29 PM PDT 24
Peak memory 201852 kb
Host smart-46e6900f-fb3e-4311-9e43-eef60358203b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611419089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.3611419089
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.3309520828
Short name T560
Test name
Test status
Simulation time 330425017947 ps
CPU time 723.33 seconds
Started Jun 11 03:44:45 PM PDT 24
Finished Jun 11 03:56:50 PM PDT 24
Peak memory 201776 kb
Host smart-0680c159-d34b-4ece-b3e6-7aff6961e9b2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309520828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.3309520828
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.2738942014
Short name T703
Test name
Test status
Simulation time 330546249699 ps
CPU time 810.97 seconds
Started Jun 11 03:44:42 PM PDT 24
Finished Jun 11 03:58:13 PM PDT 24
Peak memory 201896 kb
Host smart-9a6c8358-fa53-4670-86d6-870559e8f9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738942014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.2738942014
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.3059111120
Short name T634
Test name
Test status
Simulation time 165224516095 ps
CPU time 198.15 seconds
Started Jun 11 03:44:48 PM PDT 24
Finished Jun 11 03:48:07 PM PDT 24
Peak memory 201788 kb
Host smart-97b1b387-04e1-49c3-8bb1-5aad5278ea6a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059111120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.3059111120
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.3215510728
Short name T552
Test name
Test status
Simulation time 269935470651 ps
CPU time 104.86 seconds
Started Jun 11 03:44:44 PM PDT 24
Finished Jun 11 03:46:30 PM PDT 24
Peak memory 201904 kb
Host smart-53db7d22-cb48-4050-ab7c-45abf85cd1be
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215510728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.3215510728
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.541536219
Short name T396
Test name
Test status
Simulation time 603781641606 ps
CPU time 356.48 seconds
Started Jun 11 03:44:41 PM PDT 24
Finished Jun 11 03:50:39 PM PDT 24
Peak memory 201760 kb
Host smart-9ad7104c-cb8d-4006-877a-dd9cbef28e9e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541536219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.a
dc_ctrl_filters_wakeup_fixed.541536219
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.3207569740
Short name T207
Test name
Test status
Simulation time 124145003129 ps
CPU time 668.36 seconds
Started Jun 11 03:44:46 PM PDT 24
Finished Jun 11 03:55:57 PM PDT 24
Peak memory 202184 kb
Host smart-ed45c859-7f9e-47b3-917d-2a8ea695bf4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207569740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.3207569740
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.2440200955
Short name T567
Test name
Test status
Simulation time 45728539553 ps
CPU time 104.59 seconds
Started Jun 11 03:44:49 PM PDT 24
Finished Jun 11 03:46:34 PM PDT 24
Peak memory 200836 kb
Host smart-b01d168f-5127-406b-a128-8867df6f367a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440200955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.2440200955
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.691874401
Short name T474
Test name
Test status
Simulation time 4718762568 ps
CPU time 11.49 seconds
Started Jun 11 03:44:45 PM PDT 24
Finished Jun 11 03:44:59 PM PDT 24
Peak memory 201536 kb
Host smart-63de068b-583d-4c2e-9114-eba0af671626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691874401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.691874401
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.3660396314
Short name T562
Test name
Test status
Simulation time 5722613464 ps
CPU time 14.67 seconds
Started Jun 11 03:44:45 PM PDT 24
Finished Jun 11 03:45:02 PM PDT 24
Peak memory 201648 kb
Host smart-1c00410f-4af8-42da-82a2-061892390564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660396314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.3660396314
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.3258178979
Short name T285
Test name
Test status
Simulation time 336189229562 ps
CPU time 844.68 seconds
Started Jun 11 03:44:48 PM PDT 24
Finished Jun 11 03:58:54 PM PDT 24
Peak memory 201848 kb
Host smart-91d684c4-fcff-4f96-a574-22885cad603e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258178979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
3258178979
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.3334844547
Short name T24
Test name
Test status
Simulation time 84558965312 ps
CPU time 186.73 seconds
Started Jun 11 03:44:47 PM PDT 24
Finished Jun 11 03:47:56 PM PDT 24
Peak memory 210612 kb
Host smart-dc3d8731-a895-4ecd-9712-fb22b7cf02a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334844547 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.3334844547
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.3294652418
Short name T698
Test name
Test status
Simulation time 476607494 ps
CPU time 1.67 seconds
Started Jun 11 03:44:53 PM PDT 24
Finished Jun 11 03:44:56 PM PDT 24
Peak memory 200816 kb
Host smart-4c7ef300-a815-4ef8-8b1d-55465b5b2a6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294652418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.3294652418
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.2695646122
Short name T772
Test name
Test status
Simulation time 524303006274 ps
CPU time 672.93 seconds
Started Jun 11 03:44:51 PM PDT 24
Finished Jun 11 03:56:06 PM PDT 24
Peak memory 201864 kb
Host smart-d2be00d5-9726-4777-9fe8-97a68e19cb80
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695646122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.2695646122
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.722190234
Short name T415
Test name
Test status
Simulation time 333147061352 ps
CPU time 152.53 seconds
Started Jun 11 03:44:50 PM PDT 24
Finished Jun 11 03:47:24 PM PDT 24
Peak memory 201812 kb
Host smart-ef5b7cfa-aa01-47a8-be96-19ed654e03e4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=722190234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt
_fixed.722190234
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.2773207265
Short name T609
Test name
Test status
Simulation time 331967897959 ps
CPU time 835.61 seconds
Started Jun 11 03:44:47 PM PDT 24
Finished Jun 11 03:58:44 PM PDT 24
Peak memory 201900 kb
Host smart-eefb2744-13a4-4866-9406-2a094fcbd920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773207265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.2773207265
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.3208989998
Short name T519
Test name
Test status
Simulation time 488012916375 ps
CPU time 426.56 seconds
Started Jun 11 03:44:47 PM PDT 24
Finished Jun 11 03:51:55 PM PDT 24
Peak memory 201868 kb
Host smart-8b0d28dc-d5be-41bd-9fcc-ab4588460f5d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208989998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.3208989998
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.1885036140
Short name T543
Test name
Test status
Simulation time 201779091283 ps
CPU time 470.32 seconds
Started Jun 11 03:44:53 PM PDT 24
Finished Jun 11 03:52:45 PM PDT 24
Peak memory 201820 kb
Host smart-277e2ffb-6ac9-488d-b59f-5378b183502c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885036140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.1885036140
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.2631985942
Short name T514
Test name
Test status
Simulation time 203813629811 ps
CPU time 505.12 seconds
Started Jun 11 03:44:49 PM PDT 24
Finished Jun 11 03:53:16 PM PDT 24
Peak memory 201760 kb
Host smart-5061496c-67aa-4c82-a000-16c23d667c48
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631985942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.2631985942
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.3611033951
Short name T665
Test name
Test status
Simulation time 80044810056 ps
CPU time 271.7 seconds
Started Jun 11 03:45:00 PM PDT 24
Finished Jun 11 03:49:33 PM PDT 24
Peak memory 202044 kb
Host smart-28731916-fa86-48e0-bd90-b7fb7e7b6ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611033951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.3611033951
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.3094499847
Short name T518
Test name
Test status
Simulation time 35633714937 ps
CPU time 15.65 seconds
Started Jun 11 03:44:50 PM PDT 24
Finished Jun 11 03:45:07 PM PDT 24
Peak memory 201636 kb
Host smart-d4bb6997-948d-4150-86b6-950ea5158936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094499847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.3094499847
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.1063212426
Short name T627
Test name
Test status
Simulation time 3646181311 ps
CPU time 8.98 seconds
Started Jun 11 03:44:53 PM PDT 24
Finished Jun 11 03:45:03 PM PDT 24
Peak memory 200912 kb
Host smart-b78bc300-3e17-4b62-b4c1-a36a3625ab68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063212426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.1063212426
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.2378174924
Short name T103
Test name
Test status
Simulation time 5801981244 ps
CPU time 7.87 seconds
Started Jun 11 03:44:47 PM PDT 24
Finished Jun 11 03:44:57 PM PDT 24
Peak memory 201664 kb
Host smart-9d1c04b9-f216-41d4-ba2b-35587f13d57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378174924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.2378174924
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.903242015
Short name T201
Test name
Test status
Simulation time 348174467248 ps
CPU time 453.42 seconds
Started Jun 11 03:44:51 PM PDT 24
Finished Jun 11 03:52:26 PM PDT 24
Peak memory 202144 kb
Host smart-8bb3afdd-5ad9-4a8b-b0b5-cc42a849a0c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903242015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.903242015
Directory /workspace/9.adc_ctrl_stress_all/latest
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