Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7571	1			T3	9		T9	65		T11	22
testmodes[AdcCtrlTestmodeNormal]	5831	1			T1	1		T2	1		T3	10
testmodes[AdcCtrlTestmodeLowpower]	6042	1			T2	1		T9	71		T10	14
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	4110	1			T3	4		T9	24		T11	19
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1834	1			T3	5		T9	18		T11	1
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1514	1			T9	23		T11	1		T45	20
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1848	1			T3	5		T9	18		T11	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2144	1			T3	4		T7	1		T8	2
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1491	1			T9	22		T10	2		T11	2
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1501	1			T9	23		T11	2		T45	18
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1500	1			T2	1		T9	22		T10	2
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2805	1			T9	25		T10	12		T11	4