Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27253

1

T1

1

T2

32

T3

19

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21713

1

T1

1

T2

11

T3

19

auto[ADC_CTRL_FILTER_COND_OUT]

5540

1

T2

21

T6

1

T7

24

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21185

1

T1

1

T2

21

T3

19

auto[1]

6068

1

T2

11

T7

24

T8

27

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23424

1

T1

1

T2

16

T3

19

auto[1]

3829

1

T2

16

T7

22

T8

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	20	1			T187	20		-	-		-	-
values[0]	65	1			T188	1		T189	19		T146	16
values[1]	631	1			T1	1		T8	4		T104	33
values[2]	637	1			T8	25		T45	19		T122	2
values[3]	868	1			T10	22		T40	29		T113	11
values[4]	719	1			T190	3		T80	21		T191	1
values[5]	459	1			T14	2		T113	2		T105	1
values[6]	601	1			T6	1		T14	22		T40	25
values[7]	673	1			T2	21		T11	3		T28	2
values[8]	571	1			T2	11		T14	2		T28	5
values[9]	3485	1			T7	24		T10	8		T13	39
minimum	18524	1			T3	19		T9	194		T10	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	858	1			T1	1		T8	4		T104	22
values[1]	3005	1			T7	24		T8	25		T13	39
values[2]	700	1			T10	22		T113	11		T80	46
values[3]	759	1			T14	2		T190	3		T35	14
values[4]	433	1			T113	2		T105	1		T192	15
values[5]	645	1			T6	1		T14	22		T40	25
values[6]	600	1			T2	21		T11	3		T28	2
values[7]	652	1			T2	11		T14	2		T15	6
values[8]	790	1			T10	8		T113	6		T36	7
values[9]	269	1			T41	6		T104	9		T34	1
minimum	18542	1			T3	19		T9	194		T10	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23273

1

T1

1

T2

18

T3

19

auto[1]

3980

1

T2

14

T8

14

T10

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T1	1		T8	2		T33	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T104	9		T193	15		T194	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T8	15		T40	13		T45	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1519	1			T7	2		T13	39		T104	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T10	13		T113	4		T80	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T80	11		T191	1		T195	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T14	1		T190	3		T35	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T36	1		T124	3		T112	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T113	1		T105	1		T192	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T140	1		T111	1		T196	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T40	14		T33	15		T197	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T6	1		T14	14		T108	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T28	1		T40	13		T105	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T2	11		T11	2		T35	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T2	5		T14	1		T28	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T15	1		T80	13		T35	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T113	4		T36	5		T110	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T10	3		T154	5		T198	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T34	1		T199	5		T194	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T41	6		T104	9		T110	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18393	1			T3	19		T9	194		T10	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T8	2		T122	1		T200	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T104	13		T193	16		T194	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T8	10		T40	16		T45	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1052	1			T7	22		T104	10		T82	38
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T10	9		T113	7		T80	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T80	10		T195	2		T177	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T14	1		T35	8		T167	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T124	11		T125	1		T115	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T113	1		T192	14		T159	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T111	2		T201	2		T48	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T40	11		T33	18		T122	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T14	8		T108	12		T199	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T28	1		T40	13		T105	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T2	10		T11	1		T202	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T2	6		T14	1		T200	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T15	5		T80	11		T35	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T113	2		T36	2		T114	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T10	5		T154	14		T198	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T194	1		T203	11		T204	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T205	9		T206	3		T21	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T11	1		T35	1		T33	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T187	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T189	10		T146	16		T207	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T188	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T1	1		T8	2		T33	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T104	10		T193	15		T194	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T8	15		T45	9		T122	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T208	1		T37	4		T186	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T10	13		T40	13		T113	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T108	16		T167	14		T124	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T190	3		T192	1		T167	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T80	11		T191	1		T36	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T14	1		T113	1		T105	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T140	1		T111	1		T209	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T40	14		T197	3		T106	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T6	1		T14	14		T108	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T28	1		T33	15		T122	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T2	11		T11	2		T35	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T2	5		T14	1		T28	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T80	13		T108	12		T106	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	350	1			T113	4		T34	1		T199	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1689	1			T7	2		T10	3		T13	39
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18382	1			T3	19		T9	194		T10	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T187	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T189	9		T207	5		T210	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T8	2		T200	5		T124	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T104	23		T193	16		T194	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T8	10		T45	10		T122	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T208	1		T37	2		T186	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T10	9		T40	16		T113	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T108	12		T167	15		T124	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T192	14		T167	1		T46	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T80	10		T115	10		T211	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T14	1		T113	1		T35	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T111	2		T201	2		T48	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T40	11		T106	11		T107	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T14	8		T108	12		T199	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T28	1		T33	18		T122	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T2	10		T11	1		T36	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T2	6		T14	1		T40	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T80	11		T108	13		T106	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T113	2		T36	2		T194	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1176	1			T7	22		T10	5		T15	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T11	1		T35	1		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T1	1		T8	4		T33	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T104	14		T193	17		T194	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T8	11		T40	17		T45	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1379	1			T7	24		T13	3		T104	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T10	11		T113	8		T80	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T80	11		T191	1		T195	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T14	2		T190	1		T35	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T36	1		T124	12		T112	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T113	2		T105	1		T192	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T140	1		T111	3		T196	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T40	12		T33	19		T197	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T6	1		T14	9		T108	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T28	2		T40	14		T105	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T2	11		T11	3		T35	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T2	7		T14	2		T28	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T15	6		T80	12		T35	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T113	3		T36	5		T110	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T10	7		T154	15		T198	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T34	1		T199	1		T194	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T41	1		T104	1		T110	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18532	1			T3	19		T9	194		T10	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T121	9		T200	5		T212	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T104	8		T193	14		T194	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T8	14		T40	12		T45	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1192	1			T13	36		T213	22		T81	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T10	11		T113	3		T80	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T80	10		T214	2		T215	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T190	2		T35	3		T46	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T124	2		T115	14		T211	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T159	7		T216	6		T117	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T159	12		T217	8		T218	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T40	13		T33	14		T197	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T14	13		T108	11		T199	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T40	12		T105	2		T154	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T2	10		T202	9		T38	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T2	4		T28	4		T200	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T80	12		T35	1		T108	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T113	3		T36	2		T110	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T10	1		T154	4		T198	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T199	4		T219	16		T220	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T41	5		T104	8		T110	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T221	10		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T187	9		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T189	10		T146	1		T207	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T188	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T1	1		T8	4		T33	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T104	25		T193	17		T194	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T8	11		T45	11		T122	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T208	2		T37	3		T186	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T10	11		T40	17		T113	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T108	13		T167	16		T124	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T190	1		T192	15		T167	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T80	11		T191	1		T36	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T14	2		T113	2		T105	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T140	1		T111	3		T209	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T40	12		T197	1		T106	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T6	1		T14	9		T108	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T28	2		T33	19		T122	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T2	11		T11	3		T35	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T2	7		T14	2		T28	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T80	12		T108	14		T106	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	350	1			T113	3		T34	1		T199	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1541	1			T7	24		T10	7		T13	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18524	1			T3	19		T9	194		T10	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T187	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T189	9		T146	15		T207	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T121	9		T200	5		T124	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T104	8		T193	14		T194	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T8	14		T45	8		T131	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T37	3		T186	3		T141	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T10	11		T40	12		T113	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T108	15		T167	13		T124	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T190	2		T46	14		T110	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T80	10		T115	14		T211	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T35	3		T114	8		T159	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T222	9		T223	12		T224	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T40	13		T197	2		T125	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T14	13		T108	11		T199	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T33	14		T122	1		T154	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T2	10		T36	2		T202	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T2	4		T28	4		T40	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T80	12		T108	11		T38	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T113	3		T199	4		T36	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1324	1			T10	1		T13	36		T41	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23273

1

T1

1

T2

18

T3

19

auto[1]

auto[0]

3980

1

T2

14

T8

14

T10

12

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27253

1

T1

1

T2

32

T3

19

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23919

1

T2

32

T3

19

T6

1

auto[ADC_CTRL_FILTER_COND_OUT]

3334

1

T1

1

T10

8

T14

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20970

1

T1

1

T3

19

T9

188

auto[1]

6283

1

T2

32

T6

1

T7

24

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23424

1

T1

1

T2

16

T3

19

auto[1]

3829

1

T2

16

T7

22

T8

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	470	1			T9	6		T11	5		T45	2
values[0]	136	1			T154	13		T124	14		T225	14
values[1]	568	1			T2	21		T6	1		T10	8
values[2]	2946	1			T7	24		T13	39		T104	22
values[3]	863	1			T8	2		T113	11		T45	19
values[4]	720	1			T14	2		T41	6		T104	20
values[5]	679	1			T2	11		T28	2		T113	2
values[6]	519	1			T40	25		T113	6		T190	3
values[7]	612	1			T14	22		T40	29		T108	24
values[8]	589	1			T1	1		T10	22		T35	1
values[9]	1068	1			T8	27		T15	6		T28	5
minimum	18083	1			T3	19		T9	188		T10	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	863	1			T2	21		T6	1		T10	8
values[1]	2928	1			T7	24		T13	39		T113	11
values[2]	868	1			T8	2		T105	1		T80	21
values[3]	834	1			T14	2		T41	6		T113	2
values[4]	474	1			T28	2		T40	25		T190	3
values[5]	629	1			T2	11		T113	6		T108	25
values[6]	598	1			T14	22		T40	29		T108	24
values[7]	580	1			T1	1		T10	22		T28	5
values[8]	794	1			T8	27		T15	6		T40	26
values[9]	160	1			T226	20		T195	3		T209	1
minimum	18525	1			T3	19		T9	194		T10	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23273

1

T1

1

T2

18

T3

19

auto[1]

3980

1

T2

14

T8

14

T10

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T2	11		T6	1		T11	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T10	3		T14	1		T167	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1521	1			T7	2		T13	39		T104	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T113	4		T110	8		T19	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T8	1		T191	1		T199	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T105	1		T80	11		T18	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T41	6		T113	1		T80	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T14	1		T45	9		T104	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T28	1		T190	3		T35	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T40	14		T110	8		T111	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T2	5		T113	4		T122	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T108	12		T197	3		T167	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T14	14		T192	1		T36	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T40	13		T108	12		T122	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T10	13		T35	6		T121	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T1	1		T28	5		T35	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T8	16		T15	1		T34	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T40	13		T199	8		T172	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T227	10		T228	14		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T226	20		T195	1		T209	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18382	1			T3	19		T9	194		T10	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T229	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T2	10		T11	1		T105	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T10	5		T14	1		T167	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1095	1			T7	22		T104	13		T82	38
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T113	7		T19	5		T39	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T8	1		T199	9		T202	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T80	10		T18	4		T194	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T113	1		T80	11		T171	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T14	1		T45	10		T104	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T28	1		T35	1		T106	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T40	11		T111	2		T177	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T2	6		T113	2		T122	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T108	13		T167	1		T38	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T14	8		T192	14		T36	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T40	16		T108	12		T122	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T10	9		T35	8		T122	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T192	3		T46	2		T154	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T8	11		T15	5		T194	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T40	13		T199	6		T172	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T195	2		T230	5		T231	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T11	1		T35	1		T33	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	455	1			T9	6		T11	5		T45	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T232	1		T233	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T234	16		T235	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T154	9		T124	3		T225	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T2	11		T6	1		T11	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T10	3		T14	1		T167	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1523	1			T7	2		T13	39		T104	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T18	5		T110	8		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T8	1		T199	14		T202	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T113	4		T45	9		T105	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T41	6		T80	13		T191	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T14	1		T104	10		T33	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T2	5		T28	1		T113	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T36	1		T111	1		T177	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T113	4		T190	3		T37	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T40	14		T108	12		T167	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T14	14		T192	1		T208	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T40	13		T108	12		T197	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T10	13		T122	1		T36	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T1	1		T35	1		T122	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T8	16		T15	1		T34	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	348	1			T28	5		T40	13		T199	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17941	1			T3	19		T9	188		T10	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T236	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T234	17		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T154	4		T124	11		T118	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T2	10		T11	1		T105	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T10	5		T14	1		T167	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1107	1			T7	22		T104	13		T82	38
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T18	4		T141	1		T206	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T8	1		T199	9		T202	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T113	7		T45	10		T80	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T80	11		T141	12		T204	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T14	1		T104	10		T33	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T2	6		T28	1		T113	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T111	2		T177	12		T186	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T113	2		T37	2		T106	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T40	11		T108	13		T167	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T14	8		T192	14		T208	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T40	16		T108	12		T46	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T10	9		T122	1		T36	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T122	14		T192	3		T36	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T8	11		T15	5		T35	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T40	13		T199	6		T195	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T11	1		T35	1		T33	1