Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27253

1

T1

1

T2

32

T3

19

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24136

1

T2

32

T3

19

T7

24

auto[ADC_CTRL_FILTER_COND_OUT]

3117

1

T1

1

T6

1

T8

27

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21607

1

T3

19

T9

194

T10

21

auto[1]

5646

1

T1

1

T2

32

T6

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23424

1

T1

1

T2

16

T3

19

auto[1]

3829

1

T2

16

T7

22

T8

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	296	1			T2	21		T35	2		T122	32
values[0]	16	1			T206	15		T292	1		-	-
values[1]	658	1			T8	27		T10	22		T190	3
values[2]	834	1			T1	1		T14	22		T35	3
values[3]	829	1			T14	2		T104	11		T105	6
values[4]	2914	1			T2	11		T7	24		T13	39
values[5]	618	1			T6	1		T14	2		T15	6
values[6]	503	1			T113	2		T104	9		T33	33
values[7]	516	1			T10	8		T113	11		T36	7
values[8]	776	1			T11	3		T40	51		T34	1
values[9]	769	1			T8	2		T28	2		T113	6
minimum	18524	1			T3	19		T9	194		T10	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	698	1			T1	1		T8	27		T190	3
values[1]	757	1			T14	22		T104	11		T105	6
values[2]	767	1			T14	2		T110	10		T114	9
values[3]	2823	1			T2	11		T7	24		T13	39
values[4]	719	1			T6	1		T14	2		T15	6
values[5]	423	1			T10	8		T113	2		T33	33
values[6]	584	1			T113	11		T34	1		T36	7
values[7]	757	1			T11	3		T28	2		T40	51
values[8]	825	1			T2	21		T8	2		T113	6
values[9]	96	1			T35	2		T122	5		T286	1
minimum	18804	1			T3	19		T9	194		T10	35

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23273

1

T1

1

T2

18

T3

19

auto[1]

3980

1

T2

14

T8

14

T10

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T200	6		T47	1		T171	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T1	1		T8	16		T190	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T105	3		T35	2		T202	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T14	14		T104	1		T33	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T14	1		T114	9		T126	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T110	10		T198	1		T125	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1482	1			T2	5		T7	2		T13	39
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T28	5		T104	9		T36	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T14	1		T15	1		T40	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T6	1		T41	6		T80	25
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T10	3		T113	1		T209	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T33	15		T167	14		T106	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T36	5		T200	5		T39	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T113	4		T34	1		T195	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T40	13		T47	8		T242	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T11	2		T28	1		T40	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T2	11		T8	1		T113	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T122	13		T167	1		T46	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T286	1		T271	16		T289	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T35	2		T122	2		T257	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18472	1			T3	19		T9	194		T10	26
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T154	9		T149	1		T205	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T200	5		T171	12		T115	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T8	11		T108	12		T192	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T105	3		T35	1		T202	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T14	8		T104	10		T37	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T14	1		T268	7		T129	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T125	4		T186	2		T216	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1070	1			T2	6		T7	22		T80	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T104	13		T36	2		T256	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T14	1		T15	5		T40	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T80	21		T192	3		T208	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T10	5		T113	1		T159	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T33	18		T167	15		T106	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T36	2		T200	4		T39	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T113	7		T195	2		T19	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T40	13		T47	6		T242	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T11	1		T28	1		T40	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T2	10		T8	1		T113	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T122	14		T167	1		T46	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T289	1		T290	3		T300	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T122	3		T257	2		T120	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T10	9		T11	1		T35	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T154	4		T149	11		T205	18

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T2	11		T286	1		T203	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T35	2		T122	15		T18	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T206	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T292	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T10	13		T200	6		T107	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T8	16		T190	3		T35	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T35	2		T283	11		T171	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T1	1		T14	14		T33	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T14	1		T105	3		T202	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T104	1		T121	10		T37	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1507	1			T2	5		T7	2		T13	39
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T28	5		T104	9		T36	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T14	1		T15	1		T40	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T6	1		T41	6		T80	25
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T113	1		T104	9		T122	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T33	15		T167	14		T194	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T10	3		T36	5		T116	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T113	4		T106	1		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T40	13		T39	5		T47	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T11	2		T40	14		T34	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T8	1		T113	4		T105	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T28	1		T45	9		T167	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18382	1			T3	19		T9	194		T10	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T2	10		T203	11		T144	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T122	17		T18	4		T106	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T206	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T10	9		T200	5		T124	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T8	11		T108	12		T192	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T35	1		T283	11		T171	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T14	8		T194	17		T107	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T14	1		T105	3		T202	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T104	10		T37	2		T111	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1105	1			T2	6		T7	22		T80	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T104	13		T36	2		T256	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T14	1		T15	5		T40	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T80	21		T192	3		T208	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T113	1		T122	1		T200	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T33	18		T167	15		T194	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T10	5		T36	2		T249	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T113	7		T106	11		T154	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T40	13		T39	3		T47	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T11	1		T40	11		T35	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T8	1		T113	2		T154	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T28	1		T45	10		T167	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T11	1		T35	1		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T200	6		T47	1		T171	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T1	1		T8	13		T190	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T105	4		T35	2		T202	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T14	9		T104	11		T33	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T14	2		T114	1		T126	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T110	1		T198	1		T125	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1393	1			T2	7		T7	24		T13	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T28	1		T104	14		T36	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T14	2		T15	6		T40	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T6	1		T41	1		T80	23
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T10	7		T113	2		T209	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T33	19		T167	16		T106	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T36	5		T200	5		T39	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T113	8		T34	1		T195	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T40	14		T47	7		T242	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T11	3		T28	2		T40	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T2	11		T8	2		T113	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T122	15		T167	2		T46	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T286	1		T271	1		T289	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T35	2		T122	4		T257	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18583	1			T3	19		T9	194		T10	24
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T154	5		T149	12		T205	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T200	5		T171	15		T115	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T8	14		T190	2		T108	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T105	2		T35	1		T202	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T14	13		T121	9		T37	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T114	8		T126	10		T214	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T110	9		T125	9		T186	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1159	1			T2	4		T13	36		T213	22
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T28	4		T104	8		T36	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T40	12		T104	8		T108	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T41	5		T80	23		T301	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T10	1		T128	10		T159	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T33	14		T167	13		T38	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T36	2		T200	4		T39	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T113	3		T19	5		T126	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T40	12		T47	7		T242	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T40	13		T45	8		T35	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T2	10		T113	3		T154	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T122	12		T46	14		T199	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T271	15		T289	1		T290	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T122	1		T120	1		T163	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T10	11		T124	13		T285	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T154	8		T205	17		T258	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T2	11		T286	1		T203	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T35	2		T122	19		T18	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T206	15		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T292	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T10	11		T200	6		T107	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T8	13		T190	1		T35	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T35	2		T283	12		T171	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T1	1		T14	9		T33	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T14	2		T105	4		T202	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T104	11		T121	1		T37	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1436	1			T2	7		T7	24		T13	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T28	1		T104	14		T36	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T14	2		T15	6		T40	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T6	1		T41	1		T80	23
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T113	2		T104	1		T122	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T33	19		T167	16		T194	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T10	7		T36	5		T116	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T113	8		T106	12		T154	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T40	14		T39	7		T47	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T11	3		T40	12		T34	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T8	2		T113	3		T105	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T28	2		T45	11		T167	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18524	1			T3	19		T9	194		T10	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T2	10		T241	11		T144	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T122	13		T120	1		T302	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T10	11		T200	5		T124	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T8	14		T190	2		T108	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T35	1		T283	10		T171	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T14	13		T194	8		T130	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T105	2		T202	9		T114	24
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T121	9		T37	3		T110	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1176	1			T2	4		T13	36		T213	22
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T28	4		T104	8		T36	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T40	12		T108	15		T199	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T41	5		T80	23		T142	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T104	8		T200	4		T48	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T33	14		T167	13		T238	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T10	1		T36	2		T249	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T113	3		T38	6		T126	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T40	12		T39	1		T47	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T40	13		T35	3		T199	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T113	3		T154	4		T237	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T45	8		T46	14		T199	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23273

1

T1

1

T2

18

T3

19

auto[1]

auto[0]

3980

1

T2

14

T8

14

T10

12