Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27253

1

T1

1

T2

32

T3

19

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23677

1

T1

1

T2

21

T3

19

auto[ADC_CTRL_FILTER_COND_OUT]

3576

1

T2

11

T10

30

T14

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21151

1

T1

1

T2

11

T3

19

auto[1]

6102

1

T2

21

T6

1

T7

24

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23424

1

T1

1

T2

16

T3

19

auto[1]

3829

1

T2

16

T7

22

T8

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	708	1			T8	25		T9	6		T11	5
values[0]	54	1			T295	1		T303	2		T134	18
values[1]	629	1			T2	21		T6	1		T10	8
values[2]	3010	1			T7	24		T13	39		T113	11
values[3]	812	1			T8	2		T105	1		T80	21
values[4]	647	1			T14	2		T41	6		T45	19
values[5]	693	1			T2	11		T28	2		T113	2
values[6]	580	1			T40	25		T113	6		T108	25
values[7]	620	1			T14	22		T40	29		T108	24
values[8]	537	1			T1	1		T10	22		T35	1
values[9]	880	1			T8	2		T28	5		T40	26
minimum	18083	1			T3	19		T9	188		T10	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	528	1			T2	21		T10	8		T14	2
values[1]	3019	1			T7	24		T13	39		T113	11
values[2]	863	1			T8	2		T45	19		T105	1
values[3]	743	1			T14	2		T41	6		T113	2
values[4]	476	1			T2	11		T28	2		T40	25
values[5]	685	1			T113	6		T108	25		T197	3
values[6]	584	1			T14	22		T40	29		T108	24
values[7]	559	1			T1	1		T10	22		T28	5
values[8]	826	1			T8	27		T15	6		T40	26
values[9]	146	1			T194	2		T226	20		T230	6
minimum	18824	1			T3	19		T6	1		T9	194

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23273

1

T1

1

T2

18

T3

19

auto[1]

3980

1

T2

14

T8

14

T10

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T2	11		T105	3		T80	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T10	3		T14	1		T167	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1485	1			T7	2		T13	39		T168	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T113	4		T104	9		T108	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T8	1		T45	9		T80	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T105	1		T18	5		T194	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T113	1		T104	9		T283	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T14	1		T41	6		T104	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T28	1		T190	3		T35	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T2	5		T40	14		T36	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T113	4		T197	3		T122	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T108	12		T167	1		T208	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T14	14		T192	1		T125	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T40	13		T108	12		T122	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T1	1		T35	6		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T10	13		T28	5		T35	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T8	16		T15	1		T34	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T40	13		T199	8		T211	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T194	1		T230	1		T231	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T226	20		T222	10		T304	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18463	1			T3	19		T6	1		T9	194
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T124	3		T229	1		T206	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T2	10		T105	3		T80	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T10	5		T14	1		T167	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1036	1			T7	22		T82	38		T200	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T113	7		T104	13		T108	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T8	1		T45	10		T80	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T18	4		T194	17		T114	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T113	1		T283	11		T171	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T14	1		T104	10		T80	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T28	1		T35	1		T106	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T2	6		T40	11		T111	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T113	2		T122	3		T37	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T108	13		T167	1		T208	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T14	8		T192	14		T125	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T40	16		T108	12		T122	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T35	8		T122	1		T159	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T10	9		T192	3		T154	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T8	11		T15	5		T195	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T40	13		T199	6		T211	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T194	1		T230	5		T231	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T304	12		T240	12		T305	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T11	2		T35	1		T33	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T124	11		T206	15		T118	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	474	1			T8	15		T9	6		T11	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T199	8		T211	8		T222	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T303	2		T234	16		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T295	1		T134	18		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T2	11		T6	1		T11	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T10	3		T14	1		T167	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1498	1			T7	2		T13	39		T168	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T113	4		T104	9		T108	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T8	1		T80	11		T199	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T105	1		T18	5		T194	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T45	9		T104	9		T191	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T14	1		T41	6		T104	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T28	1		T113	1		T190	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T2	5		T36	1		T110	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T113	4		T197	3		T122	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T40	14		T108	12		T107	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T14	14		T192	1		T130	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T40	13		T108	12		T167	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T1	1		T122	1		T125	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T10	13		T35	1		T122	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T8	1		T34	1		T35	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T28	5		T40	13		T226	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17941	1			T3	19		T9	188		T10	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T8	10		T15	5		T194	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T199	6		T211	9		T304	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T234	17		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T2	10		T11	1		T105	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T10	5		T14	1		T167	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1052	1			T7	22		T82	38		T200	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T113	7		T104	13		T108	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T8	1		T80	10		T199	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T18	4		T194	17		T114	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T45	10		T283	11		T204	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T14	1		T104	10		T80	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T28	1		T113	1		T35	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T2	6		T111	2		T177	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T113	2		T122	3		T37	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T40	11		T108	13		T125	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T14	8		T192	14		T130	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T40	16		T108	12		T167	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T122	1		T125	4		T267	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T10	9		T122	14		T192	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T8	1		T35	8		T195	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T40	13		T171	2		T172	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T11	1		T35	1		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T2	11		T105	4		T80	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T10	7		T14	2		T167	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1377	1			T7	24		T13	3		T168	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T113	8		T104	14		T108	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T8	2		T45	11		T80	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T105	1		T18	9		T194	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T113	2		T104	1		T283	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T14	2		T41	1		T104	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T28	2		T190	1		T35	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T2	7		T40	12		T36	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T113	3		T197	1		T122	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T108	14		T167	2		T208	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T14	9		T192	15		T125	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T40	17		T108	13		T122	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T1	1		T35	11		T122	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T10	11		T28	1		T35	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T8	13		T15	6		T34	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T40	14		T199	7		T211	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T194	2		T230	6		T231	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T226	1		T222	1		T304	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18627	1			T3	19		T6	1		T9	194
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T124	12		T229	1		T206	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T2	10		T105	2		T80	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T10	1		T167	13		T154	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1144	1			T13	36		T213	22		T81	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T113	3		T104	8		T108	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T45	8		T80	10		T199	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T194	8		T114	16		T237	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T104	8		T283	10		T171	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T41	5		T80	12		T33	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T190	2		T35	1		T285	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T2	4		T40	13		T110	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T113	3		T197	2		T122	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T108	11		T126	10		T262	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T14	13		T125	9		T130	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T40	12		T108	11		T122	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T35	3		T159	12		T258	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T10	11		T28	4		T171	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T8	14		T121	9		T212	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T40	12		T199	7		T211	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T226	19		T222	9		T240	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T117	14		T306	8		T234	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T124	2		T118	1		T248	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	480	1			T8	11		T9	6		T11	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T199	7		T211	10		T222	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T303	2		T234	18		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T295	1		T134	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T2	11		T6	1		T11	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T10	7		T14	2		T167	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1392	1			T7	24		T13	3		T168	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T113	8		T104	14		T108	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T8	2		T80	11		T199	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T105	1		T18	9		T194	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T45	11		T104	1		T191	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T14	2		T41	1		T104	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T28	2		T113	2		T190	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T2	7		T36	1		T110	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T113	3		T197	1		T122	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T40	12		T108	14		T107	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T14	9		T192	15		T130	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T40	17		T108	13		T167	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T1	1		T122	2		T125	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T10	11		T35	1		T122	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T8	2		T34	1		T35	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T28	1		T40	14		T226	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18083	1			T3	19		T9	188		T10	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T8	14		T152	3		T144	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T199	7		T211	7		T222	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T234	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T134	17		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T2	10		T105	2		T80	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T10	1		T167	13		T154	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1158	1			T13	36		T213	22		T81	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T113	3		T104	8		T108	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T80	10		T199	13		T202	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T194	8		T114	16		T237	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T45	8		T104	8		T199	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T41	5		T80	12		T33	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T190	2		T35	1		T171	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T2	4		T110	7		T186	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T113	3		T197	2		T122	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T40	13		T108	11		T114	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T14	13		T130	11		T21	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T40	12		T108	11		T46	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T125	9		T128	10		T258	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T10	11		T122	12		T36	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T35	3		T121	9		T212	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T28	4		T40	12		T226	19

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23273

1

T1

1

T2

18

T3

19

auto[1]

auto[0]

3980

1

T2

14

T8

14

T10

12