Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27253

1

T1

1

T2

32

T3

19

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24147

1

T1

1

T2

21

T3

19

auto[ADC_CTRL_FILTER_COND_OUT]

3106

1

T2

11

T6

1

T8

29

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21496

1

T2

32

T3

19

T8

4

auto[1]

5757

1

T1

1

T6

1

T7

24

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23424

1

T1

1

T2

16

T3

19

auto[1]

3829

1

T2

16

T7

22

T8

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	249	1			T40	25		T190	3		T35	15
values[0]	26	1			T255	1		T261	25		-	-
values[1]	752	1			T14	2		T35	3		T33	33
values[2]	579	1			T2	21		T191	1		T167	29
values[3]	761	1			T8	2		T11	3		T14	24
values[4]	597	1			T8	25		T192	15		T18	9
values[5]	659	1			T10	22		T15	6		T40	26
values[6]	605	1			T1	1		T10	8		T28	2
values[7]	774	1			T2	11		T6	1		T28	5
values[8]	2899	1			T7	24		T8	2		T13	39
values[9]	828	1			T113	13		T105	6		T34	1
minimum	18524	1			T3	19		T9	194		T10	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	717	1			T2	21		T14	2		T35	3
values[1]	603	1			T41	6		T191	1		T108	25
values[2]	745	1			T8	2		T11	3		T14	24
values[3]	594	1			T8	25		T10	22		T15	6
values[4]	697	1			T1	1		T28	2		T40	26
values[5]	635	1			T6	1		T10	8		T113	6
values[6]	3033	1			T2	11		T7	24		T8	2
values[7]	554	1			T45	19		T104	9		T105	1
values[8]	866	1			T40	25		T113	13		T190	3
values[9]	95	1			T150	6		T257	1		T151	2
minimum	18714	1			T3	19		T9	194		T10	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23273

1

T1

1

T2

18

T3

19

auto[1]

3980

1

T2

14

T8

14

T10

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T2	11		T33	15		T106	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T14	1		T35	2		T167	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T41	6		T197	3		T194	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T191	1		T108	12		T46	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T80	11		T192	1		T199	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T8	1		T11	2		T14	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T80	14		T18	5		T111	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T8	15		T10	13		T15	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T1	1		T40	13		T122	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T28	1		T115	10		T196	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T113	4		T122	13		T167	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T6	1		T10	3		T80	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1535	1			T7	2		T13	39		T40	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T2	5		T8	1		T28	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T45	9		T105	1		T35	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T104	9		T208	1		T114	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T40	14		T113	1		T34	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T113	4		T190	3		T105	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T150	1		T257	1		T151	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T260	12		T307	1		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18453	1			T3	19		T9	194		T10	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T154	9		T222	9		T254	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T2	10		T33	18		T106	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T14	1		T35	1		T167	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T194	1		T186	2		T204	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T108	13		T46	2		T39	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T80	10		T192	14		T199	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T8	1		T11	1		T14	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T80	11		T18	4		T111	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T8	10		T10	9		T15	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T40	13		T122	3		T36	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T28	1		T115	10		T172	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T113	2		T122	14		T167	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T10	5		T80	11		T256	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1121	1			T7	22		T40	16		T82	38
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T2	6		T8	1		T104	23
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T45	10		T192	3		T200	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T208	1		T171	1		T115	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T40	11		T113	1		T122	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T113	7		T105	3		T35	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T150	5		T259	13		T135	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T260	8		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T11	1		T35	1		T33	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T154	4		T222	7		T224	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T40	14		T35	1		T110	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T190	3		T35	6		T108	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T261	14		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T255	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T33	15		T106	1		T194	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T14	1		T35	2		T106	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T2	11		T110	10		T194	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T191	1		T167	14		T46	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T41	6		T80	11		T197	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T8	1		T11	2		T14	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T192	1		T18	5		T193	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T8	15		T141	1		T242	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T40	13		T80	14		T122	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T10	13		T15	1		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T1	1		T113	4		T202	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T10	3		T28	1		T80	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T40	13		T108	16		T122	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T2	5		T6	1		T28	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1547	1			T7	2		T13	39		T45	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T8	1		T104	9		T33	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T113	1		T34	1		T35	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T113	4		T105	3		T121	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18382	1			T3	19		T9	194		T10	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T40	11		T203	11		T150	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T35	8		T108	12		T308	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T261	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T33	18		T106	11		T194	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T14	1		T35	1		T106	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T2	10		T194	1		T299	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T167	15		T46	2		T39	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T80	10		T199	9		T36	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T8	1		T11	1		T14	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T192	14		T18	4		T193	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T8	10		T141	1		T242	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T40	13		T80	11		T122	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T10	9		T15	5		T115	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T113	2		T202	8		T124	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T10	5		T28	1		T80	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T40	16		T108	12		T122	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T2	6		T104	23		T200	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1087	1			T7	22		T45	10		T82	38
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T8	1		T208	1		T115	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T113	1		T122	1		T200	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T113	7		T105	3		T107	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T11	1		T35	1		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T2	11		T33	19		T106	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T14	2		T35	2		T167	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T41	1		T197	1		T194	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T191	1		T108	14		T46	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T80	11		T192	15		T199	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T8	2		T11	3		T14	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T80	12		T18	9		T111	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T8	11		T10	11		T15	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T1	1		T40	14		T122	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T28	2		T115	11		T196	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T113	3		T122	15		T167	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T6	1		T10	7		T80	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1462	1			T7	24		T13	3		T40	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T2	7		T8	2		T28	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T45	11		T105	1		T35	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T104	1		T208	2		T114	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T40	12		T113	2		T34	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T113	8		T190	1		T105	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T150	6		T257	1		T151	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T260	9		T307	1		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18566	1			T3	19		T9	194		T10	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T154	5		T222	8		T254	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T2	10		T33	14		T110	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T35	1		T167	13		T154	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T41	5		T197	2		T226	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T108	11		T46	14		T110	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T80	10		T199	13		T36	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T14	13		T37	3		T19	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T80	13		T262	9		T258	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T8	14		T10	11		T242	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T40	12		T122	1		T36	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T115	9		T172	12		T130	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T113	3		T122	12		T202	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T10	1		T80	12		T256	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1194	1			T13	36		T40	12		T213	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T2	4		T28	4		T104	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T45	8		T200	5		T238	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T104	8		T114	8		T115	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T40	13		T110	7		T47	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T113	3		T190	2		T105	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T151	1		T259	9		T135	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T260	11		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T237	9		T269	9		T25	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T154	8		T222	8		T258	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T40	12		T35	1		T110	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T190	1		T35	11		T108	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T261	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T255	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T33	19		T106	12		T194	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T14	2		T35	2		T106	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T2	11		T110	1		T194	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T191	1		T167	16		T46	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T41	1		T80	11		T197	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T8	2		T11	3		T14	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T192	15		T18	9		T193	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T8	11		T141	2		T242	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T40	14		T80	12		T122	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T10	11		T15	6		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T1	1		T113	3		T202	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T10	7		T28	2		T80	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T40	17		T108	13		T122	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T2	7		T6	1		T28	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1420	1			T7	24		T13	3		T45	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T8	2		T104	1		T33	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T113	2		T34	1		T35	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T113	8		T105	4		T121	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18524	1			T3	19		T9	194		T10	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T40	13		T110	7		T270	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T190	2		T35	3		T108	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T261	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T33	14		T194	8		T237	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T35	1		T154	12		T126	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T2	10		T110	9		T226	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T167	13		T46	14		T110	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T41	5		T80	10		T197	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T14	13		T108	11		T37	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T193	14		T262	9		T258	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T8	14		T242	2		T239	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T40	12		T80	13		T122	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T10	11		T115	9		T172	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T113	3		T202	9		T124	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T10	1		T80	12		T222	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T40	12		T108	15		T122	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T2	4		T28	4		T104	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1214	1			T13	36		T45	8		T213	22
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T104	8		T115	14		T211	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T200	5		T47	7		T171	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T113	3		T105	2		T121	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23273

1

T1

1

T2

18

T3

19

auto[1]

auto[0]

3980

1

T2

14

T8

14

T10

12