Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27253

1

T1

1

T2

32

T3

19

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23585

1

T1

1

T3

19

T7

24

auto[ADC_CTRL_FILTER_COND_OUT]

3668

1

T2

32

T6

1

T8

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21226

1

T2

32

T3

19

T6

1

auto[1]

6027

1

T1

1

T7

24

T8

27

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23424

1

T1

1

T2

16

T3

19

auto[1]

3829

1

T2

16

T7

22

T8

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	273	1			T8	25		T36	1		T110	8
values[0]	27	1			T278	11		T269	15		T309	1
values[1]	618	1			T14	22		T113	2		T197	3
values[2]	624	1			T2	21		T10	30		T40	25
values[3]	724	1			T2	11		T15	6		T40	26
values[4]	575	1			T1	1		T35	1		T33	33
values[5]	2827	1			T7	24		T13	39		T168	1
values[6]	850	1			T14	2		T28	5		T80	49
values[7]	707	1			T6	1		T8	2		T11	3
values[8]	533	1			T28	2		T40	29		T104	9
values[9]	971	1			T8	2		T14	2		T113	11
minimum	18524	1			T3	19		T9	194		T10	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	629	1			T2	21		T14	22		T40	25
values[1]	598	1			T2	11		T10	30		T15	6
values[2]	712	1			T40	26		T122	27		T110	10
values[3]	2810	1			T1	1		T7	24		T13	39
values[4]	749	1			T14	2		T105	1		T80	21
values[5]	680	1			T11	3		T28	5		T80	49
values[6]	771	1			T6	1		T8	2		T28	2
values[7]	560	1			T45	19		T104	9		T34	1
values[8]	927	1			T8	27		T14	2		T113	11
values[9]	102	1			T36	7		T279	1		T258	3
minimum	18715	1			T3	19		T9	194		T10	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23273

1

T1

1

T2

18

T3

19

auto[1]

3980

1

T2

14

T8

14

T10

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T40	14		T197	3		T122	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T2	11		T14	14		T35	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T10	16		T15	1		T113	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T2	5		T41	6		T104	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T110	10		T111	1		T177	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T40	13		T122	13		T124	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1530	1			T1	1		T7	2		T13	39
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T35	1		T33	15		T208	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T105	1		T80	11		T167	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T14	1		T192	1		T194	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T11	2		T80	14		T108	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T28	5		T80	13		T108	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T40	13		T104	1		T106	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T6	1		T8	1		T28	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T121	10		T280	1		T262	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T45	9		T104	9		T34	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T8	16		T113	4		T122	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T14	1		T108	16		T36	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T36	5		T279	1		T206	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T258	3		T150	1		T284	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18443	1			T3	19		T9	194		T10	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T171	16		T203	1		T277	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T40	11		T122	1		T199	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T2	10		T14	8		T167	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T10	14		T15	5		T113	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T2	6		T104	13		T105	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T111	2		T177	12		T125	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T40	13		T122	14		T124	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1039	1			T7	22		T82	38		T281	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T33	18		T208	1		T171	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T80	10		T167	15		T199	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T14	1		T192	3		T194	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T11	1		T80	11		T108	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T80	11		T108	12		T192	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T40	16		T104	10		T106	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T8	1		T28	1		T106	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T280	12		T262	2		T127	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T45	10		T35	8		T202	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T8	11		T113	7		T122	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T14	1		T108	12		T107	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T36	2		T206	14		T310	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T150	5		T240	12		T244	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T11	1		T113	1		T35	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T171	11		T203	11		T279	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T8	15		T110	8		T311	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T36	1		T243	11		T312	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T278	11		T269	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T309	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T113	1		T197	3		T122	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T14	14		T167	1		T114	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T10	16		T40	14		T199	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T2	11		T41	6		T104	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T15	1		T113	4		T199	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T2	5		T40	13		T122	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T1	1		T140	1		T186	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T35	1		T33	15		T208	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1491	1			T7	2		T13	39		T168	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T192	1		T107	1		T47	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T80	14		T108	12		T167	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T14	1		T28	5		T80	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T11	2		T104	1		T154	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T6	1		T8	1		T191	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T40	13		T106	1		T19	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T28	1		T104	9		T190	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T8	1		T113	4		T121	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T14	1		T45	9		T108	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18382	1			T3	19		T9	194		T10	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T8	10		T313	14		T314	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T243	12		T312	5		T272	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T269	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T113	1		T122	1		T111	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T14	8		T167	1		T114	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T10	14		T40	11		T199	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T2	10		T104	13		T105	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T15	5		T113	2		T111	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T2	6		T40	13		T122	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T186	2		T211	9		T130	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T33	18		T208	1		T115	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1055	1			T7	22		T80	10		T82	38
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T192	3		T107	14		T47	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T80	11		T108	13		T167	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T14	1		T80	11		T108	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T11	1		T104	10		T154	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T8	1		T106	11		T154	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T40	16		T106	6		T19	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T28	1		T35	8		T204	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T8	1		T113	7		T122	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T14	1		T45	10		T108	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T11	1		T35	1		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T40	12		T197	1		T122	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T2	11		T14	9		T35	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T10	18		T15	6		T113	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T2	7		T41	1		T104	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T110	1		T111	3		T177	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T40	14		T122	15		T124	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1373	1			T1	1		T7	24		T13	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T35	1		T33	19		T208	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T105	1		T80	11		T167	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T14	2		T192	4		T194	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T11	3		T80	12		T108	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T28	1		T80	12		T108	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T40	17		T104	11		T106	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T6	1		T8	2		T28	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T121	1		T280	13		T262	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T45	11		T104	1		T34	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T8	13		T113	8		T122	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T14	2		T108	13		T36	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T36	5		T279	1		T206	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T258	1		T150	6		T284	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18582	1			T3	19		T9	194		T10	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T171	12		T203	12		T277	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T40	13		T197	2		T199	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T2	10		T14	13		T114	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T10	12		T113	3		T199	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T2	4		T41	5		T104	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T110	9		T172	12		T238	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T40	12		T122	12		T124	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1196	1			T13	36		T213	22		T81	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T33	14		T115	9		T212	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T80	10		T167	13		T199	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T226	19		T47	7		T283	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T80	13		T108	11		T46	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T28	4		T80	12		T108	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T40	12		T19	5		T171	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T190	2		T124	2		T226	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T121	9		T262	9		T127	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T45	8		T104	8		T35	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T8	14		T113	3		T122	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T108	15		T126	10		T256	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T36	2		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T258	2		T284	10		T240	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T241	6		T243	7		T259	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T171	15		T233	7		T315	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T8	11		T110	1		T311	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T36	1		T243	13		T312	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T278	1		T269	6		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T309	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T113	2		T197	1		T122	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T14	9		T167	2		T114	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T10	18		T40	12		T199	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T2	11		T41	1		T104	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T15	6		T113	3		T199	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T2	7		T40	14		T122	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T1	1		T140	1		T186	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T35	1		T33	19		T208	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1385	1			T7	24		T13	3		T168	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T192	4		T107	15		T47	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T80	12		T108	14		T167	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T14	2		T28	1		T80	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T11	3		T104	11		T154	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T6	1		T8	2		T191	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T40	17		T106	7		T19	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T28	2		T104	1		T190	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	315	1			T8	2		T113	8		T121	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T14	2		T45	11		T108	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18524	1			T3	19		T9	194		T10	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T8	14		T110	7		T313	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T243	10		T271	15		T151	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T278	10		T269	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T197	2		T110	7		T241	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T14	13		T114	16		T171	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T10	12		T40	13		T199	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T2	10		T41	5		T104	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T113	3		T199	4		T110	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T2	4		T40	12		T122	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T186	3		T211	7		T130	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T33	14		T115	9		T212	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1161	1			T13	36		T213	22		T80	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T47	7		T283	10		T141	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T80	13		T108	11		T167	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T28	4		T80	12		T108	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T171	7		T275	8		T248	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T154	4		T124	2		T39	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T40	12		T19	5		T262	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T104	8		T190	2		T35	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T113	3		T121	9		T122	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T45	8		T108	15		T202	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23273

1

T1

1

T2

18

T3

19

auto[1]

auto[0]

3980

1

T2

14

T8

14

T10

12