Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27253

1

T1

1

T2

32

T3

19

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24062

1

T2

11

T3

19

T6

1

auto[ADC_CTRL_FILTER_COND_OUT]

3191

1

T1

1

T2

21

T14

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21178

1

T1

1

T2

11

T3

19

auto[1]

6075

1

T2

21

T7

24

T8

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23424

1

T1

1

T2

16

T3

19

auto[1]

3829

1

T2

16

T7

22

T8

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	373	1			T8	2		T28	5		T36	6
values[0]	29	1			T104	9		T217	18		T316	1
values[1]	645	1			T10	22		T14	22		T15	6
values[2]	441	1			T2	21		T8	2		T14	2
values[3]	616	1			T1	1		T34	1		T108	24
values[4]	720	1			T10	8		T40	25		T41	6
values[5]	637	1			T113	2		T80	49		T35	1
values[6]	823	1			T8	25		T191	1		T199	5
values[7]	470	1			T121	10		T122	2		T110	8
values[8]	900	1			T11	3		T14	2		T40	29
values[9]	3075	1			T2	11		T6	1		T7	24
minimum	18524	1			T3	19		T9	194		T10	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	576	1			T2	21		T8	2		T113	11
values[1]	393	1			T1	1		T14	2		T28	2
values[2]	698	1			T40	25		T41	6		T34	1
values[3]	691	1			T10	8		T113	2		T104	11
values[4]	789	1			T8	25		T80	25		T167	2
values[5]	605	1			T191	1		T121	10		T199	5
values[6]	2891	1			T7	24		T11	3		T13	39
values[7]	761	1			T6	1		T14	2		T40	55
values[8]	936	1			T2	11		T28	5		T113	6
values[9]	150	1			T8	2		T107	1		T124	14
minimum	18763	1			T3	19		T9	194		T10	35

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23273

1

T1

1

T2

18

T3

19

auto[1]

3980

1

T2

14

T8

14

T10

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T8	1		T113	4		T108	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T2	11		T105	3		T18	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T35	8		T192	1		T194	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T1	1		T14	1		T28	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T41	6		T34	1		T108	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T40	14		T106	1		T194	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T10	3		T108	12		T46	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T113	1		T104	1		T80	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T8	15		T167	1		T107	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T80	14		T112	1		T198	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T191	1		T199	5		T106	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T121	10		T200	6		T106	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1489	1			T7	2		T11	2		T13	39
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T39	5		T209	1		T141	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T6	1		T14	1		T40	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T40	13		T208	1		T36	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T2	5		T28	5		T80	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T113	4		T45	9		T190	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T8	1		T231	1		T295	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T107	1		T124	3		T126	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18450	1			T3	19		T9	194		T10	26
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T15	1		T193	15		T48	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T8	1		T113	7		T108	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T2	10		T105	3		T18	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T35	9		T192	3		T194	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T14	1		T28	1		T200	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T108	12		T199	9		T37	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T40	11		T106	6		T194	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T10	5		T108	13		T46	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T113	1		T104	10		T80	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T8	10		T167	1		T107	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T80	11		T198	8		T125	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T106	2		T249	8		T22	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T200	5		T106	11		T230	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1082	1			T7	22		T11	1		T82	38
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T39	3		T141	12		T130	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T14	1		T40	13		T104	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T40	16		T208	1		T36	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T2	6		T80	10		T122	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T113	2		T45	10		T167	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T8	1		T231	7		T246	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T124	11		T149	11		T247	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T10	9		T11	1		T14	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T15	5		T193	16		T48	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T8	1		T28	5		T111	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T36	4		T107	1		T124	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T104	9		T316	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T217	9		T317	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T10	13		T14	14		T122	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T15	1		T105	3		T18	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T8	1		T113	4		T35	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T2	11		T14	1		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T34	1		T108	12		T192	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T1	1		T200	5		T241	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T10	3		T41	6		T108	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T40	14		T104	1		T106	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T167	1		T107	1		T38	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T113	1		T80	27		T35	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T8	15		T191	1		T199	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T200	6		T106	1		T211	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T122	1		T110	8		T126	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T121	10		T47	1		T209	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T11	2		T14	1		T104	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T40	13		T208	1		T36	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1556	1			T2	5		T6	1		T7	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T113	4		T45	9		T190	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18382	1			T3	19		T9	194		T10	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T8	1		T111	2		T222	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T36	2		T124	11		T280	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T217	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T10	9		T14	8		T122	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T15	5		T105	3		T18	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T8	1		T113	7		T35	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T2	10		T14	1		T28	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T108	12		T192	3		T199	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T200	4		T243	7		T129	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T10	5		T108	13		T46	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T40	11		T104	10		T106	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T167	1		T107	12		T38	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T113	1		T80	22		T111	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T8	10		T106	2		T249	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T200	5		T106	11		T211	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T122	1		T172	7		T205	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T230	5		T250	7		T223	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T11	1		T14	1		T104	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T40	16		T208	1		T36	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1114	1			T2	6		T7	22		T40	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T113	2		T45	10		T167	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T11	1		T35	1		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T8	2		T113	8		T108	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T2	11		T105	4		T18	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T35	13		T192	4		T194	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T1	1		T14	2		T28	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T41	1		T34	1		T108	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T40	12		T106	7		T194	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T10	7		T108	14		T46	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T113	2		T104	11		T80	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T8	11		T167	2		T107	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T80	12		T112	1		T198	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T191	1		T199	1		T106	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T121	1		T200	6		T106	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1406	1			T7	24		T11	3		T13	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T39	7		T209	1		T141	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T6	1		T14	2		T40	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T40	17		T208	2		T36	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T2	7		T28	1		T80	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T113	3		T45	11		T190	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T8	2		T231	8		T295	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T107	1		T124	12		T126	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18575	1			T3	19		T9	194		T10	24
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T15	6		T193	17		T48	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T113	3		T108	15		T199	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T2	10		T105	2		T241	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T35	4		T237	9		T186	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T200	4		T19	5		T242	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T41	5		T108	11		T199	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T40	13		T194	8		T241	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T10	1		T108	11		T46	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T80	12		T110	7		T124	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T8	14		T251	12		T214	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T80	13		T198	7		T115	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T199	4		T110	7		T126	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T121	9		T200	5		T252	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1165	1			T13	36		T213	22		T81	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T39	1		T141	10		T130	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T40	12		T104	8		T115	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T40	12		T36	2		T202	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T2	4		T28	4		T80	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T113	3		T45	8		T190	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T253	4		T246	11		T318	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T124	2		T126	10		T247	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T10	11		T14	13		T104	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T193	14		T48	1		T319	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T8	2		T28	1		T111	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T36	4		T107	1		T124	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T104	1		T316	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T217	10		T317	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T10	11		T14	9		T122	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T15	6		T105	4		T18	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T8	2		T113	8		T35	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T2	11		T14	2		T28	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T34	1		T108	13		T192	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T1	1		T200	5		T241	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T10	7		T41	1		T108	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T40	12		T104	11		T106	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T167	2		T107	13		T38	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T113	2		T80	24		T35	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T8	11		T191	1		T199	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T200	6		T106	12		T211	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T122	2		T110	1		T126	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T121	1		T47	1		T209	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T11	3		T14	2		T104	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	349	1			T40	17		T208	2		T36	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1455	1			T2	7		T6	1		T7	24
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T113	3		T45	11		T190	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18524	1			T3	19		T9	194		T10	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T28	4		T226	19		T222	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T36	2		T124	2		T126	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T104	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T217	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T10	11		T14	13		T122	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T105	2		T193	14		T48	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T113	3		T35	4		T108	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T2	10		T19	5		T242	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T108	11		T199	13		T37	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T200	4		T241	11		T252	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T10	1		T41	5		T108	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T40	13		T110	7		T194	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T38	6		T130	11		T251	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T80	25		T198	7		T115	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T8	14		T199	4		T128	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T200	5		T211	7		T252	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T110	7		T126	10		T225	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T121	9		T238	12		T222	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T104	8		T33	14		T197	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T40	12		T36	2		T202	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1215	1			T2	4		T13	36		T40	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T113	3		T45	8		T190	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23273

1

T1

1

T2

18

T3

19

auto[1]

auto[0]

3980

1

T2

14

T8

14

T10

12