Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27253

1

T1

1

T2

32

T3

19

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23458

1

T1

1

T2

32

T3

19

auto[ADC_CTRL_FILTER_COND_OUT]

3795

1

T8

27

T10

22

T11

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21517

1

T1

1

T2

21

T3

19

auto[1]

5736

1

T2

11

T6

1

T7

24

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23424

1

T1

1

T2

16

T3

19

auto[1]

3829

1

T2

16

T7

22

T8

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	145	1			T14	2		T35	2		T122	5
values[0]	159	1			T265	16		T131	23		T118	6
values[1]	750	1			T2	21		T14	22		T104	11
values[2]	2679	1			T7	24		T8	2		T13	39
values[3]	671	1			T6	1		T8	2		T41	6
values[4]	631	1			T15	6		T40	51		T35	3
values[5]	622	1			T10	8		T11	3		T14	2
values[6]	806	1			T113	6		T80	24		T108	24
values[7]	686	1			T28	2		T45	19		T190	3
values[8]	573	1			T113	2		T46	17		T208	2
values[9]	1007	1			T1	1		T2	11		T8	25
minimum	18524	1			T3	19		T9	194		T10	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	687	1			T2	21		T14	22		T104	11
values[1]	2772	1			T7	24		T8	2		T13	39
values[2]	632	1			T6	1		T8	2		T15	6
values[3]	701	1			T40	25		T104	22		T80	21
values[4]	649	1			T10	8		T11	3		T14	2
values[5]	801	1			T28	2		T45	19		T80	24
values[6]	592	1			T113	2		T190	3		T122	2
values[7]	627	1			T35	15		T46	17		T208	2
values[8]	914	1			T1	1		T2	11		T8	25
values[9]	78	1			T80	25		T122	5		T196	2
minimum	18800	1			T3	19		T9	194		T10	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23273

1

T1

1

T2

18

T3

19

auto[1]

3980

1

T2

14

T8

14

T10

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T2	11		T14	14		T104	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T33	15		T122	13		T199	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1506	1			T7	2		T8	1		T13	39
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T40	13		T104	9		T36	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T6	1		T15	1		T105	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T8	1		T41	6		T105	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T40	14		T35	2		T191	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T104	9		T80	11		T108	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T10	3		T14	1		T28	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T11	2		T40	13		T113	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T108	12		T37	4		T106	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T28	1		T45	9		T80	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T113	1		T202	10		T171	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T190	3		T122	1		T167	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T35	1		T208	1		T36	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T35	6		T46	15		T193	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T1	1		T2	5		T35	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T8	15		T10	13		T14	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T80	14		T122	2		T225	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T196	2		T295	1		T320	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18449	1			T3	19		T9	194		T10	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T34	1		T286	1		T238	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T2	10		T14	8		T104	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T33	18		T122	14		T199	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1026	1			T7	22		T8	1		T82	38
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T40	16		T36	2		T117	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T15	5		T105	3		T200	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T8	1		T237	8		T172	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T40	11		T35	1		T111	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T104	13		T80	10		T108	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T10	5		T14	1		T113	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T11	1		T40	13		T113	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T108	12		T37	2		T106	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T28	1		T45	10		T80	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T113	1		T202	8		T171	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T122	1		T167	15		T38	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T208	1		T194	17		T195	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T35	8		T46	2		T193	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T2	6		T192	14		T18	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T8	10		T10	9		T14	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T80	11		T122	3		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T11	1		T35	1		T33	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T205	9		T265	15		T118	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T35	2		T122	2		T199	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T14	1		T196	2		T141	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T131	13		T150	1		T298	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T265	1		T118	5		T144	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T2	11		T14	14		T104	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T34	1		T33	15		T122	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1448	1			T7	2		T8	1		T13	39
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T40	13		T104	9		T36	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T6	1		T105	3		T199	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T8	1		T41	6		T105	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T15	1		T40	14		T35	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T40	13		T108	12		T110	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T10	3		T14	1		T28	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T11	2		T113	4		T104	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T113	4		T108	12		T37	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T80	13		T106	2		T124	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T202	10		T171	1		T279	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T28	1		T45	9		T190	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T113	1		T208	1		T195	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T46	15		T193	15		T229	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T1	1		T2	5		T80	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T8	15		T10	13		T35	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18382	1			T3	19		T9	194		T10	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T122	3		T186	2		T321	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T14	1		T141	12		T276	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T131	10		T150	16		T298	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T265	15		T118	1		T144	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T2	10		T14	8		T104	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T33	18		T122	14		T199	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1015	1			T7	22		T8	1		T82	38
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T40	16		T36	2		T296	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T105	3		T199	9		T200	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T8	1		T237	8		T172	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T15	5		T40	11		T35	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T40	13		T108	13		T39	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T10	5		T14	1		T192	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T11	1		T113	7		T104	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T113	2		T108	12		T37	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T80	11		T106	17		T124	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T202	8		T171	1		T266	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T28	1		T45	10		T122	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T113	1		T208	1		T195	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T46	2		T193	16		T299	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T2	6		T80	11		T192	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T8	10		T10	9		T35	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T11	1		T35	1		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T2	11		T14	9		T104	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T33	19		T122	15		T199	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1352	1			T7	24		T8	2		T13	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T40	17		T104	1		T36	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T6	1		T15	6		T105	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T8	2		T41	1		T105	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T40	12		T35	2		T191	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T104	14		T80	11		T108	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T10	7		T14	2		T28	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T11	3		T40	14		T113	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T108	13		T37	3		T106	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T28	2		T45	11		T80	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T113	2		T202	9		T171	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T190	1		T122	2		T167	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T35	1		T208	2		T36	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T35	11		T46	3		T193	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T1	1		T2	7		T35	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T8	11		T10	11		T14	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T80	12		T122	4		T225	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T196	2		T295	1		T320	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18595	1			T3	19		T9	194		T10	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T34	1		T286	1		T238	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T2	10		T14	13		T110	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T33	14		T122	12		T199	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1180	1			T13	36		T213	22		T81	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T40	12		T104	8		T36	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T105	2		T200	4		T256	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T41	5		T237	9		T172	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T40	13		T35	1		T114	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T104	8		T80	10		T108	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T10	1		T28	4		T113	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T40	12		T113	3		T226	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T108	11		T37	3		T154	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T45	8		T80	12		T124	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T202	9		T266	10		T284	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T190	2		T167	13		T38	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T194	8		T198	7		T243	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T35	3		T46	14		T193	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T2	4		T121	9		T199	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T8	14		T10	11		T108	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T80	13		T122	1		T225	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T294	10		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T197	2		T131	12		T263	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T238	14		T205	9		T118	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T35	2		T122	4		T199	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T14	2		T196	2		T141	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T131	11		T150	17		T298	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T265	16		T118	5		T144	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T2	11		T14	9		T104	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T34	1		T33	19		T122	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1331	1			T7	24		T8	2		T13	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T40	17		T104	1		T36	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T6	1		T105	4		T199	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T8	2		T41	1		T105	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T15	6		T40	12		T35	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T40	14		T108	14		T110	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T10	7		T14	2		T28	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T11	3		T113	8		T104	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T113	3		T108	13		T37	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T80	12		T106	19		T124	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T202	9		T171	2		T279	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T28	2		T45	11		T190	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T113	2		T208	2		T195	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T46	3		T193	17		T229	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T1	1		T2	7		T80	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T8	11		T10	11		T35	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18524	1			T3	19		T9	194		T10	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T122	1		T199	4		T186	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T141	10		T276	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T131	12		T322	11		T323	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T118	1		T144	5		T324	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T2	10		T14	13		T197	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T33	14		T122	12		T199	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1132	1			T13	36		T213	22		T81	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T40	12		T104	8		T36	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T105	2		T199	13		T200	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T41	5		T237	9		T172	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T40	13		T35	1		T114	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T40	12		T108	11		T110	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T10	1		T28	4		T47	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T113	3		T104	8		T80	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T113	3		T108	11		T37	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T80	12		T124	13		T262	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T202	9		T266	10		T233	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T45	8		T190	2		T167	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T198	7		T223	12		T284	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T46	14		T193	14		T271	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T2	4		T80	13		T121	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T8	14		T10	11		T35	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23273

1

T1

1

T2

18

T3

19

auto[1]

auto[0]

3980

1

T2

14

T8

14

T10

12