Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27253

1

T1

1

T2

32

T3

19

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21696

1

T1

1

T2

11

T3

19

auto[ADC_CTRL_FILTER_COND_OUT]

5557

1

T2

21

T6

1

T7

24

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21167

1

T1

1

T2

21

T3

19

auto[1]

6086

1

T2

11

T7

24

T8

27

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23424

1

T1

1

T2

16

T3

19

auto[1]

3829

1

T2

16

T7

22

T8

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	345	1			T199	5		T110	8		T237	18
values[0]	55	1			T130	23		T189	19		T207	12
values[1]	614	1			T1	1		T8	4		T104	22
values[2]	628	1			T45	19		T104	11		T122	2
values[3]	841	1			T8	25		T10	22		T40	29
values[4]	762	1			T190	3		T80	21		T191	1
values[5]	486	1			T14	2		T113	2		T105	1
values[6]	572	1			T6	1		T14	22		T40	25
values[7]	665	1			T2	21		T11	3		T28	2
values[8]	639	1			T2	11		T14	2		T28	5
values[9]	3122	1			T7	24		T10	8		T13	39
minimum	18524	1			T3	19		T9	194		T10	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	673	1			T1	1		T8	2		T104	22
values[1]	3031	1			T7	24		T13	39		T40	29
values[2]	635	1			T8	25		T10	22		T113	11
values[3]	766	1			T14	2		T190	3		T35	14
values[4]	485	1			T113	2		T105	1		T192	15
values[5]	695	1			T6	1		T14	22		T40	25
values[6]	532	1			T2	21		T11	3		T28	2
values[7]	644	1			T14	2		T15	6		T28	5
values[8]	863	1			T2	11		T10	8		T113	6
values[9]	198	1			T41	6		T34	1		T110	8
minimum	18731	1			T3	19		T8	2		T9	194

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23273

1

T1

1

T2

18

T3

19

auto[1]

3980

1

T2

14

T8

14

T10

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T1	1		T8	1		T33	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T104	9		T193	15		T194	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T40	13		T45	9		T122	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1543	1			T7	2		T13	39		T104	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T8	15		T10	13		T113	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T80	11		T191	1		T124	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T14	1		T190	3		T35	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T167	1		T36	1		T112	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T113	1		T105	1		T192	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T140	1		T111	1		T47	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T40	14		T33	15		T197	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T6	1		T14	14		T108	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T28	1		T40	13		T105	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T2	11		T11	2		T35	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T14	1		T28	5		T200	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T15	1		T80	13		T108	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T2	5		T113	4		T199	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T10	3		T104	9		T35	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T34	1		T115	10		T203	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T41	6		T110	8		T198	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18460	1			T3	19		T8	1		T9	194
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T107	1		T130	12		T188	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T8	1		T122	1		T18	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T104	13		T193	16		T194	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T40	16		T45	10		T122	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1080	1			T7	22		T104	10		T82	38
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T8	10		T10	9		T113	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T80	10		T124	11		T195	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T14	1		T35	8		T46	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T167	1		T125	1		T115	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T113	1		T192	14		T159	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T111	2		T201	2		T48	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T40	11		T33	18		T122	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T14	8		T108	12		T199	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T28	1		T40	13		T105	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T2	10		T11	1		T202	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T14	1		T200	4		T194	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T15	5		T80	11		T108	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T2	6		T113	2		T36	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T10	5		T35	1		T154	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T115	10		T203	11		T204	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T21	3		T187	8		T304	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T8	1		T11	1		T35	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T107	12		T130	11		T145	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T199	5		T237	10		T47	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T110	8		T205	10		T287	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T189	10		T207	7		T325	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T130	12		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T1	1		T8	2		T33	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T104	9		T193	15		T194	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T45	9		T122	1		T18	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T104	1		T208	1		T37	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T8	15		T10	13		T40	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T108	16		T167	14		T124	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T190	3		T46	15		T110	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T80	11		T191	1		T167	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T14	1		T113	1		T105	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T140	1		T111	1		T209	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T40	14		T197	3		T106	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T6	1		T14	14		T108	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T28	1		T33	15		T122	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T2	11		T11	2		T35	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T2	5		T14	1		T28	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T80	13		T35	2		T108	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T113	4		T34	1		T36	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1579	1			T7	2		T10	3		T13	39
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18382	1			T3	19		T9	194		T10	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T237	8		T47	6		T204	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T205	9		T206	3		T119	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T189	9		T207	5		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T130	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T8	2		T212	3		T129	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T104	13		T193	16		T194	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T45	10		T122	1		T18	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T104	10		T208	1		T37	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T8	10		T10	9		T40	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T108	12		T167	15		T124	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T46	2		T111	2		T283	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T80	10		T167	1		T115	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T14	1		T113	1		T35	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T111	2		T201	2		T48	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T40	11		T106	11		T222	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T14	8		T108	12		T199	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T28	1		T33	18		T122	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T2	10		T11	1		T202	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T2	6		T14	1		T40	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T80	11		T108	13		T106	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T113	2		T36	2		T194	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1071	1			T7	22		T10	5		T15	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T11	1		T35	1		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T1	1		T8	2		T33	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T104	14		T193	17		T194	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T40	17		T45	11		T122	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1410	1			T7	24		T13	3		T104	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T8	11		T10	11		T113	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T80	11		T191	1		T124	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T14	2		T190	1		T35	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T167	2		T36	1		T112	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T113	2		T105	1		T192	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T140	1		T111	3		T47	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T40	12		T33	19		T197	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T6	1		T14	9		T108	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T28	2		T40	14		T105	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T2	11		T11	3		T35	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T14	2		T28	1		T200	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T15	6		T80	12		T108	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T2	7		T113	3		T199	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T10	7		T104	1		T35	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T34	1		T115	11		T203	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T41	1		T110	1		T198	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18569	1			T3	19		T8	2		T9	194
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T107	13		T130	12		T188	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T200	5		T124	13		T263	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T104	8		T193	14		T194	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T40	12		T45	8		T122	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1213	1			T13	36		T213	22		T81	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T8	14		T10	11		T113	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T80	10		T124	2		T214	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T190	2		T35	3		T46	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T115	14		T211	7		T251	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T238	12		T159	7		T216	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T159	12		T271	15		T217	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T40	13		T33	14		T197	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T14	13		T108	11		T199	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T40	12		T105	2		T154	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T2	10		T202	9		T256	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T28	4		T200	4		T126	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T80	12		T108	11		T199	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T2	4		T113	3		T199	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T10	1		T104	8		T35	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T115	9		T219	16		T220	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T41	5		T110	7		T21	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T121	9		T212	1		T189	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T130	11		T151	1		T24	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T199	1		T237	9		T47	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T110	1		T205	10		T287	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T189	10		T207	6		T325	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T130	12		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T1	1		T8	4		T33	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T104	14		T193	17		T194	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T45	11		T122	2		T18	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T104	11		T208	2		T37	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T8	11		T10	11		T40	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T108	13		T167	16		T124	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T190	1		T46	3		T110	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T80	11		T191	1		T167	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T14	2		T113	2		T105	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T140	1		T111	3		T209	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T40	12		T197	1		T106	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T6	1		T14	9		T108	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T28	2		T33	19		T122	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T2	11		T11	3		T35	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T2	7		T14	2		T28	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T80	12		T35	2		T108	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T113	3		T34	1		T36	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1406	1			T7	24		T10	7		T13	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18524	1			T3	19		T9	194		T10	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T199	4		T237	9		T47	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T110	7		T205	9		T119	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T189	9		T207	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T130	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T121	9		T212	1		T263	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T104	8		T193	14		T194	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T45	8		T200	5		T124	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T37	3		T186	3		T141	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T8	14		T10	11		T40	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T108	15		T167	13		T124	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T190	2		T46	14		T110	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T80	10		T115	14		T211	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T35	3		T114	8		T159	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T222	9		T159	12		T217	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T40	13		T197	2		T126	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T14	13		T108	11		T199	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T33	14		T122	1		T154	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T2	10		T202	9		T39	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T2	4		T28	4		T40	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T80	12		T108	11		T38	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T113	3		T36	2		T110	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1244	1			T10	1		T13	36		T41	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23273

1

T1

1

T2

18

T3

19

auto[1]

auto[0]

3980

1

T2

14

T8

14

T10

12