Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T2	11		T6	1		T11	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T10	7		T14	2		T167	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1430	1			T7	24		T13	3		T104	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T113	8		T110	1		T19	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T8	2		T191	1		T199	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T105	1		T80	11		T18	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T41	1		T113	2		T80	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T14	2		T45	11		T104	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T28	2		T190	1		T35	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T40	12		T110	1		T111	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T2	7		T113	3		T122	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T108	14		T197	1		T167	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T14	9		T192	15		T36	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T40	17		T108	13		T122	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T10	11		T35	11		T121	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T1	1		T28	1		T35	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T8	13		T15	6		T34	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T40	14		T199	7		T172	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T227	1		T228	1		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T226	1		T195	3		T209	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18524	1			T3	19		T9	194		T10	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T229	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T2	10		T105	2		T80	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T10	1		T167	13		T154	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1186	1			T13	36		T104	8		T213	22
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T113	3		T110	7		T19	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T199	17		T202	9		T114	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T80	10		T194	8		T237	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T41	5		T80	12		T171	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T45	8		T104	8		T33	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T190	2		T35	1		T193	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T40	13		T110	7		T114	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T2	4		T113	3		T122	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T108	11		T197	2		T38	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T14	13		T36	2		T130	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T40	12		T108	11		T122	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T10	11		T35	3		T121	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T28	4		T46	14		T171	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T8	14		T211	7		T238	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T40	12		T199	7		T239	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T227	9		T228	13		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T226	19		T240	13		T25	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	455	1			T9	6		T11	5		T45	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T232	1		T233	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T234	18		T235	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T154	5		T124	12		T225	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T2	11		T6	1		T11	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T10	7		T14	2		T167	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1444	1			T7	24		T13	3		T104	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T18	9		T110	1		T141	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T8	2		T199	10		T202	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T113	8		T45	11		T105	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T41	1		T80	12		T191	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T14	2		T104	12		T33	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T2	7		T28	2		T113	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T36	1		T111	3		T177	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T113	3		T190	1		T37	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T40	12		T108	14		T167	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T14	9		T192	15		T208	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T40	17		T108	13		T197	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T10	11		T122	2		T36	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T1	1		T35	1		T122	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T8	13		T15	6		T34	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	338	1			T28	1		T40	14		T199	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18083	1			T3	19		T9	188		T10	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T236	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T234	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T154	8		T124	2		T225	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T2	10		T105	2		T80	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T10	1		T167	13		T198	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1186	1			T13	36		T104	8		T213	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T110	7		T241	6		T119	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T199	13		T202	9		T114	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T113	3		T45	8		T80	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T41	5		T80	12		T199	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T104	8		T33	14		T110	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T2	4		T35	1		T122	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T186	3		T242	2		T127	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T113	3		T190	2		T37	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T40	13		T108	11		T38	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T14	13		T130	11		T128	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T40	12		T108	11		T197	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T10	11		T36	2		T243	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T122	12		T36	2		T125	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T8	14		T35	3		T121	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T28	4		T40	12		T199	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23273

1

T1

1

T2

18

T3

19

auto[1]

auto[0]

3980

1

T2

14

T8

14

T10

12