Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27253

1

T1

1

T2

32

T3

19

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24041

1

T2

11

T3

19

T6

1

auto[ADC_CTRL_FILTER_COND_OUT]

3212

1

T1

1

T2

21

T8

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21228

1

T1

1

T2

11

T3

19

auto[1]

6025

1

T2

21

T7

24

T8

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23424

1

T1

1

T2

16

T3

19

auto[1]

3829

1

T2

16

T7

22

T8

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	31	1			T244	6		T245	1		T246	24
values[0]	127	1			T10	22		T193	31		T110	10
values[1]	529	1			T14	22		T15	6		T104	9
values[2]	464	1			T2	21		T8	2		T14	2
values[3]	603	1			T1	1		T34	1		T108	24
values[4]	674	1			T10	8		T40	25		T41	6
values[5]	700	1			T113	2		T80	49		T35	1
values[6]	864	1			T8	25		T191	1		T199	5
values[7]	471	1			T121	10		T122	2		T110	8
values[8]	863	1			T11	3		T14	2		T40	29
values[9]	3403	1			T2	11		T6	1		T7	24
minimum	18524	1			T3	19		T9	194		T10	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	785	1			T2	21		T8	2		T14	22
values[1]	377	1			T1	1		T14	2		T28	2
values[2]	669	1			T40	25		T41	6		T34	1
values[3]	750	1			T10	8		T104	11		T80	24
values[4]	757	1			T8	25		T113	2		T80	25
values[5]	600	1			T191	1		T121	10		T199	5
values[6]	2888	1			T7	24		T11	3		T13	39
values[7]	789	1			T6	1		T14	2		T40	55
values[8]	919	1			T2	11		T113	6		T45	19
values[9]	159	1			T8	2		T28	5		T124	14
minimum	18560	1			T3	19		T9	194		T10	35

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23273

1

T1

1

T2

18

T3

19

auto[1]

3980

1

T2

14

T8

14

T10

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T8	1		T14	14		T113	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T2	11		T15	1		T105	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T35	8		T192	1		T194	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T1	1		T14	1		T28	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T41	6		T34	1		T108	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T40	14		T199	14		T106	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T10	3		T108	12		T46	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T104	1		T80	13		T110	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T8	15		T167	1		T115	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T113	1		T80	14		T35	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T191	1		T199	5		T106	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T121	10		T200	6		T106	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1459	1			T7	2		T11	2		T13	39
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T39	5		T209	1		T141	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T6	1		T14	1		T40	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T40	13		T33	1		T208	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T2	5		T80	11		T122	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T113	4		T45	9		T190	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T28	5		T149	2		T215	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T8	1		T124	3		T126	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18407	1			T3	19		T9	194		T10	26
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T8	1		T14	8		T113	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T2	10		T15	5		T105	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T35	9		T192	3		T194	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T14	1		T28	1		T200	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T108	12		T37	2		T201	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T40	11		T199	9		T106	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T10	5		T108	13		T46	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T104	10		T80	11		T111	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T8	10		T167	1		T115	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T113	1		T80	11		T198	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T106	2		T125	1		T22	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T200	5		T106	11		T230	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1057	1			T7	22		T11	1		T82	38
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T39	3		T141	12		T130	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T14	1		T40	13		T104	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T40	16		T208	1		T36	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T2	6		T80	10		T122	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T113	2		T45	10		T167	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T149	13		T215	5		T246	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T8	1		T124	11		T247	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T10	9		T11	1		T35	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T244	3		T246	12		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T245	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T10	13		T144	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T193	15		T110	10		T217	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T14	14		T104	9		T122	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T15	1		T105	3		T18	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T8	1		T113	4		T35	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T2	11		T14	1		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T34	1		T108	12		T192	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T1	1		T199	14		T200	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T10	3		T41	6		T108	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T40	14		T104	1		T106	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T167	1		T107	1		T38	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T113	1		T80	27		T35	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T8	15		T191	1		T199	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T200	6		T106	1		T211	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T122	1		T110	8		T126	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T121	10		T114	17		T47	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T11	2		T14	1		T104	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T40	13		T33	1		T208	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1638	1			T2	5		T6	1		T7	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	347	1			T8	1		T113	4		T45	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18382	1			T3	19		T9	194		T10	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T244	3		T246	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T10	9		T144	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T193	16		T217	9		T248	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T14	8		T122	14		T192	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T15	5		T105	3		T18	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T8	1		T113	7		T35	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T2	10		T14	1		T28	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T108	12		T192	3		T37	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T199	9		T200	4		T243	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T10	5		T108	13		T46	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T40	11		T104	10		T106	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T167	1		T107	12		T38	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T113	1		T80	22		T111	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T8	10		T106	2		T249	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T200	5		T106	11		T211	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T122	1		T172	7		T205	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T114	12		T230	5		T250	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T11	1		T14	1		T104	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T40	16		T208	1		T202	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1160	1			T2	6		T7	22		T40	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T8	1		T113	2		T45	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T11	1		T35	1		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T8	2		T14	9		T113	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T2	11		T15	6		T105	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T35	13		T192	4		T194	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T1	1		T14	2		T28	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T41	1		T34	1		T108	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T40	12		T199	10		T106	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T10	7		T108	14		T46	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T104	11		T80	12		T110	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T8	11		T167	2		T115	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T113	2		T80	12		T35	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T191	1		T199	1		T106	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T121	1		T200	6		T106	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1377	1			T7	24		T11	3		T13	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T39	7		T209	1		T141	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T6	1		T14	2		T40	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T40	17		T33	1		T208	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T2	7		T80	11		T122	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T113	3		T45	11		T190	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T28	1		T149	15		T215	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T8	2		T124	12		T126	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18538	1			T3	19		T9	194		T10	24
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T14	13		T113	3		T104	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T2	10		T105	2		T193	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T35	4		T237	9		T186	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T200	4		T19	5		T242	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T41	5		T108	11		T37	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T40	13		T199	13		T194	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T10	1		T108	11		T46	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T80	12		T110	7		T124	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T8	14		T115	14		T251	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T80	13		T198	7		T211	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T199	4		T110	7		T126	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T121	9		T200	5		T252	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1139	1			T13	36		T213	22		T81	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T39	1		T141	10		T130	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T40	12		T104	8		T33	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T40	12		T36	2		T202	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T2	4		T80	10		T122	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T113	3		T45	8		T190	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T28	4		T215	4		T253	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T124	2		T126	10		T247	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T10	11		T144	11		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T244	4		T246	13		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T245	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T10	11		T144	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T193	17		T110	1		T217	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T14	9		T104	1		T122	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T15	6		T105	4		T18	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T8	2		T113	8		T35	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T2	11		T14	2		T28	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T34	1		T108	13		T192	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T1	1		T199	10		T200	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T10	7		T41	1		T108	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T40	12		T104	11		T106	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T167	2		T107	13		T38	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T113	2		T80	24		T35	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T8	11		T191	1		T199	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T200	6		T106	12		T211	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T122	2		T110	1		T126	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T121	1		T114	13		T47	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T11	3		T14	2		T104	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T40	17		T33	1		T208	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1515	1			T2	7		T6	1		T7	24
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T8	2		T113	3		T45	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18524	1			T3	19		T9	194		T10	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T244	2		T246	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T10	11		T144	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T193	14		T110	9		T217	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T14	13		T104	8		T122	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T105	2		T48	1		T241	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T113	3		T35	4		T108	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T2	10		T19	5		T242	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T108	11		T37	3		T186	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T199	13		T200	4		T241	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T10	1		T41	5		T108	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T40	13		T110	7		T194	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T38	6		T115	14		T130	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T80	25		T198	7		T172	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T8	14		T199	4		T128	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T200	5		T211	7		T222	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T110	7		T126	10		T225	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T121	9		T114	16		T238	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T104	8		T33	14		T197	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T40	12		T202	9		T154	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1283	1			T2	4		T13	36		T28	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T113	3		T45	8		T190	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23273

1

T1

1

T2

18

T3

19

auto[1]

auto[0]

3980

1

T2

14

T8

14

T10

12