Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27253

1

T1

1

T2

32

T3

19

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23480

1

T1

1

T3

19

T7

24

auto[ADC_CTRL_FILTER_COND_OUT]

3773

1

T2

32

T6

1

T8

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21005

1

T1

1

T3

19

T6

1

auto[1]

6248

1

T2

32

T7

24

T8

4

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23424

1

T1

1

T2

16

T3

19

auto[1]

3829

1

T2

16

T7

22

T8

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	304	1			T113	6		T108	28		T122	27
values[0]	14	1			T254	1		T32	13		-	-
values[1]	657	1			T1	1		T10	22		T15	6
values[2]	574	1			T8	2		T11	3		T14	2
values[3]	828	1			T8	2		T14	2		T40	26
values[4]	677	1			T10	8		T28	5		T191	1
values[5]	2922	1			T2	11		T7	24		T13	39
values[6]	554	1			T35	3		T46	17		T110	10
values[7]	686	1			T2	21		T8	25		T14	22
values[8]	620	1			T6	1		T28	2		T45	19
values[9]	893	1			T40	29		T35	1		T199	5
minimum	18524	1			T3	19		T9	194		T10	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	709	1			T1	1		T8	2		T10	22
values[1]	609	1			T11	3		T14	2		T41	6
values[2]	718	1			T8	2		T14	2		T40	26
values[3]	2976	1			T7	24		T10	8		T13	39
values[4]	591	1			T2	11		T104	11		T35	2
values[5]	705	1			T35	3		T108	24		T46	17
values[6]	532	1			T2	21		T8	25		T14	22
values[7]	706	1			T6	1		T28	2		T45	19
values[8]	881	1			T40	29		T113	6		T122	27
values[9]	128	1			T108	28		T114	9		T265	3
minimum	18698	1			T3	19		T9	194		T10	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23273

1

T1

1

T2

18

T3

19

auto[1]

3980

1

T2

14

T8

14

T10

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T1	1		T15	1		T105	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T8	1		T10	13		T40	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T11	2		T14	1		T41	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T104	9		T197	3		T110	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T14	1		T191	1		T167	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T8	1		T40	13		T80	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1508	1			T7	2		T10	3		T13	39
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T28	5		T104	9		T192	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T104	1		T192	1		T38	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T2	5		T35	2		T112	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T35	2		T46	15		T106	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T108	12		T36	1		T110	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T8	15		T14	14		T122	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T2	11		T190	3		T200	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T28	1		T45	9		T34	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T6	1		T35	1		T121	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T113	4		T18	5		T199	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T40	13		T122	13		T199	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T265	1		T119	12		T266	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T108	16		T114	9		T267	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18441	1			T3	19		T9	194		T10	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T113	1		T130	12		T254	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T15	5		T105	3		T80	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T8	1		T10	9		T40	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T11	1		T14	1		T33	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T104	13		T125	4		T242	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T14	1		T167	1		T208	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T8	1		T40	13		T80	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1053	1			T7	22		T10	5		T82	38
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T192	14		T107	14		T154	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T104	10		T192	3		T38	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T2	6		T203	11		T256	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T35	1		T46	2		T106	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T108	12		T154	5		T268	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T8	10		T14	8		T122	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T2	10		T200	9		T202	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T28	1		T45	10		T80	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T177	12		T172	7		T201	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T113	2		T18	4		T199	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T40	16		T122	14		T106	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T265	2		T119	5		T266	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T108	12		T267	6		T269	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T11	1		T113	7		T35	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T113	1		T130	11		T266	14

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T113	4		T18	5		T199	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T108	16		T122	13		T237	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T254	1		T32	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T1	1		T15	1		T113	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T10	13		T40	14		T113	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T11	2		T14	1		T41	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T8	1		T122	2		T110	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T14	1		T208	1		T106	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T8	1		T40	13		T104	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T10	3		T191	1		T167	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T28	5		T199	8		T154	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1449	1			T7	2		T13	39		T104	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T2	5		T104	9		T35	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T35	2		T46	15		T107	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T110	10		T154	9		T226	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T8	15		T14	14		T106	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T2	11		T190	3		T108	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T28	1		T45	9		T34	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T6	1		T121	10		T200	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T140	1		T171	16		T126	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T40	13		T35	1		T199	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18382	1			T3	19		T9	194		T10	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T113	2		T18	4		T199	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T108	12		T122	14		T237	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T32	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T15	5		T113	7		T80	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T10	9		T40	11		T113	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T11	1		T14	1		T105	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T8	1		T122	3		T125	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T14	1		T208	1		T106	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T8	1		T40	13		T104	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T10	5		T167	1		T36	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T199	6		T154	14		T19	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1021	1			T7	22		T104	10		T82	38
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T2	6		T192	14		T107	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T35	1		T46	2		T107	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T154	4		T204	4		T268	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T8	10		T14	8		T106	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T2	10		T108	12		T200	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T28	1		T45	10		T80	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T200	5		T172	7		T201	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T171	11		T48	1		T230	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T40	16		T106	6		T194	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T11	1		T35	1		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T1	1		T15	6		T105	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T8	2		T10	11		T40	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T11	3		T14	2		T41	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T104	14		T197	1		T110	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T14	2		T191	1		T167	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T8	2		T40	14		T80	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1391	1			T7	24		T10	7		T13	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T28	1		T104	1		T192	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T104	11		T192	4		T38	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T2	7		T35	2		T112	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T35	2		T46	3		T106	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T108	13		T36	1		T110	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T8	11		T14	9		T122	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T2	11		T190	1		T200	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T28	2		T45	11		T34	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T6	1		T35	1		T121	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T113	3		T18	9		T199	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T40	17		T122	15		T199	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T265	3		T119	12		T266	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T108	13		T114	1		T267	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18560	1			T3	19		T9	194		T10	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T113	2		T130	12		T254	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T105	2		T80	10		T35	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T10	11		T40	13		T122	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T41	5		T33	14		T117	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T104	8		T197	2		T110	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T36	2		T198	7		T222	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T40	12		T80	13		T199	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1170	1			T10	1		T13	36		T213	22
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T28	4		T104	8		T154	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T38	6		T115	14		T262	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T2	4		T126	10		T256	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T35	1		T46	14		T226	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T108	11		T110	9		T154	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T8	14		T14	13		T128	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T2	10		T190	2		T200	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T45	8		T80	12		T167	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T121	9		T270	15		T151	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T113	3		T199	13		T110	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T40	12		T122	12		T199	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T119	5		T266	4		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T108	15		T114	8		T267	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T113	3		T271	15		T21	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T130	11		T266	10		T272	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T113	3		T18	9		T199	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T108	13		T122	15		T237	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T254	1		T32	13		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T1	1		T15	6		T113	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T10	11		T40	12		T113	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T11	3		T14	2		T41	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T8	2		T122	4		T110	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T14	2		T208	2		T106	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T8	2		T40	14		T104	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T10	7		T191	1		T167	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T28	1		T199	7		T154	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1346	1			T7	24		T13	3		T104	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T2	7		T104	1		T35	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T35	2		T46	3		T107	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T110	1		T154	5		T226	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T8	11		T14	9		T106	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T2	11		T190	1		T108	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T28	2		T45	11		T34	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T6	1		T121	1		T200	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T140	1		T171	12		T126	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T40	17		T35	1		T199	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18524	1			T3	19		T9	194		T10	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T113	3		T199	13		T110	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T108	15		T122	12		T237	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T113	3		T80	10		T108	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T10	11		T40	13		T36	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T41	5		T105	2		T35	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T122	1		T110	7		T125	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T198	7		T222	9		T214	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T40	12		T104	8		T80	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T10	1		T36	2		T211	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T28	4		T199	7		T154	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1124	1			T13	36		T213	22		T81	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T2	4		T104	8		T256	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T35	1		T46	14		T38	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T110	9		T154	8		T226	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T8	14		T14	13		T226	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T2	10		T190	2		T108	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T45	8		T80	12		T167	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T121	9		T200	5		T270	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T171	15		T126	10		T119	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T40	12		T199	4		T194	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23273

1

T1

1

T2

18

T3

19

auto[1]

auto[0]

3980

1

T2

14

T8

14

T10

12