Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27253

1

T1

1

T2

32

T3

19

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23708

1

T1

1

T3

19

T7

24

auto[ADC_CTRL_FILTER_COND_OUT]

3545

1

T2

32

T6

1

T8

29

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21198

1

T1

1

T3

19

T6

1

auto[1]

6055

1

T2

32

T7

24

T8

4

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23424

1

T1

1

T2

16

T3

19

auto[1]

3829

1

T2

16

T7

22

T8

12

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	25	1			T246	25		-	-		-	-
values[0]	92	1			T114	29		T254	1		T120	5
values[1]	620	1			T1	1		T10	22		T15	6
values[2]	549	1			T8	2		T11	3		T14	2
values[3]	824	1			T8	2		T14	2		T40	26
values[4]	700	1			T10	8		T28	5		T104	9
values[5]	2885	1			T2	11		T7	24		T13	39
values[6]	572	1			T35	3		T46	17		T106	12
values[7]	690	1			T2	21		T14	22		T190	3
values[8]	582	1			T6	1		T8	25		T28	2
values[9]	1190	1			T40	29		T113	6		T35	1
minimum	18524	1			T3	19		T9	194		T10	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	844	1			T1	1		T8	2		T10	22
values[1]	599	1			T11	3		T14	2		T41	6
values[2]	763	1			T8	2		T14	2		T40	26
values[3]	2982	1			T7	24		T10	8		T13	39
values[4]	538	1			T2	11		T104	20		T35	2
values[5]	730	1			T35	3		T108	24		T46	17
values[6]	570	1			T2	21		T8	25		T14	22
values[7]	664	1			T28	2		T45	19		T34	1
values[8]	696	1			T6	1		T40	29		T113	6
values[9]	312	1			T108	28		T122	27		T114	9
minimum	18555	1			T3	19		T9	194		T10	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23273

1

T1

1

T2

18

T3

19

auto[1]

3980

1

T2

14

T8

14

T10

12

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T1	1		T15	1		T40	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T8	1		T10	13		T113	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T11	2		T14	1		T41	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T104	9		T197	3		T110	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T14	1		T40	13		T191	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T8	1		T33	1		T199	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1515	1			T7	2		T10	3		T13	39
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T28	5		T192	1		T193	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T104	1		T35	2		T38	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T2	5		T104	9		T192	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T46	15		T106	1		T107	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T35	2		T108	12		T36	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T190	3		T122	1		T200	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T2	11		T8	15		T14	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T28	1		T45	9		T34	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T35	1		T107	1		T177	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T113	4		T18	5		T199	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T6	1		T40	13		T199	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T122	13		T171	16		T265	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T108	16		T114	9		T205	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18398	1			T3	19		T9	194		T10	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T273	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T15	5		T40	11		T113	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T8	1		T10	9		T113	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T11	1		T14	1		T80	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T104	13		T125	4		T171	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T14	1		T40	13		T167	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T8	1		T199	6		T106	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1043	1			T7	22		T10	5		T82	38
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T192	14		T193	16		T107	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T104	10		T38	6		T115	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T2	6		T192	3		T256	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T46	2		T106	11		T107	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T35	1		T108	12		T154	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T122	1		T200	4		T194	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T2	10		T8	10		T14	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T28	1		T45	10		T80	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T177	12		T172	7		T201	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T113	2		T18	4		T199	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T40	16		T106	6		T194	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T122	14		T171	11		T265	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T108	12		T205	18		T267	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T11	1		T35	1		T33	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T273	8		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T246	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T254	1		T120	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T114	17		T274	8		T32	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T1	1		T15	1		T40	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T10	13		T113	1		T122	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T11	2		T14	1		T41	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T8	1		T105	3		T110	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T14	1		T40	13		T80	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T8	1		T104	9		T33	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T10	3		T191	1		T167	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T28	5		T104	9		T199	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1482	1			T7	2		T13	39		T104	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T2	5		T192	2		T107	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T46	15		T106	1		T107	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T35	2		T110	10		T154	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T190	3		T200	5		T194	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T2	11		T14	14		T108	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T28	1		T45	9		T34	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T6	1		T8	15		T107	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T113	4		T122	13		T167	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	427	1			T40	13		T35	1		T108	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18382	1			T3	19		T9	194		T10	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T246	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T120	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T114	12		T274	5		T32	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T15	5		T40	11		T113	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T10	9		T113	1		T122	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T11	1		T14	1		T35	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T8	1		T105	3		T125	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T14	1		T40	13		T80	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T8	1		T104	13		T106	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T10	5		T167	1		T36	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T199	6		T154	14		T19	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1025	1			T7	22		T104	10		T82	38
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T2	6		T192	17		T107	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T46	2		T106	11		T107	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T35	1		T154	4		T204	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T200	4		T194	1		T124	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T2	10		T14	8		T108	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T28	1		T45	10		T80	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T8	10		T172	7		T201	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T113	2		T122	14		T167	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	347	1			T40	16		T108	12		T106	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T11	1		T35	1		T33	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T1	1		T15	6		T40	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T8	2		T10	11		T113	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T11	3		T14	2		T41	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T104	14		T197	1		T110	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T14	2		T40	14		T191	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T8	2		T33	1		T199	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1381	1			T7	24		T10	7		T13	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T28	1		T192	15		T193	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T104	11		T35	2		T38	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T2	7		T104	1		T192	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T46	3		T106	12		T107	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T35	2		T108	13		T36	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T190	1		T122	2		T200	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T2	11		T8	11		T14	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T28	2		T45	11		T34	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T35	1		T107	1		T177	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T113	3		T18	9		T199	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T6	1		T40	17		T199	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T122	15		T171	12		T265	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T108	13		T114	1		T205	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18525	1			T3	19		T9	194		T10	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T273	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T40	13		T113	3		T80	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T10	11		T105	2		T122	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T41	5		T80	13		T33	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T104	8		T197	2		T110	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T40	12		T36	2		T198	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T199	7		T39	1		T256	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1177	1			T10	1		T13	36		T213	22
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T28	4		T193	14		T154	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T38	6		T115	14		T262	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T2	4		T104	8		T226	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T46	14		T226	16		T172	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T35	1		T108	11		T110	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T190	2		T200	4		T124	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T2	10		T8	14		T14	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T45	8		T80	12		T121	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T270	15		T151	8		T275	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T113	3		T199	13		T110	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T40	12		T199	4		T194	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T122	12		T171	15		T266	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T108	15		T114	8		T205	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T271	15		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T273	6		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T246	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T254	1		T120	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T114	13		T274	6		T32	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T1	1		T15	6		T40	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T10	11		T113	2		T122	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T11	3		T14	2		T41	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T8	2		T105	4		T110	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T14	2		T40	14		T80	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T8	2		T104	14		T33	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T10	7		T191	1		T167	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T28	1		T104	1		T199	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1358	1			T7	24		T13	3		T104	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T2	7		T192	19		T107	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T46	3		T106	12		T107	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T35	2		T110	1		T154	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T190	1		T200	5		T194	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T2	11		T14	9		T108	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T28	2		T45	11		T34	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T6	1		T8	11		T107	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T113	3		T122	15		T167	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	429	1			T40	17		T35	1		T108	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18524	1			T3	19		T9	194		T10	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T246	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T114	16		T274	7		T276	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T40	13		T113	3		T80	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T10	11		T122	1		T36	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T41	5		T35	3		T33	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T105	2		T110	7		T125	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T40	12		T80	13		T198	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T104	8		T197	2		T193	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T10	1		T36	2		T211	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T28	4		T104	8		T199	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1149	1			T13	36		T213	22		T81	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T2	4		T256	2		T239	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T46	14		T38	6		T172	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T35	1		T110	9		T154	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T190	2		T200	4		T124	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T2	10		T14	13		T108	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T45	8		T80	12		T121	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T8	14		T270	15		T151	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T113	3		T122	12		T167	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	345	1			T40	12		T108	15		T199	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23273

1

T1

1

T2

18

T3

19

auto[1]

auto[0]

3980

1

T2

14

T8

14

T10

12