Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.76 99.07 96.67 100.00 100.00 98.83 98.33 91.39


Total test records in report: 917
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
T791 /workspace/coverage/default/41.adc_ctrl_filters_interrupt.1892651303 Jun 13 02:34:19 PM PDT 24 Jun 13 02:37:54 PM PDT 24 342492657105 ps
T792 /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.145711205 Jun 13 02:34:24 PM PDT 24 Jun 13 02:38:33 PM PDT 24 209437054603 ps
T58 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2620847546 Jun 13 02:17:27 PM PDT 24 Jun 13 02:17:33 PM PDT 24 1840142437 ps
T59 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.3964702603 Jun 13 02:17:18 PM PDT 24 Jun 13 02:17:24 PM PDT 24 341950994 ps
T100 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2792233909 Jun 13 02:17:11 PM PDT 24 Jun 13 02:17:17 PM PDT 24 413392777 ps
T793 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.2032498952 Jun 13 02:17:48 PM PDT 24 Jun 13 02:17:54 PM PDT 24 317448053 ps
T60 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1945344737 Jun 13 02:17:07 PM PDT 24 Jun 13 02:17:16 PM PDT 24 542803086 ps
T51 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1407644032 Jun 13 02:17:27 PM PDT 24 Jun 13 02:17:36 PM PDT 24 2576736472 ps
T794 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.4184232299 Jun 13 02:17:44 PM PDT 24 Jun 13 02:17:47 PM PDT 24 335717055 ps
T795 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.454275954 Jun 13 02:17:31 PM PDT 24 Jun 13 02:17:37 PM PDT 24 311977641 ps
T63 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.2224248095 Jun 13 02:17:08 PM PDT 24 Jun 13 02:17:16 PM PDT 24 390413966 ps
T54 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3308401041 Jun 13 02:17:15 PM PDT 24 Jun 13 02:17:21 PM PDT 24 463906483 ps
T69 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3809024264 Jun 13 02:17:22 PM PDT 24 Jun 13 02:17:28 PM PDT 24 529376882 ps
T796 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3982942019 Jun 13 02:17:23 PM PDT 24 Jun 13 02:17:29 PM PDT 24 524064180 ps
T52 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.4245747310 Jun 13 02:17:28 PM PDT 24 Jun 13 02:17:38 PM PDT 24 4509830428 ps
T55 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1374983191 Jun 13 02:17:20 PM PDT 24 Jun 13 02:17:30 PM PDT 24 8117877764 ps
T56 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3674934341 Jun 13 02:17:07 PM PDT 24 Jun 13 02:17:36 PM PDT 24 8493544692 ps
T53 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.4145070581 Jun 13 02:17:41 PM PDT 24 Jun 13 02:17:45 PM PDT 24 2217193353 ps
T87 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1371710753 Jun 13 02:17:28 PM PDT 24 Jun 13 02:17:32 PM PDT 24 615183518 ps
T797 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1318658663 Jun 13 02:17:03 PM PDT 24 Jun 13 02:17:10 PM PDT 24 490691482 ps
T64 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1190724494 Jun 13 02:17:30 PM PDT 24 Jun 13 02:17:38 PM PDT 24 646160780 ps
T57 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.589173005 Jun 13 02:17:34 PM PDT 24 Jun 13 02:17:39 PM PDT 24 4519458080 ps
T88 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.100342390 Jun 13 02:17:22 PM PDT 24 Jun 13 02:17:28 PM PDT 24 359056918 ps
T89 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.4250754321 Jun 13 02:17:11 PM PDT 24 Jun 13 02:19:22 PM PDT 24 39637788261 ps
T85 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3714709590 Jun 13 02:17:22 PM PDT 24 Jun 13 02:17:28 PM PDT 24 551862012 ps
T90 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3417024659 Jun 13 02:17:08 PM PDT 24 Jun 13 02:17:19 PM PDT 24 1190641195 ps
T798 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.1074099558 Jun 13 02:17:13 PM PDT 24 Jun 13 02:17:19 PM PDT 24 319046874 ps
T799 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1255427174 Jun 13 02:17:29 PM PDT 24 Jun 13 02:17:34 PM PDT 24 520906245 ps
T800 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3773815019 Jun 13 02:17:50 PM PDT 24 Jun 13 02:17:57 PM PDT 24 319706424 ps
T101 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2490002508 Jun 13 02:17:04 PM PDT 24 Jun 13 02:17:12 PM PDT 24 421479831 ps
T96 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1351267354 Jun 13 02:17:20 PM PDT 24 Jun 13 02:17:26 PM PDT 24 499195035 ps
T102 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.167392756 Jun 13 02:17:21 PM PDT 24 Jun 13 02:17:28 PM PDT 24 2076940624 ps
T801 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.2697601794 Jun 13 02:17:21 PM PDT 24 Jun 13 02:17:26 PM PDT 24 383592844 ps
T802 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.3475163888 Jun 13 02:17:44 PM PDT 24 Jun 13 02:17:45 PM PDT 24 411720606 ps
T68 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2088678207 Jun 13 02:17:29 PM PDT 24 Jun 13 02:17:36 PM PDT 24 4341065192 ps
T803 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.2570905082 Jun 13 02:17:12 PM PDT 24 Jun 13 02:17:19 PM PDT 24 347065302 ps
T91 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2105874339 Jun 13 02:17:07 PM PDT 24 Jun 13 02:17:15 PM PDT 24 1385128447 ps
T66 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2382784041 Jun 13 02:17:21 PM PDT 24 Jun 13 02:17:28 PM PDT 24 547319990 ps
T804 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.325454969 Jun 13 02:17:36 PM PDT 24 Jun 13 02:17:39 PM PDT 24 398779639 ps
T67 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2015649329 Jun 13 02:17:23 PM PDT 24 Jun 13 02:17:31 PM PDT 24 4397951985 ps
T86 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2109644616 Jun 13 02:17:17 PM PDT 24 Jun 13 02:17:23 PM PDT 24 587217084 ps
T92 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2920587678 Jun 13 02:17:02 PM PDT 24 Jun 13 02:17:10 PM PDT 24 1039373342 ps
T805 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3570890273 Jun 13 02:17:07 PM PDT 24 Jun 13 02:17:17 PM PDT 24 4978429360 ps
T70 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2473868582 Jun 13 02:17:10 PM PDT 24 Jun 13 02:17:21 PM PDT 24 4089972705 ps
T806 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2200695481 Jun 13 02:17:28 PM PDT 24 Jun 13 02:17:34 PM PDT 24 2450664577 ps
T65 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.1301246630 Jun 13 02:17:21 PM PDT 24 Jun 13 02:17:28 PM PDT 24 427151050 ps
T807 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.526988254 Jun 13 02:17:15 PM PDT 24 Jun 13 02:17:22 PM PDT 24 384525121 ps
T808 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.207792878 Jun 13 02:17:49 PM PDT 24 Jun 13 02:17:55 PM PDT 24 443426270 ps
T809 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.355393895 Jun 13 02:17:08 PM PDT 24 Jun 13 02:17:16 PM PDT 24 649763514 ps
T810 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.2700149299 Jun 13 02:17:10 PM PDT 24 Jun 13 02:17:19 PM PDT 24 769266973 ps
T811 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3619573078 Jun 13 02:17:52 PM PDT 24 Jun 13 02:17:58 PM PDT 24 457672116 ps
T812 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.1388078925 Jun 13 02:17:49 PM PDT 24 Jun 13 02:17:56 PM PDT 24 493986449 ps
T93 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1597664848 Jun 13 02:17:08 PM PDT 24 Jun 13 02:17:15 PM PDT 24 409639838 ps
T169 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1613922817 Jun 13 02:17:23 PM PDT 24 Jun 13 02:17:38 PM PDT 24 4416245211 ps
T813 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.2300012216 Jun 13 02:17:21 PM PDT 24 Jun 13 02:17:27 PM PDT 24 522341385 ps
T814 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2004916290 Jun 13 02:17:11 PM PDT 24 Jun 13 02:17:19 PM PDT 24 1016194982 ps
T815 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.283287139 Jun 13 02:17:13 PM PDT 24 Jun 13 02:17:21 PM PDT 24 1361304226 ps
T816 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1720566760 Jun 13 02:17:17 PM PDT 24 Jun 13 02:17:24 PM PDT 24 4098245436 ps
T817 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2511977198 Jun 13 02:17:11 PM PDT 24 Jun 13 02:17:33 PM PDT 24 4531778278 ps
T818 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.284995772 Jun 13 02:17:14 PM PDT 24 Jun 13 02:17:22 PM PDT 24 2057439207 ps
T819 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3757017475 Jun 13 02:17:11 PM PDT 24 Jun 13 02:17:18 PM PDT 24 736429891 ps
T94 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.945428434 Jun 13 02:17:17 PM PDT 24 Jun 13 02:17:37 PM PDT 24 26822865350 ps
T820 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.1472303316 Jun 13 02:17:18 PM PDT 24 Jun 13 02:17:32 PM PDT 24 4692300743 ps
T821 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.3579165022 Jun 13 02:17:48 PM PDT 24 Jun 13 02:17:54 PM PDT 24 297489756 ps
T822 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.3055514213 Jun 13 02:17:27 PM PDT 24 Jun 13 02:17:32 PM PDT 24 417913106 ps
T823 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2202501804 Jun 13 02:17:24 PM PDT 24 Jun 13 02:17:30 PM PDT 24 325582525 ps
T824 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.717011253 Jun 13 02:17:16 PM PDT 24 Jun 13 02:17:32 PM PDT 24 4219079020 ps
T170 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.4074548031 Jun 13 02:17:20 PM PDT 24 Jun 13 02:17:32 PM PDT 24 7681847514 ps
T825 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.670719469 Jun 13 02:17:29 PM PDT 24 Jun 13 02:17:33 PM PDT 24 369679933 ps
T826 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.154127697 Jun 13 02:17:22 PM PDT 24 Jun 13 02:17:27 PM PDT 24 478789236 ps
T827 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.3025412800 Jun 13 02:17:08 PM PDT 24 Jun 13 02:17:15 PM PDT 24 496330802 ps
T828 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1099196273 Jun 13 02:17:43 PM PDT 24 Jun 13 02:17:46 PM PDT 24 485954253 ps
T829 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.3125086674 Jun 13 02:17:30 PM PDT 24 Jun 13 02:17:35 PM PDT 24 297437038 ps
T830 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.709818187 Jun 13 02:17:29 PM PDT 24 Jun 13 02:17:36 PM PDT 24 398973498 ps
T831 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2216929686 Jun 13 02:17:36 PM PDT 24 Jun 13 02:17:39 PM PDT 24 429217409 ps
T832 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1854411676 Jun 13 02:17:15 PM PDT 24 Jun 13 02:17:23 PM PDT 24 573009096 ps
T833 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2598914606 Jun 13 02:17:12 PM PDT 24 Jun 13 02:17:19 PM PDT 24 535316923 ps
T95 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.4287865454 Jun 13 02:17:20 PM PDT 24 Jun 13 02:17:27 PM PDT 24 535347535 ps
T97 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3919823209 Jun 13 02:17:12 PM PDT 24 Jun 13 02:17:19 PM PDT 24 488286790 ps
T834 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1664212735 Jun 13 02:17:27 PM PDT 24 Jun 13 02:17:31 PM PDT 24 547418672 ps
T835 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.2513471856 Jun 13 02:17:24 PM PDT 24 Jun 13 02:17:30 PM PDT 24 487608036 ps
T836 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3768188373 Jun 13 02:17:28 PM PDT 24 Jun 13 02:17:33 PM PDT 24 548021651 ps
T837 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.3516014905 Jun 13 02:17:16 PM PDT 24 Jun 13 02:17:23 PM PDT 24 426677866 ps
T838 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.4208352935 Jun 13 02:17:08 PM PDT 24 Jun 13 02:17:15 PM PDT 24 392651164 ps
T839 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.2855111393 Jun 13 02:17:52 PM PDT 24 Jun 13 02:17:59 PM PDT 24 367926854 ps
T840 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1047113053 Jun 13 02:17:03 PM PDT 24 Jun 13 02:17:12 PM PDT 24 611503180 ps
T841 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2880426311 Jun 13 02:17:26 PM PDT 24 Jun 13 02:17:31 PM PDT 24 520940836 ps
T842 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.3403131185 Jun 13 02:17:07 PM PDT 24 Jun 13 02:17:14 PM PDT 24 425004265 ps
T843 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2213466198 Jun 13 02:17:29 PM PDT 24 Jun 13 02:17:33 PM PDT 24 466126383 ps
T844 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2597332892 Jun 13 02:17:08 PM PDT 24 Jun 13 02:17:20 PM PDT 24 4088305762 ps
T98 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2340347247 Jun 13 02:17:16 PM PDT 24 Jun 13 02:17:22 PM PDT 24 544899438 ps
T845 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.1520909111 Jun 13 02:17:02 PM PDT 24 Jun 13 02:17:13 PM PDT 24 3411767743 ps
T846 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.942287342 Jun 13 02:17:31 PM PDT 24 Jun 13 02:17:36 PM PDT 24 407857605 ps
T847 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2230643832 Jun 13 02:17:08 PM PDT 24 Jun 13 02:17:27 PM PDT 24 3803599470 ps
T848 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1853509093 Jun 13 02:17:11 PM PDT 24 Jun 13 02:17:19 PM PDT 24 493125716 ps
T99 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3574997879 Jun 13 02:17:10 PM PDT 24 Jun 13 02:18:05 PM PDT 24 51535837926 ps
T849 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3480304699 Jun 13 02:17:19 PM PDT 24 Jun 13 02:17:29 PM PDT 24 2119677108 ps
T850 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1243907617 Jun 13 02:17:20 PM PDT 24 Jun 13 02:17:26 PM PDT 24 570874803 ps
T851 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.2107452676 Jun 13 02:17:29 PM PDT 24 Jun 13 02:17:34 PM PDT 24 501982171 ps
T852 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.4175751017 Jun 13 02:17:22 PM PDT 24 Jun 13 02:17:28 PM PDT 24 520443816 ps
T71 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.253713415 Jun 13 02:17:10 PM PDT 24 Jun 13 02:17:38 PM PDT 24 8233947885 ps
T853 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3116290863 Jun 13 02:17:17 PM PDT 24 Jun 13 02:17:23 PM PDT 24 474707333 ps
T854 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.29208275 Jun 13 02:17:27 PM PDT 24 Jun 13 02:17:32 PM PDT 24 313707214 ps
T855 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.511520395 Jun 13 02:17:10 PM PDT 24 Jun 13 02:17:16 PM PDT 24 633128813 ps
T856 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.824716549 Jun 13 02:17:22 PM PDT 24 Jun 13 02:17:28 PM PDT 24 458682826 ps
T857 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1829402017 Jun 13 02:17:02 PM PDT 24 Jun 13 02:17:12 PM PDT 24 4881734265 ps
T858 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.1379927648 Jun 13 02:17:10 PM PDT 24 Jun 13 02:17:23 PM PDT 24 5073739797 ps
T859 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.1400596449 Jun 13 02:17:48 PM PDT 24 Jun 13 02:17:53 PM PDT 24 360589289 ps
T860 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.4240444474 Jun 13 02:17:13 PM PDT 24 Jun 13 02:17:20 PM PDT 24 595570747 ps
T861 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.1341262447 Jun 13 02:17:17 PM PDT 24 Jun 13 02:17:24 PM PDT 24 421672385 ps
T862 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.2547311384 Jun 13 02:17:04 PM PDT 24 Jun 13 02:17:12 PM PDT 24 370380180 ps
T863 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1075243176 Jun 13 02:17:30 PM PDT 24 Jun 13 02:17:34 PM PDT 24 457944531 ps
T864 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1758958317 Jun 13 02:17:16 PM PDT 24 Jun 13 02:17:22 PM PDT 24 534221184 ps
T865 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2007531847 Jun 13 02:17:23 PM PDT 24 Jun 13 02:17:33 PM PDT 24 2541482568 ps
T866 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3182831527 Jun 13 02:17:19 PM PDT 24 Jun 13 02:17:26 PM PDT 24 521055061 ps
T867 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.4046435966 Jun 13 02:17:10 PM PDT 24 Jun 13 02:17:18 PM PDT 24 428677515 ps
T868 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.724653585 Jun 13 02:17:23 PM PDT 24 Jun 13 02:17:28 PM PDT 24 823820359 ps
T869 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1016074972 Jun 13 02:17:22 PM PDT 24 Jun 13 02:17:28 PM PDT 24 564584459 ps
T870 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.992665063 Jun 13 02:17:07 PM PDT 24 Jun 13 02:17:19 PM PDT 24 2348092400 ps
T871 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.101280070 Jun 13 02:17:36 PM PDT 24 Jun 13 02:17:39 PM PDT 24 525464678 ps
T872 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.4059889610 Jun 13 02:17:16 PM PDT 24 Jun 13 02:17:25 PM PDT 24 3832052942 ps
T873 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.4228659802 Jun 13 02:17:07 PM PDT 24 Jun 13 02:17:15 PM PDT 24 330536371 ps
T874 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.4082447957 Jun 13 02:17:07 PM PDT 24 Jun 13 02:17:18 PM PDT 24 832729549 ps
T875 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1661187588 Jun 13 02:17:36 PM PDT 24 Jun 13 02:17:39 PM PDT 24 352415304 ps
T876 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2194835357 Jun 13 02:17:19 PM PDT 24 Jun 13 02:17:25 PM PDT 24 421792727 ps
T877 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3158428571 Jun 13 02:17:10 PM PDT 24 Jun 13 02:17:17 PM PDT 24 931263935 ps
T878 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.4062390680 Jun 13 02:17:12 PM PDT 24 Jun 13 02:17:20 PM PDT 24 582426990 ps
T879 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1746111619 Jun 13 02:17:27 PM PDT 24 Jun 13 02:17:35 PM PDT 24 2047824734 ps
T880 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1461419663 Jun 13 02:17:10 PM PDT 24 Jun 13 02:17:22 PM PDT 24 4060978496 ps
T881 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.1060888097 Jun 13 02:17:11 PM PDT 24 Jun 13 02:17:20 PM PDT 24 2481274575 ps
T882 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2452670209 Jun 13 02:17:16 PM PDT 24 Jun 13 02:17:23 PM PDT 24 613954993 ps
T883 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1645300873 Jun 13 02:17:52 PM PDT 24 Jun 13 02:17:58 PM PDT 24 408323919 ps
T884 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.1408430094 Jun 13 02:17:12 PM PDT 24 Jun 13 02:17:19 PM PDT 24 327867581 ps
T885 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1440021990 Jun 13 02:17:25 PM PDT 24 Jun 13 02:17:48 PM PDT 24 5173021194 ps
T886 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3317996090 Jun 13 02:17:18 PM PDT 24 Jun 13 02:17:25 PM PDT 24 2333005689 ps
T72 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1959397198 Jun 13 02:17:24 PM PDT 24 Jun 13 02:17:40 PM PDT 24 4459927570 ps
T887 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3980332950 Jun 13 02:17:07 PM PDT 24 Jun 13 02:18:35 PM PDT 24 26497855270 ps
T888 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.4157956955 Jun 13 02:17:20 PM PDT 24 Jun 13 02:17:28 PM PDT 24 408116225 ps
T889 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.1702364302 Jun 13 02:17:22 PM PDT 24 Jun 13 02:17:27 PM PDT 24 472881067 ps
T890 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.3756686427 Jun 13 02:17:30 PM PDT 24 Jun 13 02:17:35 PM PDT 24 428921829 ps
T891 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1227051171 Jun 13 02:17:08 PM PDT 24 Jun 13 02:17:15 PM PDT 24 491421418 ps
T892 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2916508329 Jun 13 02:17:11 PM PDT 24 Jun 13 02:17:18 PM PDT 24 1393849889 ps
T893 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.2557035598 Jun 13 02:17:48 PM PDT 24 Jun 13 02:17:53 PM PDT 24 411176698 ps
T894 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2282694198 Jun 13 02:17:27 PM PDT 24 Jun 13 02:17:32 PM PDT 24 405675567 ps
T895 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.333981919 Jun 13 02:17:10 PM PDT 24 Jun 13 02:17:17 PM PDT 24 455436180 ps
T896 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.855846186 Jun 13 02:17:07 PM PDT 24 Jun 13 02:17:17 PM PDT 24 888284992 ps
T897 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2652005756 Jun 13 02:17:28 PM PDT 24 Jun 13 02:17:33 PM PDT 24 345842099 ps
T898 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3869131108 Jun 13 02:17:48 PM PDT 24 Jun 13 02:17:54 PM PDT 24 450712670 ps
T899 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3996891732 Jun 13 02:17:29 PM PDT 24 Jun 13 02:17:55 PM PDT 24 8214698592 ps
T900 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2980267826 Jun 13 02:17:04 PM PDT 24 Jun 13 02:17:14 PM PDT 24 996938966 ps
T901 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.326134831 Jun 13 02:17:44 PM PDT 24 Jun 13 02:17:46 PM PDT 24 426410996 ps
T902 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.50442454 Jun 13 02:17:49 PM PDT 24 Jun 13 02:17:56 PM PDT 24 387358204 ps
T903 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.1279918709 Jun 13 02:17:28 PM PDT 24 Jun 13 02:17:33 PM PDT 24 311795298 ps
T904 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.226410797 Jun 13 02:17:46 PM PDT 24 Jun 13 02:17:50 PM PDT 24 419062284 ps
T905 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2478742956 Jun 13 02:17:26 PM PDT 24 Jun 13 02:17:33 PM PDT 24 4225903914 ps
T906 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3718336853 Jun 13 02:17:28 PM PDT 24 Jun 13 02:17:34 PM PDT 24 536516426 ps
T907 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1447482308 Jun 13 02:17:17 PM PDT 24 Jun 13 02:17:34 PM PDT 24 4314089385 ps
T908 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3787256401 Jun 13 02:17:10 PM PDT 24 Jun 13 02:17:17 PM PDT 24 512748542 ps
T909 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1986052509 Jun 13 02:17:02 PM PDT 24 Jun 13 02:17:09 PM PDT 24 437211652 ps
T910 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.1567345732 Jun 13 02:17:04 PM PDT 24 Jun 13 02:17:32 PM PDT 24 8038878447 ps
T911 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.336042033 Jun 13 02:17:04 PM PDT 24 Jun 13 02:17:12 PM PDT 24 544085722 ps
T912 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.4043792208 Jun 13 02:17:16 PM PDT 24 Jun 13 02:17:23 PM PDT 24 464482361 ps
T913 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3510305773 Jun 13 02:17:28 PM PDT 24 Jun 13 02:17:32 PM PDT 24 562187248 ps
T914 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3643446176 Jun 13 02:17:17 PM PDT 24 Jun 13 02:17:23 PM PDT 24 535411908 ps
T915 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2671454634 Jun 13 02:17:03 PM PDT 24 Jun 13 02:17:10 PM PDT 24 781837645 ps
T916 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.358372208 Jun 13 02:17:08 PM PDT 24 Jun 13 02:17:20 PM PDT 24 3966905739 ps
T917 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.1228048484 Jun 13 02:17:07 PM PDT 24 Jun 13 02:17:28 PM PDT 24 21407581116 ps

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.1438450136
Short name T2
Test name
Test status
Simulation time 356964332488 ps
CPU time 361.1 seconds
Started Jun 13 02:32:03 PM PDT 24
Finished Jun 13 02:38:09 PM PDT 24
Peak memory 202288 kb
Host smart-3da2451f-ed71-40e2-b31a-1ce7d6dbf4b0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438450136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.1438450136
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.300865452
Short name T11
Test name
Test status
Simulation time 38237991994 ps
CPU time 102.25 seconds
Started Jun 13 02:31:40 PM PDT 24
Finished Jun 13 02:33:26 PM PDT 24
Peak memory 210884 kb
Host smart-d9c069a8-b82b-4cc0-858f-e72f393a860b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300865452 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.300865452
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.155484576
Short name T45
Test name
Test status
Simulation time 1353749431123 ps
CPU time 1100.07 seconds
Started Jun 13 02:35:25 PM PDT 24
Finished Jun 13 02:53:47 PM PDT 24
Peak memory 210768 kb
Host smart-3cb8e84b-c8dc-4df4-9139-8318f18c057f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155484576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all.
155484576
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.1754167704
Short name T171
Test name
Test status
Simulation time 620108196496 ps
CPU time 1401.92 seconds
Started Jun 13 02:35:35 PM PDT 24
Finished Jun 13 02:58:58 PM PDT 24
Peak memory 202504 kb
Host smart-20356f83-3a0a-4e50-baf2-c8fc86a702a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754167704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.1754167704
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.2146097153
Short name T40
Test name
Test status
Simulation time 543969382966 ps
CPU time 313.27 seconds
Started Jun 13 02:40:17 PM PDT 24
Finished Jun 13 02:45:35 PM PDT 24
Peak memory 202272 kb
Host smart-3a66404d-5ed4-4a90-8ddb-808fe8246c42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146097153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.2146097153
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.826895220
Short name T47
Test name
Test status
Simulation time 416415167309 ps
CPU time 486.15 seconds
Started Jun 13 02:31:53 PM PDT 24
Finished Jun 13 02:40:04 PM PDT 24
Peak memory 210684 kb
Host smart-9fec84db-03cd-4c44-9805-1d7202fee1c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826895220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all.
826895220
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.1366885748
Short name T8
Test name
Test status
Simulation time 489517599669 ps
CPU time 122.81 seconds
Started Jun 13 02:34:42 PM PDT 24
Finished Jun 13 02:36:46 PM PDT 24
Peak memory 202264 kb
Host smart-972017fb-b927-4af2-a4fb-5be49107d3bf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366885748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.1366885748
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.4159836796
Short name T35
Test name
Test status
Simulation time 384137979504 ps
CPU time 459.27 seconds
Started Jun 13 02:32:30 PM PDT 24
Finished Jun 13 02:40:14 PM PDT 24
Peak memory 218648 kb
Host smart-453181c2-905d-4be6-928b-151ce15b30bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159836796 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.4159836796
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.3934107710
Short name T80
Test name
Test status
Simulation time 530578873198 ps
CPU time 469.02 seconds
Started Jun 13 02:34:47 PM PDT 24
Finished Jun 13 02:42:37 PM PDT 24
Peak memory 202252 kb
Host smart-f9a5a981-6650-4e1d-ad4b-929cc72aab0e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934107710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.3934107710
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.1903058724
Short name T113
Test name
Test status
Simulation time 486775944644 ps
CPU time 123.19 seconds
Started Jun 13 02:33:23 PM PDT 24
Finished Jun 13 02:35:27 PM PDT 24
Peak memory 202168 kb
Host smart-d1d69224-534b-4e52-b2a5-c692cc0a173f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903058724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.1903058724
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1190724494
Short name T64
Test name
Test status
Simulation time 646160780 ps
CPU time 3.64 seconds
Started Jun 13 02:17:30 PM PDT 24
Finished Jun 13 02:17:38 PM PDT 24
Peak memory 217272 kb
Host smart-53830f83-3817-4325-be42-e75fda8f3cd5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190724494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.1190724494
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.2040213711
Short name T108
Test name
Test status
Simulation time 521058607846 ps
CPU time 1295.92 seconds
Started Jun 13 02:33:00 PM PDT 24
Finished Jun 13 02:54:38 PM PDT 24
Peak memory 202220 kb
Host smart-3745acd2-5bb7-4cb6-bdee-5a24b000d21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040213711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.2040213711
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.1830064646
Short name T61
Test name
Test status
Simulation time 8174951075 ps
CPU time 19.71 seconds
Started Jun 13 02:31:22 PM PDT 24
Finished Jun 13 02:31:45 PM PDT 24
Peak memory 218776 kb
Host smart-b78eb250-c051-46c1-a8d4-147f4412ab49
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830064646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.1830064646
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.619102060
Short name T36
Test name
Test status
Simulation time 341350943616 ps
CPU time 174.26 seconds
Started Jun 13 02:34:12 PM PDT 24
Finished Jun 13 02:37:07 PM PDT 24
Peak memory 211832 kb
Host smart-108e945a-75e6-430d-99c6-c91f125d4e8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619102060 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.619102060
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.3448083294
Short name T110
Test name
Test status
Simulation time 557155387504 ps
CPU time 1363.45 seconds
Started Jun 13 02:34:24 PM PDT 24
Finished Jun 13 02:57:09 PM PDT 24
Peak memory 202204 kb
Host smart-cfab1a20-2812-4d37-b948-d9d4630e3f15
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448083294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.3448083294
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.190096941
Short name T130
Test name
Test status
Simulation time 334064666867 ps
CPU time 373.63 seconds
Started Jun 13 02:59:21 PM PDT 24
Finished Jun 13 03:05:35 PM PDT 24
Peak memory 202304 kb
Host smart-0d7aa7f4-7a69-4323-a716-72348fbd395a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190096941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gati
ng.190096941
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3308401041
Short name T54
Test name
Test status
Simulation time 463906483 ps
CPU time 1.01 seconds
Started Jun 13 02:17:15 PM PDT 24
Finished Jun 13 02:17:21 PM PDT 24
Peak memory 201148 kb
Host smart-df5cf98d-5853-440c-97b4-3c92a8e86e9e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308401041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.3308401041
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.985081108
Short name T200
Test name
Test status
Simulation time 329868289542 ps
CPU time 581.18 seconds
Started Jun 13 02:31:50 PM PDT 24
Finished Jun 13 02:41:36 PM PDT 24
Peak memory 202180 kb
Host smart-72eaddcf-3768-41c4-b23e-aec8da77d3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985081108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.985081108
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.3826592213
Short name T154
Test name
Test status
Simulation time 539035451246 ps
CPU time 209.37 seconds
Started Jun 13 02:32:58 PM PDT 24
Finished Jun 13 02:36:29 PM PDT 24
Peak memory 202204 kb
Host smart-f6184068-d892-42fe-b061-6f182a114ee3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826592213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.3826592213
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.3733236645
Short name T205
Test name
Test status
Simulation time 516334350721 ps
CPU time 236.49 seconds
Started Jun 13 02:32:12 PM PDT 24
Finished Jun 13 02:36:16 PM PDT 24
Peak memory 202236 kb
Host smart-821e80a9-43cf-4f7f-ba9b-5e28e1813fa8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733236645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.3733236645
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.3731590542
Short name T104
Test name
Test status
Simulation time 516264348791 ps
CPU time 647.07 seconds
Started Jun 13 02:33:40 PM PDT 24
Finished Jun 13 02:44:29 PM PDT 24
Peak memory 202212 kb
Host smart-cb52d82e-8ee9-4a6a-a43f-8d479043409b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731590542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.3731590542
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.3589731602
Short name T150
Test name
Test status
Simulation time 484596721870 ps
CPU time 255.83 seconds
Started Jun 13 02:33:21 PM PDT 24
Finished Jun 13 02:37:38 PM PDT 24
Peak memory 202180 kb
Host smart-0830d437-5bbe-4317-a4cb-0ba2490a5e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589731602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.3589731602
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.3149034581
Short name T271
Test name
Test status
Simulation time 539063405567 ps
CPU time 145.89 seconds
Started Jun 13 02:35:29 PM PDT 24
Finished Jun 13 02:37:56 PM PDT 24
Peak memory 202280 kb
Host smart-26a5a41a-19d6-40d9-bcc2-624461a8b2a2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149034581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.3149034581
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.3580516163
Short name T111
Test name
Test status
Simulation time 496336706856 ps
CPU time 558.88 seconds
Started Jun 13 02:32:30 PM PDT 24
Finished Jun 13 02:41:53 PM PDT 24
Peak memory 202292 kb
Host smart-c7fcf1cf-aa85-459d-ad15-74bf06265418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580516163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.3580516163
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.661592112
Short name T246
Test name
Test status
Simulation time 500928008288 ps
CPU time 1141.11 seconds
Started Jun 13 02:32:00 PM PDT 24
Finished Jun 13 02:51:06 PM PDT 24
Peak memory 202252 kb
Host smart-0891df3d-cb1f-41bc-8c26-84071db1ab05
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661592112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gati
ng.661592112
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.2264970276
Short name T13
Test name
Test status
Simulation time 601695907979 ps
CPU time 348.96 seconds
Started Jun 13 02:31:43 PM PDT 24
Finished Jun 13 02:37:36 PM PDT 24
Peak memory 202268 kb
Host smart-5ae5c382-16bd-445d-b529-dc86ee2b75fb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264970276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.2264970276
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.2674903234
Short name T240
Test name
Test status
Simulation time 499554997366 ps
CPU time 319.73 seconds
Started Jun 13 02:32:22 PM PDT 24
Finished Jun 13 02:37:50 PM PDT 24
Peak memory 202176 kb
Host smart-10f5c871-b4f2-4c1d-92a8-6a838ffd2c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674903234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.2674903234
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.2553388732
Short name T206
Test name
Test status
Simulation time 486501467371 ps
CPU time 558.99 seconds
Started Jun 13 02:31:57 PM PDT 24
Finished Jun 13 02:41:21 PM PDT 24
Peak memory 202256 kb
Host smart-a374822f-1b99-4619-9bd4-f1a77e9898a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553388732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.2553388732
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.287101149
Short name T347
Test name
Test status
Simulation time 338848945 ps
CPU time 1.4 seconds
Started Jun 13 02:31:56 PM PDT 24
Finished Jun 13 02:32:02 PM PDT 24
Peak memory 201884 kb
Host smart-28aa7a99-fc18-4755-a1b7-5a4c32b77f71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287101149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.287101149
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.3377344492
Short name T278
Test name
Test status
Simulation time 561829725562 ps
CPU time 1269.74 seconds
Started Jun 13 02:31:59 PM PDT 24
Finished Jun 13 02:53:14 PM PDT 24
Peak memory 202248 kb
Host smart-367aeefc-21c7-45bf-abdb-9354e6c0b5f1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377344492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.3377344492
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.73827278
Short name T250
Test name
Test status
Simulation time 313489825191 ps
CPU time 1037.36 seconds
Started Jun 13 02:34:14 PM PDT 24
Finished Jun 13 02:51:33 PM PDT 24
Peak memory 202592 kb
Host smart-5817da35-3233-438e-85cf-810575fb7571
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73827278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all.73827278
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1613922817
Short name T169
Test name
Test status
Simulation time 4416245211 ps
CPU time 10.75 seconds
Started Jun 13 02:17:23 PM PDT 24
Finished Jun 13 02:17:38 PM PDT 24
Peak memory 201376 kb
Host smart-3e1ab5d0-f4ac-49b1-9227-5f6ab6cda3f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613922817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.1613922817
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.2727395436
Short name T189
Test name
Test status
Simulation time 469806318868 ps
CPU time 407.73 seconds
Started Jun 13 02:32:39 PM PDT 24
Finished Jun 13 02:39:29 PM PDT 24
Peak memory 202196 kb
Host smart-73ba51d2-8f9f-4943-834a-8ec4417af675
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727395436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.2727395436
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.2233473248
Short name T234
Test name
Test status
Simulation time 355546666137 ps
CPU time 793.26 seconds
Started Jun 13 02:35:06 PM PDT 24
Finished Jun 13 02:48:20 PM PDT 24
Peak memory 202228 kb
Host smart-a9ace4e3-f755-4760-a48e-aa7a4a98206d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233473248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.2233473248
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.1293820017
Short name T194
Test name
Test status
Simulation time 620824465851 ps
CPU time 471.67 seconds
Started Jun 13 02:31:25 PM PDT 24
Finished Jun 13 02:39:22 PM PDT 24
Peak memory 202200 kb
Host smart-e9aa4284-27e7-468f-bb93-8c5184b1a864
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293820017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.1293820017
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.3068968055
Short name T217
Test name
Test status
Simulation time 162204234155 ps
CPU time 44.34 seconds
Started Jun 13 02:31:57 PM PDT 24
Finished Jun 13 02:32:45 PM PDT 24
Peak memory 202268 kb
Host smart-7b1ceffd-68e3-41f8-9e32-56d1c22ccff6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068968055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.3068968055
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.3666363535
Short name T122
Test name
Test status
Simulation time 522286981064 ps
CPU time 314.06 seconds
Started Jun 13 02:31:58 PM PDT 24
Finished Jun 13 02:37:17 PM PDT 24
Peak memory 202204 kb
Host smart-187af7f7-9e2e-403c-83e6-480f8e9406a1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666363535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.3666363535
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.3442847587
Short name T144
Test name
Test status
Simulation time 505490548537 ps
CPU time 198.7 seconds
Started Jun 13 02:32:04 PM PDT 24
Finished Jun 13 02:35:29 PM PDT 24
Peak memory 202224 kb
Host smart-e8c59537-a7d0-4d88-ab83-81f6575046d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442847587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.3442847587
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.1980900046
Short name T233
Test name
Test status
Simulation time 408077448181 ps
CPU time 247.2 seconds
Started Jun 13 02:34:42 PM PDT 24
Finished Jun 13 02:38:51 PM PDT 24
Peak memory 210828 kb
Host smart-3403a06e-3ce4-4aaf-ab00-37e11eefba59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980900046 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.1980900046
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.2265672753
Short name T276
Test name
Test status
Simulation time 501527585900 ps
CPU time 1135.27 seconds
Started Jun 13 02:32:01 PM PDT 24
Finished Jun 13 02:51:01 PM PDT 24
Peak memory 202292 kb
Host smart-b772df74-35cd-4205-9378-b299ecd1eafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265672753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.2265672753
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.1838426894
Short name T261
Test name
Test status
Simulation time 266190991698 ps
CPU time 289.83 seconds
Started Jun 13 02:33:06 PM PDT 24
Finished Jun 13 02:37:58 PM PDT 24
Peak memory 202144 kb
Host smart-bb3ae0a8-e40a-40cb-9a22-7b189c87d23c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838426894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.1838426894
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.157627235
Short name T172
Test name
Test status
Simulation time 2284344453841 ps
CPU time 1982.78 seconds
Started Jun 13 02:32:00 PM PDT 24
Finished Jun 13 03:05:08 PM PDT 24
Peak memory 210656 kb
Host smart-399d03f8-52ee-452c-a59d-ff8b7ad706b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157627235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all.
157627235
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.3413062014
Short name T115
Test name
Test status
Simulation time 334029792535 ps
CPU time 113.89 seconds
Started Jun 13 02:31:27 PM PDT 24
Finished Jun 13 02:33:25 PM PDT 24
Peak memory 202240 kb
Host smart-3ad86bad-43ff-4de0-aae7-c8f80b74dad7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413062014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.3413062014
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.1301246630
Short name T65
Test name
Test status
Simulation time 427151050 ps
CPU time 2.25 seconds
Started Jun 13 02:17:21 PM PDT 24
Finished Jun 13 02:17:28 PM PDT 24
Peak memory 201424 kb
Host smart-baac7865-df09-41f0-ac15-4896a1320e2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301246630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.1301246630
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.2772297570
Short name T137
Test name
Test status
Simulation time 1033686758780 ps
CPU time 507.44 seconds
Started Jun 13 02:32:02 PM PDT 24
Finished Jun 13 02:40:35 PM PDT 24
Peak memory 210792 kb
Host smart-609ba84f-74ec-4ebf-830d-17135ed98d58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772297570 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.2772297570
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.2153905681
Short name T198
Test name
Test status
Simulation time 394649065305 ps
CPU time 429.2 seconds
Started Jun 13 02:33:28 PM PDT 24
Finished Jun 13 02:40:39 PM PDT 24
Peak memory 202272 kb
Host smart-72af5f4a-4f40-4481-837e-dea570987563
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153905681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.2153905681
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.531618678
Short name T247
Test name
Test status
Simulation time 49675914689 ps
CPU time 73.76 seconds
Started Jun 13 02:32:26 PM PDT 24
Finished Jun 13 02:33:46 PM PDT 24
Peak memory 218160 kb
Host smart-4662e7d6-731a-4df9-ae89-c2f3632e21ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531618678 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.531618678
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.1992296590
Short name T187
Test name
Test status
Simulation time 372071209939 ps
CPU time 847.23 seconds
Started Jun 13 02:32:25 PM PDT 24
Finished Jun 13 02:46:39 PM PDT 24
Peak memory 202208 kb
Host smart-ddcc1ed7-2423-4512-be18-a3fef6015202
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992296590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.1992296590
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.3296690474
Short name T151
Test name
Test status
Simulation time 543445283094 ps
CPU time 297.34 seconds
Started Jun 13 02:33:12 PM PDT 24
Finished Jun 13 02:38:10 PM PDT 24
Peak memory 202264 kb
Host smart-dea187cd-5ba2-42ae-bf7a-4ed82ca73db6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296690474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.3296690474
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.2946419415
Short name T260
Test name
Test status
Simulation time 589540906245 ps
CPU time 1310.52 seconds
Started Jun 13 02:32:03 PM PDT 24
Finished Jun 13 02:53:59 PM PDT 24
Peak memory 202256 kb
Host smart-da0bc1fb-444f-4bde-b25b-d2131ac4e561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946419415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.2946419415
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.1561456786
Short name T199
Test name
Test status
Simulation time 549736685720 ps
CPU time 308.16 seconds
Started Jun 13 02:33:49 PM PDT 24
Finished Jun 13 02:38:59 PM PDT 24
Peak memory 202176 kb
Host smart-dba2b343-ed8f-4833-86a3-3661c3462a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561456786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.1561456786
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.3857306298
Short name T254
Test name
Test status
Simulation time 489808546307 ps
CPU time 1077.36 seconds
Started Jun 13 02:34:37 PM PDT 24
Finished Jun 13 02:52:36 PM PDT 24
Peak memory 202204 kb
Host smart-60746600-dc6b-4ca2-8359-64d2fa73bccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857306298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.3857306298
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.1000671870
Short name T266
Test name
Test status
Simulation time 331157243217 ps
CPU time 220.94 seconds
Started Jun 13 02:32:12 PM PDT 24
Finished Jun 13 02:36:01 PM PDT 24
Peak memory 202368 kb
Host smart-d562c24b-9f58-4a25-a4a7-681df6e0d13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000671870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.1000671870
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.2306685654
Short name T291
Test name
Test status
Simulation time 325959720810 ps
CPU time 359.61 seconds
Started Jun 13 02:32:52 PM PDT 24
Finished Jun 13 02:38:53 PM PDT 24
Peak memory 202208 kb
Host smart-0ad20737-7d4d-4342-930c-25ca72158016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306685654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.2306685654
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.2064864109
Short name T273
Test name
Test status
Simulation time 364042159442 ps
CPU time 175.2 seconds
Started Jun 13 02:31:48 PM PDT 24
Finished Jun 13 02:34:46 PM PDT 24
Peak memory 202280 kb
Host smart-02ce4aaa-7a7c-4962-8f7e-e4f4b945dea0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064864109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.2064864109
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.3057510115
Short name T229
Test name
Test status
Simulation time 327270567706 ps
CPU time 363.32 seconds
Started Jun 13 02:33:05 PM PDT 24
Finished Jun 13 02:39:10 PM PDT 24
Peak memory 202188 kb
Host smart-2403b719-398c-4dcb-b7cd-d1a2cf7f2979
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057510115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.3057510115
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.2473822922
Short name T134
Test name
Test status
Simulation time 374405363884 ps
CPU time 78.75 seconds
Started Jun 13 02:33:06 PM PDT 24
Finished Jun 13 02:34:27 PM PDT 24
Peak memory 202276 kb
Host smart-4ca4aba7-4c2d-4ec5-aa15-e2d01c112289
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473822922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.2473822922
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.2507875901
Short name T24
Test name
Test status
Simulation time 265224362385 ps
CPU time 238.6 seconds
Started Jun 13 02:33:56 PM PDT 24
Finished Jun 13 02:37:56 PM PDT 24
Peak memory 219180 kb
Host smart-1ad957b0-56ef-4c0e-b8b3-5041d2c87154
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507875901 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.2507875901
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.702381428
Short name T258
Test name
Test status
Simulation time 351449284150 ps
CPU time 834.23 seconds
Started Jun 13 02:31:26 PM PDT 24
Finished Jun 13 02:45:26 PM PDT 24
Peak memory 202196 kb
Host smart-959db8e7-fce1-49b6-a9cf-e7554c165316
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702381428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_w
akeup.702381428
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.2170163966
Short name T44
Test name
Test status
Simulation time 115083424321 ps
CPU time 496.48 seconds
Started Jun 13 02:34:15 PM PDT 24
Finished Jun 13 02:42:33 PM PDT 24
Peak memory 202520 kb
Host smart-7b70be57-076b-40b6-9c88-49308f715019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170163966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.2170163966
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.945428434
Short name T94
Test name
Test status
Simulation time 26822865350 ps
CPU time 14.77 seconds
Started Jun 13 02:17:17 PM PDT 24
Finished Jun 13 02:17:37 PM PDT 24
Peak memory 201428 kb
Host smart-a87e0700-f5ab-4d08-b16c-11da9edfbd72
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945428434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_b
ash.945428434
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.2491609228
Short name T227
Test name
Test status
Simulation time 183696908147 ps
CPU time 210.85 seconds
Started Jun 13 02:31:49 PM PDT 24
Finished Jun 13 02:35:23 PM PDT 24
Peak memory 202228 kb
Host smart-d2b9af77-b701-4d85-a509-a74576121afc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491609228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.2491609228
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.2274730165
Short name T241
Test name
Test status
Simulation time 346622501005 ps
CPU time 760.77 seconds
Started Jun 13 02:32:47 PM PDT 24
Finished Jun 13 02:45:30 PM PDT 24
Peak memory 202276 kb
Host smart-06118dfd-ae6b-43ed-acca-337acdc701e7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274730165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.2274730165
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.3772090522
Short name T112
Test name
Test status
Simulation time 327556532587 ps
CPU time 755.53 seconds
Started Jun 13 02:33:54 PM PDT 24
Finished Jun 13 02:46:30 PM PDT 24
Peak memory 202320 kb
Host smart-03d57e65-54d6-4a26-bfcf-6021d32fc50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772090522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.3772090522
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.2413929531
Short name T174
Test name
Test status
Simulation time 115266321011 ps
CPU time 423.19 seconds
Started Jun 13 02:34:00 PM PDT 24
Finished Jun 13 02:41:05 PM PDT 24
Peak memory 202496 kb
Host smart-ef3e954a-6860-42c2-b2c1-b26b4a8ee339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413929531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.2413929531
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.2927867421
Short name T309
Test name
Test status
Simulation time 490331101726 ps
CPU time 1169.51 seconds
Started Jun 13 02:31:52 PM PDT 24
Finished Jun 13 02:51:26 PM PDT 24
Peak memory 202272 kb
Host smart-414ea4b0-20c2-4e7b-bab1-540e06b80335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927867421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.2927867421
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.1614165779
Short name T341
Test name
Test status
Simulation time 490797223019 ps
CPU time 1125.84 seconds
Started Jun 13 02:32:02 PM PDT 24
Finished Jun 13 02:50:53 PM PDT 24
Peak memory 202196 kb
Host smart-12b0407f-e065-4be0-8932-6df2f25b174e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614165779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.1614165779
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.791377449
Short name T245
Test name
Test status
Simulation time 160396684898 ps
CPU time 198.24 seconds
Started Jun 13 02:32:17 PM PDT 24
Finished Jun 13 02:35:43 PM PDT 24
Peak memory 202188 kb
Host smart-ce3f6f2b-4211-452a-b1e5-5593b1039fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791377449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.791377449
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.3696815388
Short name T131
Test name
Test status
Simulation time 344987480602 ps
CPU time 396.86 seconds
Started Jun 13 02:32:48 PM PDT 24
Finished Jun 13 02:39:26 PM PDT 24
Peak memory 202232 kb
Host smart-64e834b6-c954-4837-87f2-595073ca39a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696815388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.3696815388
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.3598613892
Short name T289
Test name
Test status
Simulation time 74644423405 ps
CPU time 44.31 seconds
Started Jun 13 02:32:59 PM PDT 24
Finished Jun 13 02:33:45 PM PDT 24
Peak memory 210592 kb
Host smart-1f2fef72-5510-4231-89ab-e0ce769c028e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598613892 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.3598613892
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.60234936
Short name T255
Test name
Test status
Simulation time 485730393837 ps
CPU time 561.3 seconds
Started Jun 13 02:33:46 PM PDT 24
Finished Jun 13 02:43:08 PM PDT 24
Peak memory 202244 kb
Host smart-35d4a2eb-9810-4e82-ade9-701a85261b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60234936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.60234936
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.3928117955
Short name T292
Test name
Test status
Simulation time 495397445285 ps
CPU time 1060.7 seconds
Started Jun 13 02:34:04 PM PDT 24
Finished Jun 13 02:51:46 PM PDT 24
Peak memory 202212 kb
Host smart-364cbb49-966f-47e8-b4ad-8dccb77983da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928117955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.3928117955
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.1550880026
Short name T236
Test name
Test status
Simulation time 160544716560 ps
CPU time 382.37 seconds
Started Jun 13 02:34:24 PM PDT 24
Finished Jun 13 02:40:48 PM PDT 24
Peak memory 202264 kb
Host smart-b32be48c-b5f5-4ea7-8c91-159acec40eef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550880026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.1550880026
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.3645912731
Short name T188
Test name
Test status
Simulation time 325425914393 ps
CPU time 717.91 seconds
Started Jun 13 02:34:20 PM PDT 24
Finished Jun 13 02:46:20 PM PDT 24
Peak memory 202316 kb
Host smart-1491372c-87ff-40a7-82f5-a6c2d1bb9d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645912731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.3645912731
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.1865218133
Short name T282
Test name
Test status
Simulation time 511831568083 ps
CPU time 288.81 seconds
Started Jun 13 02:34:33 PM PDT 24
Finished Jun 13 02:39:23 PM PDT 24
Peak memory 202192 kb
Host smart-95c72cae-c571-4fcd-8b1c-7249f5057f50
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865218133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.1865218133
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.1567345732
Short name T910
Test name
Test status
Simulation time 8038878447 ps
CPU time 21.08 seconds
Started Jun 13 02:17:04 PM PDT 24
Finished Jun 13 02:17:32 PM PDT 24
Peak memory 201540 kb
Host smart-b5c48f04-bfd7-4fb3-8377-45b84ff998df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567345732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.1567345732
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.2890787528
Short name T195
Test name
Test status
Simulation time 177571734674 ps
CPU time 112.42 seconds
Started Jun 13 02:31:36 PM PDT 24
Finished Jun 13 02:33:34 PM PDT 24
Peak memory 202196 kb
Host smart-d8e7294a-831e-4f7d-a2f3-4d16155f48ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890787528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
2890787528
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.4019414194
Short name T259
Test name
Test status
Simulation time 226632116070 ps
CPU time 488.65 seconds
Started Jun 13 02:31:24 PM PDT 24
Finished Jun 13 02:39:37 PM PDT 24
Peak memory 202240 kb
Host smart-2fbaa6c6-1c68-4aad-ad25-06c549d5d1f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019414194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
4019414194
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.3667758421
Short name T178
Test name
Test status
Simulation time 84361371853 ps
CPU time 424.18 seconds
Started Jun 13 02:31:56 PM PDT 24
Finished Jun 13 02:39:04 PM PDT 24
Peak memory 202544 kb
Host smart-02e422c4-4d8f-4b2c-a255-61789aa3faed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667758421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.3667758421
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.4242007815
Short name T269
Test name
Test status
Simulation time 341089232022 ps
CPU time 179.05 seconds
Started Jun 13 02:32:00 PM PDT 24
Finished Jun 13 02:35:05 PM PDT 24
Peak memory 202240 kb
Host smart-4bcd9594-21c4-4cf9-bb10-a282a6184f5e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242007815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.4242007815
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.2405894302
Short name T221
Test name
Test status
Simulation time 326386330163 ps
CPU time 371.33 seconds
Started Jun 13 02:32:16 PM PDT 24
Finished Jun 13 02:38:34 PM PDT 24
Peak memory 202284 kb
Host smart-ab504410-98f7-4022-b091-0bd2c7e0f23b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405894302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.2405894302
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.2888795576
Short name T264
Test name
Test status
Simulation time 365106256636 ps
CPU time 869.09 seconds
Started Jun 13 02:32:26 PM PDT 24
Finished Jun 13 02:47:02 PM PDT 24
Peak memory 202208 kb
Host smart-000b11cd-fd20-4b49-891a-b72f30b69643
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888795576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.2888795576
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.801199125
Short name T218
Test name
Test status
Simulation time 326710645490 ps
CPU time 747.86 seconds
Started Jun 13 02:32:26 PM PDT 24
Finished Jun 13 02:45:01 PM PDT 24
Peak memory 202148 kb
Host smart-fd96adb9-005d-417f-bb04-3e378deb0097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801199125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.801199125
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.2236158083
Short name T32
Test name
Test status
Simulation time 211863506862 ps
CPU time 362.33 seconds
Started Jun 13 02:32:50 PM PDT 24
Finished Jun 13 02:38:53 PM PDT 24
Peak memory 210832 kb
Host smart-f737608f-56c8-4252-b6d9-17772a8924e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236158083 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.2236158083
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.3579521938
Short name T120
Test name
Test status
Simulation time 258467612123 ps
CPU time 260.41 seconds
Started Jun 13 02:33:00 PM PDT 24
Finished Jun 13 02:37:22 PM PDT 24
Peak memory 211076 kb
Host smart-fce19a23-0f67-4e59-b245-4c7e1088838f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579521938 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.3579521938
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.4272646519
Short name T173
Test name
Test status
Simulation time 101009109464 ps
CPU time 340.94 seconds
Started Jun 13 02:49:47 PM PDT 24
Finished Jun 13 02:55:44 PM PDT 24
Peak memory 202560 kb
Host smart-154b571c-59c8-4c4d-9a9c-cf06448e8715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272646519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.4272646519
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.266511493
Short name T294
Test name
Test status
Simulation time 391076603924 ps
CPU time 255.82 seconds
Started Jun 13 02:33:41 PM PDT 24
Finished Jun 13 02:37:58 PM PDT 24
Peak memory 202172 kb
Host smart-cea86ee5-9c5e-41a9-8a9b-560e6bb4b06b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266511493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_
wakeup.266511493
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.4136180207
Short name T328
Test name
Test status
Simulation time 111572048712 ps
CPU time 603.77 seconds
Started Jun 13 02:31:32 PM PDT 24
Finished Jun 13 02:41:42 PM PDT 24
Peak memory 202508 kb
Host smart-ce9f2ac0-a82a-4bfe-b713-3be3ed54b0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136180207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.4136180207
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.3233888160
Short name T181
Test name
Test status
Simulation time 126987756649 ps
CPU time 452.37 seconds
Started Jun 13 02:34:37 PM PDT 24
Finished Jun 13 02:42:10 PM PDT 24
Peak memory 202528 kb
Host smart-eca42010-0820-4449-80b3-59d55e823486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233888160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.3233888160
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.2263511123
Short name T124
Test name
Test status
Simulation time 342993040124 ps
CPU time 196.36 seconds
Started Jun 13 02:31:31 PM PDT 24
Finished Jun 13 02:34:52 PM PDT 24
Peak memory 202272 kb
Host smart-4a8cec6b-a236-415e-b492-012388fa077b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263511123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.2263511123
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2980267826
Short name T900
Test name
Test status
Simulation time 996938966 ps
CPU time 3 seconds
Started Jun 13 02:17:04 PM PDT 24
Finished Jun 13 02:17:14 PM PDT 24
Peak memory 201312 kb
Host smart-40104d65-4467-4efd-88dd-46926cd52ceb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980267826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.2980267826
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2920587678
Short name T92
Test name
Test status
Simulation time 1039373342 ps
CPU time 1.89 seconds
Started Jun 13 02:17:02 PM PDT 24
Finished Jun 13 02:17:10 PM PDT 24
Peak memory 201092 kb
Host smart-7ea5aa8c-d5ab-4fe6-b67b-27ebcc93b7b0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920587678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.2920587678
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1986052509
Short name T909
Test name
Test status
Simulation time 437211652 ps
CPU time 1.07 seconds
Started Jun 13 02:17:02 PM PDT 24
Finished Jun 13 02:17:09 PM PDT 24
Peak memory 201216 kb
Host smart-f7347c6d-f7b7-4ae1-8bbf-6ccb747032e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986052509 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.1986052509
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2490002508
Short name T101
Test name
Test status
Simulation time 421479831 ps
CPU time 1.03 seconds
Started Jun 13 02:17:04 PM PDT 24
Finished Jun 13 02:17:12 PM PDT 24
Peak memory 201132 kb
Host smart-30bcf637-d6d7-4dda-a8f9-d3aef0796f94
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490002508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.2490002508
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1318658663
Short name T797
Test name
Test status
Simulation time 490691482 ps
CPU time 1.15 seconds
Started Jun 13 02:17:03 PM PDT 24
Finished Jun 13 02:17:10 PM PDT 24
Peak memory 201156 kb
Host smart-7614ff7b-052d-40f9-8f1d-b9780426bb8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318658663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.1318658663
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.1520909111
Short name T845
Test name
Test status
Simulation time 3411767743 ps
CPU time 4.31 seconds
Started Jun 13 02:17:02 PM PDT 24
Finished Jun 13 02:17:13 PM PDT 24
Peak memory 201372 kb
Host smart-4b0ddde2-2f12-48da-9f05-66cc8e5a7b87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520909111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.1520909111
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1047113053
Short name T840
Test name
Test status
Simulation time 611503180 ps
CPU time 3 seconds
Started Jun 13 02:17:03 PM PDT 24
Finished Jun 13 02:17:12 PM PDT 24
Peak memory 217804 kb
Host smart-4f9cd6a9-e995-474b-822a-ec97f250f1c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047113053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.1047113053
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3417024659
Short name T90
Test name
Test status
Simulation time 1190641195 ps
CPU time 5.29 seconds
Started Jun 13 02:17:08 PM PDT 24
Finished Jun 13 02:17:19 PM PDT 24
Peak memory 201340 kb
Host smart-b4839ceb-a0d6-4111-adc7-633740436630
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417024659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.3417024659
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.1228048484
Short name T917
Test name
Test status
Simulation time 21407581116 ps
CPU time 14.4 seconds
Started Jun 13 02:17:07 PM PDT 24
Finished Jun 13 02:17:28 PM PDT 24
Peak memory 201400 kb
Host smart-9ef19b80-3a93-4b6e-bf37-3ea3929a51d4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228048484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.1228048484
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2671454634
Short name T915
Test name
Test status
Simulation time 781837645 ps
CPU time 1.61 seconds
Started Jun 13 02:17:03 PM PDT 24
Finished Jun 13 02:17:10 PM PDT 24
Peak memory 201152 kb
Host smart-bff4ed5e-ab90-4ffe-b077-84215ba94600
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671454634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.2671454634
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.511520395
Short name T855
Test name
Test status
Simulation time 633128813 ps
CPU time 1.31 seconds
Started Jun 13 02:17:10 PM PDT 24
Finished Jun 13 02:17:16 PM PDT 24
Peak memory 201212 kb
Host smart-31440813-a1b3-4f5b-a9d3-09541e95def4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511520395 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.511520395
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2792233909
Short name T100
Test name
Test status
Simulation time 413392777 ps
CPU time 1.05 seconds
Started Jun 13 02:17:11 PM PDT 24
Finished Jun 13 02:17:17 PM PDT 24
Peak memory 201152 kb
Host smart-504a7dfb-7736-4592-b6a4-7141fc41c410
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792233909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.2792233909
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.2547311384
Short name T862
Test name
Test status
Simulation time 370380180 ps
CPU time 1.49 seconds
Started Jun 13 02:17:04 PM PDT 24
Finished Jun 13 02:17:12 PM PDT 24
Peak memory 201148 kb
Host smart-d1ac693b-00a1-4876-a93f-ec3512335925
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547311384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.2547311384
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.992665063
Short name T870
Test name
Test status
Simulation time 2348092400 ps
CPU time 5.68 seconds
Started Jun 13 02:17:07 PM PDT 24
Finished Jun 13 02:17:19 PM PDT 24
Peak memory 201200 kb
Host smart-0ce8b531-fa94-408d-b0c2-49f97dcb411d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992665063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ct
rl_same_csr_outstanding.992665063
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.336042033
Short name T911
Test name
Test status
Simulation time 544085722 ps
CPU time 1.74 seconds
Started Jun 13 02:17:04 PM PDT 24
Finished Jun 13 02:17:12 PM PDT 24
Peak memory 201480 kb
Host smart-d31eebf5-683c-469c-b4ce-5bd57a0d06ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336042033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.336042033
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1829402017
Short name T857
Test name
Test status
Simulation time 4881734265 ps
CPU time 4.07 seconds
Started Jun 13 02:17:02 PM PDT 24
Finished Jun 13 02:17:12 PM PDT 24
Peak memory 201376 kb
Host smart-af6535f2-26b1-4b8e-94b2-61be1a0f2e03
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829402017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.1829402017
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2109644616
Short name T86
Test name
Test status
Simulation time 587217084 ps
CPU time 1.27 seconds
Started Jun 13 02:17:17 PM PDT 24
Finished Jun 13 02:17:23 PM PDT 24
Peak memory 201212 kb
Host smart-d215fc71-6561-47d3-bc20-d90b7fe0a565
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109644616 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.2109644616
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2340347247
Short name T98
Test name
Test status
Simulation time 544899438 ps
CPU time 1.15 seconds
Started Jun 13 02:17:16 PM PDT 24
Finished Jun 13 02:17:22 PM PDT 24
Peak memory 201148 kb
Host smart-fe4d5495-bb05-4708-8c8c-21a59c09e0fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340347247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.2340347247
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.4043792208
Short name T912
Test name
Test status
Simulation time 464482361 ps
CPU time 1.77 seconds
Started Jun 13 02:17:16 PM PDT 24
Finished Jun 13 02:17:23 PM PDT 24
Peak memory 201136 kb
Host smart-934b4377-e345-4fb2-8479-99278cb6be8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043792208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.4043792208
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.284995772
Short name T818
Test name
Test status
Simulation time 2057439207 ps
CPU time 2.88 seconds
Started Jun 13 02:17:14 PM PDT 24
Finished Jun 13 02:17:22 PM PDT 24
Peak memory 201152 kb
Host smart-810b3f1d-a38d-4060-87b6-70cacec88c3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284995772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_c
trl_same_csr_outstanding.284995772
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1854411676
Short name T832
Test name
Test status
Simulation time 573009096 ps
CPU time 2.36 seconds
Started Jun 13 02:17:15 PM PDT 24
Finished Jun 13 02:17:23 PM PDT 24
Peak memory 209580 kb
Host smart-679ff4e2-b30d-4b23-bfbb-9327e8b79a9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854411676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.1854411676
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.717011253
Short name T824
Test name
Test status
Simulation time 4219079020 ps
CPU time 11.44 seconds
Started Jun 13 02:17:16 PM PDT 24
Finished Jun 13 02:17:32 PM PDT 24
Peak memory 201372 kb
Host smart-109eba6a-6746-4948-af2f-0d34352fd7ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717011253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_in
tg_err.717011253
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3714709590
Short name T85
Test name
Test status
Simulation time 551862012 ps
CPU time 1.22 seconds
Started Jun 13 02:17:22 PM PDT 24
Finished Jun 13 02:17:28 PM PDT 24
Peak memory 201348 kb
Host smart-1b10d501-b1f5-4596-94b3-5155af55bd4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714709590 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.3714709590
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.4287865454
Short name T95
Test name
Test status
Simulation time 535347535 ps
CPU time 1.92 seconds
Started Jun 13 02:17:20 PM PDT 24
Finished Jun 13 02:17:27 PM PDT 24
Peak memory 201148 kb
Host smart-dac38855-3511-4c63-a039-2bcd44895056
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287865454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.4287865454
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.1702364302
Short name T889
Test name
Test status
Simulation time 472881067 ps
CPU time 1.22 seconds
Started Jun 13 02:17:22 PM PDT 24
Finished Jun 13 02:17:27 PM PDT 24
Peak memory 201116 kb
Host smart-a78c091a-84eb-44da-b886-a11a6282e733
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702364302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.1702364302
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2007531847
Short name T865
Test name
Test status
Simulation time 2541482568 ps
CPU time 6.17 seconds
Started Jun 13 02:17:23 PM PDT 24
Finished Jun 13 02:17:33 PM PDT 24
Peak memory 201188 kb
Host smart-51d21364-0061-4aa4-8aea-3537c053293a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007531847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.2007531847
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.3964702603
Short name T59
Test name
Test status
Simulation time 341950994 ps
CPU time 1.72 seconds
Started Jun 13 02:17:18 PM PDT 24
Finished Jun 13 02:17:24 PM PDT 24
Peak memory 201388 kb
Host smart-7dd65d49-ab97-4c8c-9342-9c59bf6d8d2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964702603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.3964702603
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.4175751017
Short name T852
Test name
Test status
Simulation time 520443816 ps
CPU time 2.08 seconds
Started Jun 13 02:17:22 PM PDT 24
Finished Jun 13 02:17:28 PM PDT 24
Peak memory 201212 kb
Host smart-281483ed-8c80-4257-a5a6-c7a81646a360
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175751017 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.4175751017
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1351267354
Short name T96
Test name
Test status
Simulation time 499195035 ps
CPU time 1.08 seconds
Started Jun 13 02:17:20 PM PDT 24
Finished Jun 13 02:17:26 PM PDT 24
Peak memory 201148 kb
Host smart-5072690d-e0b4-40ec-82d4-15c0d902d50b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351267354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.1351267354
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3182831527
Short name T866
Test name
Test status
Simulation time 521055061 ps
CPU time 1.93 seconds
Started Jun 13 02:17:19 PM PDT 24
Finished Jun 13 02:17:26 PM PDT 24
Peak memory 201136 kb
Host smart-3061e357-c7cf-46e0-9fad-29b0e5831ee8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182831527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.3182831527
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.167392756
Short name T102
Test name
Test status
Simulation time 2076940624 ps
CPU time 2.81 seconds
Started Jun 13 02:17:21 PM PDT 24
Finished Jun 13 02:17:28 PM PDT 24
Peak memory 201164 kb
Host smart-bdd81f7a-527a-489d-8f13-effd546e0239
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167392756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_c
trl_same_csr_outstanding.167392756
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1016074972
Short name T869
Test name
Test status
Simulation time 564584459 ps
CPU time 1.8 seconds
Started Jun 13 02:17:22 PM PDT 24
Finished Jun 13 02:17:28 PM PDT 24
Peak memory 201424 kb
Host smart-aa833bbf-195e-49cc-8e81-d4beb79c419b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016074972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.1016074972
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.589173005
Short name T57
Test name
Test status
Simulation time 4519458080 ps
CPU time 3.13 seconds
Started Jun 13 02:17:34 PM PDT 24
Finished Jun 13 02:17:39 PM PDT 24
Peak memory 201404 kb
Host smart-83e0a092-ccce-4e03-ac1e-da95238dfa51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589173005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_in
tg_err.589173005
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2194835357
Short name T876
Test name
Test status
Simulation time 421792727 ps
CPU time 1.82 seconds
Started Jun 13 02:17:19 PM PDT 24
Finished Jun 13 02:17:25 PM PDT 24
Peak memory 201212 kb
Host smart-8139cb87-226c-48b0-99ed-aefac951a0eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194835357 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.2194835357
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1371710753
Short name T87
Test name
Test status
Simulation time 615183518 ps
CPU time 0.95 seconds
Started Jun 13 02:17:28 PM PDT 24
Finished Jun 13 02:17:32 PM PDT 24
Peak memory 200964 kb
Host smart-607cea22-5c04-4499-b1f2-966aeb7c255d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371710753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.1371710753
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.2300012216
Short name T813
Test name
Test status
Simulation time 522341385 ps
CPU time 1.02 seconds
Started Jun 13 02:17:21 PM PDT 24
Finished Jun 13 02:17:27 PM PDT 24
Peak memory 201132 kb
Host smart-030c48b4-1623-4cd1-83d3-ca54aa6d9699
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300012216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.2300012216
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1440021990
Short name T885
Test name
Test status
Simulation time 5173021194 ps
CPU time 18.78 seconds
Started Jun 13 02:17:25 PM PDT 24
Finished Jun 13 02:17:48 PM PDT 24
Peak memory 201436 kb
Host smart-d9e58e1c-420b-4096-84d4-72baf07e5ab1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440021990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.1440021990
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2382784041
Short name T66
Test name
Test status
Simulation time 547319990 ps
CPU time 2.95 seconds
Started Jun 13 02:17:21 PM PDT 24
Finished Jun 13 02:17:28 PM PDT 24
Peak memory 201416 kb
Host smart-010bd131-4d85-454f-bb78-1ee662381c3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382784041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.2382784041
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2015649329
Short name T67
Test name
Test status
Simulation time 4397951985 ps
CPU time 4.27 seconds
Started Jun 13 02:17:23 PM PDT 24
Finished Jun 13 02:17:31 PM PDT 24
Peak memory 201384 kb
Host smart-b5266ebd-5ec2-4b40-a61e-2345bd581f4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015649329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.2015649329
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.724653585
Short name T868
Test name
Test status
Simulation time 823820359 ps
CPU time 1.18 seconds
Started Jun 13 02:17:23 PM PDT 24
Finished Jun 13 02:17:28 PM PDT 24
Peak memory 201256 kb
Host smart-8bfaf702-b80a-44fe-92de-2e99d6333f00
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724653585 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.724653585
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2282694198
Short name T894
Test name
Test status
Simulation time 405675567 ps
CPU time 1 seconds
Started Jun 13 02:17:27 PM PDT 24
Finished Jun 13 02:17:32 PM PDT 24
Peak memory 201156 kb
Host smart-1cf185b2-d7bc-4c11-b1cd-d742d65ec8c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282694198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.2282694198
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.2513471856
Short name T835
Test name
Test status
Simulation time 487608036 ps
CPU time 1.24 seconds
Started Jun 13 02:17:24 PM PDT 24
Finished Jun 13 02:17:30 PM PDT 24
Peak memory 201136 kb
Host smart-122d844a-82cd-4d6f-989b-8fd8c510ab6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513471856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.2513471856
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1407644032
Short name T51
Test name
Test status
Simulation time 2576736472 ps
CPU time 5.2 seconds
Started Jun 13 02:17:27 PM PDT 24
Finished Jun 13 02:17:36 PM PDT 24
Peak memory 201200 kb
Host smart-7b384371-343b-46a8-8e8d-b10c26539533
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407644032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.1407644032
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.4157956955
Short name T888
Test name
Test status
Simulation time 408116225 ps
CPU time 3.65 seconds
Started Jun 13 02:17:20 PM PDT 24
Finished Jun 13 02:17:28 PM PDT 24
Peak memory 210624 kb
Host smart-e0dfc278-0dca-4682-afd1-5253bdaf8b14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157956955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.4157956955
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1374983191
Short name T55
Test name
Test status
Simulation time 8117877764 ps
CPU time 5.31 seconds
Started Jun 13 02:17:20 PM PDT 24
Finished Jun 13 02:17:30 PM PDT 24
Peak memory 201424 kb
Host smart-3a4bb89f-9318-4bd0-8230-f701b51a7c09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374983191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.1374983191
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3809024264
Short name T69
Test name
Test status
Simulation time 529376882 ps
CPU time 2.06 seconds
Started Jun 13 02:17:22 PM PDT 24
Finished Jun 13 02:17:28 PM PDT 24
Peak memory 201216 kb
Host smart-adcf5569-1df1-4592-ab95-494b45b4c4fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809024264 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.3809024264
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3768188373
Short name T836
Test name
Test status
Simulation time 548021651 ps
CPU time 1.32 seconds
Started Jun 13 02:17:28 PM PDT 24
Finished Jun 13 02:17:33 PM PDT 24
Peak memory 200944 kb
Host smart-0fe288bf-9459-4a94-87d4-33726a9743f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768188373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.3768188373
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1664212735
Short name T834
Test name
Test status
Simulation time 547418672 ps
CPU time 0.9 seconds
Started Jun 13 02:17:27 PM PDT 24
Finished Jun 13 02:17:31 PM PDT 24
Peak memory 201144 kb
Host smart-a2d817b3-82cd-4c7f-8a65-dbb4881f16b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664212735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.1664212735
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3480304699
Short name T849
Test name
Test status
Simulation time 2119677108 ps
CPU time 5.03 seconds
Started Jun 13 02:17:19 PM PDT 24
Finished Jun 13 02:17:29 PM PDT 24
Peak memory 201164 kb
Host smart-065935d5-96b6-433e-8a55-1e45b083bd5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480304699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.3480304699
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.824716549
Short name T856
Test name
Test status
Simulation time 458682826 ps
CPU time 2.41 seconds
Started Jun 13 02:17:22 PM PDT 24
Finished Jun 13 02:17:28 PM PDT 24
Peak memory 209608 kb
Host smart-dfbbf854-8f01-45b8-bef9-3aa17e7823e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824716549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.824716549
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1959397198
Short name T72
Test name
Test status
Simulation time 4459927570 ps
CPU time 12 seconds
Started Jun 13 02:17:24 PM PDT 24
Finished Jun 13 02:17:40 PM PDT 24
Peak memory 201428 kb
Host smart-042f643d-1571-4baa-aa80-32e30d950283
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959397198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.1959397198
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2202501804
Short name T823
Test name
Test status
Simulation time 325582525 ps
CPU time 1.54 seconds
Started Jun 13 02:17:24 PM PDT 24
Finished Jun 13 02:17:30 PM PDT 24
Peak memory 201064 kb
Host smart-4cf5b52d-0dab-45e5-a8fb-6f831b185e71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202501804 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.2202501804
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.100342390
Short name T88
Test name
Test status
Simulation time 359056918 ps
CPU time 1.7 seconds
Started Jun 13 02:17:22 PM PDT 24
Finished Jun 13 02:17:28 PM PDT 24
Peak memory 201148 kb
Host smart-0ef0ec7a-2da0-4c28-83ff-bac0bf6dfb32
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100342390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.100342390
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3982942019
Short name T796
Test name
Test status
Simulation time 524064180 ps
CPU time 1.86 seconds
Started Jun 13 02:17:23 PM PDT 24
Finished Jun 13 02:17:29 PM PDT 24
Peak memory 201140 kb
Host smart-a7c9fdf4-4397-42ca-849a-98b9e581d695
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982942019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.3982942019
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.4145070581
Short name T53
Test name
Test status
Simulation time 2217193353 ps
CPU time 2.8 seconds
Started Jun 13 02:17:41 PM PDT 24
Finished Jun 13 02:17:45 PM PDT 24
Peak memory 201228 kb
Host smart-77d75951-9a78-4dd6-8256-51b2c56bd0da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145070581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.4145070581
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.4074548031
Short name T170
Test name
Test status
Simulation time 7681847514 ps
CPU time 7.44 seconds
Started Jun 13 02:17:20 PM PDT 24
Finished Jun 13 02:17:32 PM PDT 24
Peak memory 201372 kb
Host smart-883d3bcf-e3d5-4945-9249-eec5ba477130
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074548031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.4074548031
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.154127697
Short name T826
Test name
Test status
Simulation time 478789236 ps
CPU time 1.09 seconds
Started Jun 13 02:17:22 PM PDT 24
Finished Jun 13 02:17:27 PM PDT 24
Peak memory 201216 kb
Host smart-66462fba-096f-47ac-80da-880d0fce366e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154127697 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.154127697
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1243907617
Short name T850
Test name
Test status
Simulation time 570874803 ps
CPU time 1.03 seconds
Started Jun 13 02:17:20 PM PDT 24
Finished Jun 13 02:17:26 PM PDT 24
Peak memory 201152 kb
Host smart-e7240766-0a38-43cf-b269-5674e574719b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243907617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.1243907617
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3510305773
Short name T913
Test name
Test status
Simulation time 562187248 ps
CPU time 0.89 seconds
Started Jun 13 02:17:28 PM PDT 24
Finished Jun 13 02:17:32 PM PDT 24
Peak memory 201116 kb
Host smart-96f91c08-ac6e-4b6b-bad6-5ec013477f70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510305773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.3510305773
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1746111619
Short name T879
Test name
Test status
Simulation time 2047824734 ps
CPU time 4.54 seconds
Started Jun 13 02:17:27 PM PDT 24
Finished Jun 13 02:17:35 PM PDT 24
Peak memory 201148 kb
Host smart-2c0bc72a-d601-4fe3-a7cd-346d8d2ceeb3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746111619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.1746111619
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2620847546
Short name T58
Test name
Test status
Simulation time 1840142437 ps
CPU time 2.6 seconds
Started Jun 13 02:17:27 PM PDT 24
Finished Jun 13 02:17:33 PM PDT 24
Peak memory 209584 kb
Host smart-693933cd-7d36-4cac-a4da-a4a759bd1fe8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620847546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.2620847546
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2478742956
Short name T905
Test name
Test status
Simulation time 4225903914 ps
CPU time 3.82 seconds
Started Jun 13 02:17:26 PM PDT 24
Finished Jun 13 02:17:33 PM PDT 24
Peak memory 201376 kb
Host smart-60867e95-46c4-4553-b8c6-92ccefc6a97e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478742956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.2478742956
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2216929686
Short name T831
Test name
Test status
Simulation time 429217409 ps
CPU time 1.76 seconds
Started Jun 13 02:17:36 PM PDT 24
Finished Jun 13 02:17:39 PM PDT 24
Peak memory 201164 kb
Host smart-cbf9b42c-0c8f-4c2e-a80a-bdabeaaf30cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216929686 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.2216929686
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3718336853
Short name T906
Test name
Test status
Simulation time 536516426 ps
CPU time 1.91 seconds
Started Jun 13 02:17:28 PM PDT 24
Finished Jun 13 02:17:34 PM PDT 24
Peak memory 201148 kb
Host smart-89dac832-dd5b-4f12-abe0-d8171b8388d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718336853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.3718336853
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.454275954
Short name T795
Test name
Test status
Simulation time 311977641 ps
CPU time 1.35 seconds
Started Jun 13 02:17:31 PM PDT 24
Finished Jun 13 02:17:37 PM PDT 24
Peak memory 201148 kb
Host smart-d06a6d49-b4cd-4a17-9e27-67aac9863b5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454275954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.454275954
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2200695481
Short name T806
Test name
Test status
Simulation time 2450664577 ps
CPU time 2.19 seconds
Started Jun 13 02:17:28 PM PDT 24
Finished Jun 13 02:17:34 PM PDT 24
Peak memory 201228 kb
Host smart-02d5c1e2-416f-42d7-9507-48913f404e3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200695481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.2200695481
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.709818187
Short name T830
Test name
Test status
Simulation time 398973498 ps
CPU time 3.04 seconds
Started Jun 13 02:17:29 PM PDT 24
Finished Jun 13 02:17:36 PM PDT 24
Peak memory 217252 kb
Host smart-52af0d84-a4f3-4116-a824-96918359eb6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709818187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.709818187
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2088678207
Short name T68
Test name
Test status
Simulation time 4341065192 ps
CPU time 3.76 seconds
Started Jun 13 02:17:29 PM PDT 24
Finished Jun 13 02:17:36 PM PDT 24
Peak memory 201408 kb
Host smart-5f96c395-8853-4828-9ce2-cf540ee8b02d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088678207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.2088678207
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1075243176
Short name T863
Test name
Test status
Simulation time 457944531 ps
CPU time 1.1 seconds
Started Jun 13 02:17:30 PM PDT 24
Finished Jun 13 02:17:34 PM PDT 24
Peak memory 201256 kb
Host smart-8d2bea37-2b08-490b-887b-e2214bf48c00
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075243176 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.1075243176
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1661187588
Short name T875
Test name
Test status
Simulation time 352415304 ps
CPU time 1.65 seconds
Started Jun 13 02:17:36 PM PDT 24
Finished Jun 13 02:17:39 PM PDT 24
Peak memory 201076 kb
Host smart-87578a43-94ed-435f-bcb6-835a7346e35d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661187588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.1661187588
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.670719469
Short name T825
Test name
Test status
Simulation time 369679933 ps
CPU time 1.1 seconds
Started Jun 13 02:17:29 PM PDT 24
Finished Jun 13 02:17:33 PM PDT 24
Peak memory 201148 kb
Host smart-6a20a634-5203-4280-a7f4-cd6ea1b10183
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670719469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.670719469
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.4245747310
Short name T52
Test name
Test status
Simulation time 4509830428 ps
CPU time 6.11 seconds
Started Jun 13 02:17:28 PM PDT 24
Finished Jun 13 02:17:38 PM PDT 24
Peak memory 201428 kb
Host smart-d6edcf41-4ec3-4ac7-9326-c9128ca9847a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245747310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.4245747310
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3996891732
Short name T899
Test name
Test status
Simulation time 8214698592 ps
CPU time 22.61 seconds
Started Jun 13 02:17:29 PM PDT 24
Finished Jun 13 02:17:55 PM PDT 24
Peak memory 201352 kb
Host smart-0a1040b1-f12c-45fb-83b7-cfff87b101b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996891732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.3996891732
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.283287139
Short name T815
Test name
Test status
Simulation time 1361304226 ps
CPU time 2.73 seconds
Started Jun 13 02:17:13 PM PDT 24
Finished Jun 13 02:17:21 PM PDT 24
Peak memory 201336 kb
Host smart-52ae4b5e-0413-4881-af38-49a28e59e606
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283287139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alias
ing.283287139
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.4250754321
Short name T89
Test name
Test status
Simulation time 39637788261 ps
CPU time 125.81 seconds
Started Jun 13 02:17:11 PM PDT 24
Finished Jun 13 02:19:22 PM PDT 24
Peak memory 201404 kb
Host smart-fcd9df00-e582-4ede-8139-fe67eb55fe97
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250754321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.4250754321
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2105874339
Short name T91
Test name
Test status
Simulation time 1385128447 ps
CPU time 1.71 seconds
Started Jun 13 02:17:07 PM PDT 24
Finished Jun 13 02:17:15 PM PDT 24
Peak memory 201144 kb
Host smart-5214bfe2-4f56-450c-8251-10b980552c54
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105874339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.2105874339
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3757017475
Short name T819
Test name
Test status
Simulation time 736429891 ps
CPU time 1.37 seconds
Started Jun 13 02:17:11 PM PDT 24
Finished Jun 13 02:17:18 PM PDT 24
Peak memory 201244 kb
Host smart-6bdb6a11-d7fc-4bf9-8df9-321f7bf0add1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757017475 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.3757017475
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3919823209
Short name T97
Test name
Test status
Simulation time 488286790 ps
CPU time 0.95 seconds
Started Jun 13 02:17:12 PM PDT 24
Finished Jun 13 02:17:19 PM PDT 24
Peak memory 201092 kb
Host smart-3a396765-4de0-4798-adf9-1cab9ca35eee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919823209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.3919823209
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.1408430094
Short name T884
Test name
Test status
Simulation time 327867581 ps
CPU time 0.77 seconds
Started Jun 13 02:17:12 PM PDT 24
Finished Jun 13 02:17:19 PM PDT 24
Peak memory 201144 kb
Host smart-0dd70007-7c7f-4f93-bb4c-68e37cad59ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408430094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.1408430094
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3570890273
Short name T805
Test name
Test status
Simulation time 4978429360 ps
CPU time 3.45 seconds
Started Jun 13 02:17:07 PM PDT 24
Finished Jun 13 02:17:17 PM PDT 24
Peak memory 201440 kb
Host smart-a50b503c-4f76-40c8-95cd-c20445883535
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570890273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.3570890273
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.4046435966
Short name T867
Test name
Test status
Simulation time 428677515 ps
CPU time 2.18 seconds
Started Jun 13 02:17:10 PM PDT 24
Finished Jun 13 02:17:18 PM PDT 24
Peak memory 201468 kb
Host smart-0090da12-3553-490f-ba18-83bdf60fa7a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046435966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.4046435966
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2597332892
Short name T844
Test name
Test status
Simulation time 4088305762 ps
CPU time 5.19 seconds
Started Jun 13 02:17:08 PM PDT 24
Finished Jun 13 02:17:20 PM PDT 24
Peak memory 201444 kb
Host smart-db1e2157-1d42-4c88-80f0-91620a3471e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597332892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.2597332892
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.29208275
Short name T854
Test name
Test status
Simulation time 313707214 ps
CPU time 1.26 seconds
Started Jun 13 02:17:27 PM PDT 24
Finished Jun 13 02:17:32 PM PDT 24
Peak memory 201136 kb
Host smart-96d0a486-b340-44a5-b544-6fafff136f2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29208275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.29208275
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.2107452676
Short name T851
Test name
Test status
Simulation time 501982171 ps
CPU time 0.94 seconds
Started Jun 13 02:17:29 PM PDT 24
Finished Jun 13 02:17:34 PM PDT 24
Peak memory 201136 kb
Host smart-4bdcc4f6-2bf6-4300-88e7-bfebef750187
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107452676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.2107452676
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.3055514213
Short name T822
Test name
Test status
Simulation time 417913106 ps
CPU time 1.56 seconds
Started Jun 13 02:17:27 PM PDT 24
Finished Jun 13 02:17:32 PM PDT 24
Peak memory 201144 kb
Host smart-d6ed4844-23f9-4ac4-b152-29098e1828f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055514213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.3055514213
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.942287342
Short name T846
Test name
Test status
Simulation time 407857605 ps
CPU time 1.12 seconds
Started Jun 13 02:17:31 PM PDT 24
Finished Jun 13 02:17:36 PM PDT 24
Peak memory 201148 kb
Host smart-f1336a37-bcd2-43bb-9c7c-d43410d5d414
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942287342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.942287342
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.1279918709
Short name T903
Test name
Test status
Simulation time 311795298 ps
CPU time 1 seconds
Started Jun 13 02:17:28 PM PDT 24
Finished Jun 13 02:17:33 PM PDT 24
Peak memory 201136 kb
Host smart-4b72fc3a-0b5d-4e8a-a232-29c15fba3404
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279918709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.1279918709
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2652005756
Short name T897
Test name
Test status
Simulation time 345842099 ps
CPU time 1.44 seconds
Started Jun 13 02:17:28 PM PDT 24
Finished Jun 13 02:17:33 PM PDT 24
Peak memory 201116 kb
Host smart-c4179b16-e70e-4c0d-83a8-a13743a2ba45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652005756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.2652005756
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.101280070
Short name T871
Test name
Test status
Simulation time 525464678 ps
CPU time 1.22 seconds
Started Jun 13 02:17:36 PM PDT 24
Finished Jun 13 02:17:39 PM PDT 24
Peak memory 201188 kb
Host smart-257799ff-9ae7-4c74-90e6-67892c5739c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101280070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.101280070
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2880426311
Short name T841
Test name
Test status
Simulation time 520940836 ps
CPU time 1.22 seconds
Started Jun 13 02:17:26 PM PDT 24
Finished Jun 13 02:17:31 PM PDT 24
Peak memory 201136 kb
Host smart-1d4f49d2-ae6e-46ad-b06a-8cbc67f7a56b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880426311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.2880426311
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2213466198
Short name T843
Test name
Test status
Simulation time 466126383 ps
CPU time 0.9 seconds
Started Jun 13 02:17:29 PM PDT 24
Finished Jun 13 02:17:33 PM PDT 24
Peak memory 201088 kb
Host smart-9bfae034-9362-447f-8239-c8d8cf0643e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213466198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.2213466198
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.3125086674
Short name T829
Test name
Test status
Simulation time 297437038 ps
CPU time 1.34 seconds
Started Jun 13 02:17:30 PM PDT 24
Finished Jun 13 02:17:35 PM PDT 24
Peak memory 201136 kb
Host smart-818e3998-5a91-421c-9b53-b3d263564aae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125086674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.3125086674
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.4082447957
Short name T874
Test name
Test status
Simulation time 832729549 ps
CPU time 3.96 seconds
Started Jun 13 02:17:07 PM PDT 24
Finished Jun 13 02:17:18 PM PDT 24
Peak memory 201300 kb
Host smart-f8787a7d-d839-4eae-8394-dc11be5d746b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082447957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.4082447957
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3574997879
Short name T99
Test name
Test status
Simulation time 51535837926 ps
CPU time 48.8 seconds
Started Jun 13 02:17:10 PM PDT 24
Finished Jun 13 02:18:05 PM PDT 24
Peak memory 201404 kb
Host smart-b239f3f6-7b47-4019-84fb-25edef504eda
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574997879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.3574997879
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3158428571
Short name T877
Test name
Test status
Simulation time 931263935 ps
CPU time 1.04 seconds
Started Jun 13 02:17:10 PM PDT 24
Finished Jun 13 02:17:17 PM PDT 24
Peak memory 201140 kb
Host smart-4842c4c2-33b3-41b7-8571-2eee1d3186cc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158428571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.3158428571
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.4062390680
Short name T878
Test name
Test status
Simulation time 582426990 ps
CPU time 2.19 seconds
Started Jun 13 02:17:12 PM PDT 24
Finished Jun 13 02:17:20 PM PDT 24
Peak memory 201216 kb
Host smart-8a0cf1c6-612a-4660-960c-326f4790c247
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062390680 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.4062390680
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1597664848
Short name T93
Test name
Test status
Simulation time 409639838 ps
CPU time 1.3 seconds
Started Jun 13 02:17:08 PM PDT 24
Finished Jun 13 02:17:15 PM PDT 24
Peak memory 201152 kb
Host smart-303a1f6f-dad7-473d-89cd-671266e55acd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597664848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.1597664848
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.4208352935
Short name T838
Test name
Test status
Simulation time 392651164 ps
CPU time 0.85 seconds
Started Jun 13 02:17:08 PM PDT 24
Finished Jun 13 02:17:15 PM PDT 24
Peak memory 201148 kb
Host smart-1eee0c4d-f975-4be5-a83a-011b05039912
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208352935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.4208352935
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.1060888097
Short name T881
Test name
Test status
Simulation time 2481274575 ps
CPU time 3.37 seconds
Started Jun 13 02:17:11 PM PDT 24
Finished Jun 13 02:17:20 PM PDT 24
Peak memory 201216 kb
Host smart-1e137cb4-5e4e-4490-b17a-a08e4cadfffa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060888097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.1060888097
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.855846186
Short name T896
Test name
Test status
Simulation time 888284992 ps
CPU time 2.75 seconds
Started Jun 13 02:17:07 PM PDT 24
Finished Jun 13 02:17:17 PM PDT 24
Peak memory 209644 kb
Host smart-25e1c752-d1ba-4374-9dea-c064db004c78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855846186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.855846186
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.358372208
Short name T916
Test name
Test status
Simulation time 3966905739 ps
CPU time 5.88 seconds
Started Jun 13 02:17:08 PM PDT 24
Finished Jun 13 02:17:20 PM PDT 24
Peak memory 201404 kb
Host smart-37be2d0d-7bd0-492f-a1b9-4823519e941e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358372208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_int
g_err.358372208
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.325454969
Short name T804
Test name
Test status
Simulation time 398779639 ps
CPU time 1.6 seconds
Started Jun 13 02:17:36 PM PDT 24
Finished Jun 13 02:17:39 PM PDT 24
Peak memory 201180 kb
Host smart-98ef5feb-176d-4992-a030-5e0419c198a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325454969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.325454969
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1255427174
Short name T799
Test name
Test status
Simulation time 520906245 ps
CPU time 1.8 seconds
Started Jun 13 02:17:29 PM PDT 24
Finished Jun 13 02:17:34 PM PDT 24
Peak memory 201128 kb
Host smart-7b25af7c-6985-4332-9b16-ff3a03d19124
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255427174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.1255427174
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.3756686427
Short name T890
Test name
Test status
Simulation time 428921829 ps
CPU time 0.91 seconds
Started Jun 13 02:17:30 PM PDT 24
Finished Jun 13 02:17:35 PM PDT 24
Peak memory 201144 kb
Host smart-3e1234c2-90a0-4925-b1c5-e2e24ae3d08a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756686427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.3756686427
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1645300873
Short name T883
Test name
Test status
Simulation time 408323919 ps
CPU time 1.16 seconds
Started Jun 13 02:17:52 PM PDT 24
Finished Jun 13 02:17:58 PM PDT 24
Peak memory 201136 kb
Host smart-a5a89e3d-8027-4c96-ae5c-f9d113177b3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645300873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.1645300873
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.207792878
Short name T808
Test name
Test status
Simulation time 443426270 ps
CPU time 1.11 seconds
Started Jun 13 02:17:49 PM PDT 24
Finished Jun 13 02:17:55 PM PDT 24
Peak memory 201156 kb
Host smart-da3df5e1-b907-4ed2-8f8f-b307029a9d33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207792878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.207792878
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.2557035598
Short name T893
Test name
Test status
Simulation time 411176698 ps
CPU time 1.53 seconds
Started Jun 13 02:17:48 PM PDT 24
Finished Jun 13 02:17:53 PM PDT 24
Peak memory 201136 kb
Host smart-edf33f69-b24e-459a-b819-b9872e17bafb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557035598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.2557035598
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.4184232299
Short name T794
Test name
Test status
Simulation time 335717055 ps
CPU time 1.37 seconds
Started Jun 13 02:17:44 PM PDT 24
Finished Jun 13 02:17:47 PM PDT 24
Peak memory 201132 kb
Host smart-793a7657-8751-4be5-af7a-cc787ef77099
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184232299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.4184232299
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3773815019
Short name T800
Test name
Test status
Simulation time 319706424 ps
CPU time 0.97 seconds
Started Jun 13 02:17:50 PM PDT 24
Finished Jun 13 02:17:57 PM PDT 24
Peak memory 201172 kb
Host smart-4aba27ca-9073-4401-9035-af52e2864665
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773815019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.3773815019
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.226410797
Short name T904
Test name
Test status
Simulation time 419062284 ps
CPU time 0.94 seconds
Started Jun 13 02:17:46 PM PDT 24
Finished Jun 13 02:17:50 PM PDT 24
Peak memory 201276 kb
Host smart-b1f53c93-b510-4aaf-b09e-fa571e7fcef5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226410797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.226410797
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.1388078925
Short name T812
Test name
Test status
Simulation time 493986449 ps
CPU time 0.87 seconds
Started Jun 13 02:17:49 PM PDT 24
Finished Jun 13 02:17:56 PM PDT 24
Peak memory 201112 kb
Host smart-6473fbb4-7caf-42a1-989d-88c93ef691c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388078925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.1388078925
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.2700149299
Short name T810
Test name
Test status
Simulation time 769266973 ps
CPU time 3.54 seconds
Started Jun 13 02:17:10 PM PDT 24
Finished Jun 13 02:17:19 PM PDT 24
Peak memory 201352 kb
Host smart-8a73c875-c682-4917-bb1b-b70ac0fc5e8b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700149299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.2700149299
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3980332950
Short name T887
Test name
Test status
Simulation time 26497855270 ps
CPU time 82.52 seconds
Started Jun 13 02:17:07 PM PDT 24
Finished Jun 13 02:18:35 PM PDT 24
Peak memory 201412 kb
Host smart-32a401f3-c78a-4f0a-94c6-f30194a00419
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980332950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.3980332950
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2916508329
Short name T892
Test name
Test status
Simulation time 1393849889 ps
CPU time 1.48 seconds
Started Jun 13 02:17:11 PM PDT 24
Finished Jun 13 02:17:18 PM PDT 24
Peak memory 201208 kb
Host smart-4ebd5933-65df-49fd-b043-93f41b46f483
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916508329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.2916508329
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.4240444474
Short name T860
Test name
Test status
Simulation time 595570747 ps
CPU time 1.58 seconds
Started Jun 13 02:17:13 PM PDT 24
Finished Jun 13 02:17:20 PM PDT 24
Peak memory 201216 kb
Host smart-e61de5f8-363a-42d0-ba97-2f2e43551e58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240444474 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.4240444474
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.333981919
Short name T895
Test name
Test status
Simulation time 455436180 ps
CPU time 1.01 seconds
Started Jun 13 02:17:10 PM PDT 24
Finished Jun 13 02:17:17 PM PDT 24
Peak memory 201172 kb
Host smart-9d9b010d-6dac-4acd-b1aa-358c9431e144
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333981919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.333981919
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2598914606
Short name T833
Test name
Test status
Simulation time 535316923 ps
CPU time 0.81 seconds
Started Jun 13 02:17:12 PM PDT 24
Finished Jun 13 02:17:19 PM PDT 24
Peak memory 201116 kb
Host smart-0bc2985a-bd79-48f6-854a-55508df50230
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598914606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.2598914606
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2511977198
Short name T817
Test name
Test status
Simulation time 4531778278 ps
CPU time 16.22 seconds
Started Jun 13 02:17:11 PM PDT 24
Finished Jun 13 02:17:33 PM PDT 24
Peak memory 201408 kb
Host smart-8706011d-8075-4744-986c-ac6c6df39855
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511977198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.2511977198
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2004916290
Short name T814
Test name
Test status
Simulation time 1016194982 ps
CPU time 3.26 seconds
Started Jun 13 02:17:11 PM PDT 24
Finished Jun 13 02:17:19 PM PDT 24
Peak memory 201472 kb
Host smart-ec33bb78-3919-45e2-8cb0-c0836a99e928
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004916290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.2004916290
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1461419663
Short name T880
Test name
Test status
Simulation time 4060978496 ps
CPU time 6.42 seconds
Started Jun 13 02:17:10 PM PDT 24
Finished Jun 13 02:17:22 PM PDT 24
Peak memory 201468 kb
Host smart-058f178c-a077-407c-b533-e6f524e2822f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461419663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.1461419663
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3869131108
Short name T898
Test name
Test status
Simulation time 450712670 ps
CPU time 1.05 seconds
Started Jun 13 02:17:48 PM PDT 24
Finished Jun 13 02:17:54 PM PDT 24
Peak memory 201132 kb
Host smart-41262ab9-51dd-476a-a85c-afaf84d2df8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869131108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.3869131108
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.2032498952
Short name T793
Test name
Test status
Simulation time 317448053 ps
CPU time 1.38 seconds
Started Jun 13 02:17:48 PM PDT 24
Finished Jun 13 02:17:54 PM PDT 24
Peak memory 201144 kb
Host smart-1ab193da-bd85-4ef0-91bf-bc1776fe5633
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032498952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.2032498952
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.1099196273
Short name T828
Test name
Test status
Simulation time 485954253 ps
CPU time 1.69 seconds
Started Jun 13 02:17:43 PM PDT 24
Finished Jun 13 02:17:46 PM PDT 24
Peak memory 201136 kb
Host smart-aa4ba8e6-9b64-4ed9-b6d4-640de5913b67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099196273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.1099196273
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.3475163888
Short name T802
Test name
Test status
Simulation time 411720606 ps
CPU time 0.86 seconds
Started Jun 13 02:17:44 PM PDT 24
Finished Jun 13 02:17:45 PM PDT 24
Peak memory 201140 kb
Host smart-3fe8ff81-c284-48ac-9a66-681a6ad06af9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475163888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.3475163888
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3619573078
Short name T811
Test name
Test status
Simulation time 457672116 ps
CPU time 0.9 seconds
Started Jun 13 02:17:52 PM PDT 24
Finished Jun 13 02:17:58 PM PDT 24
Peak memory 201104 kb
Host smart-3aef584f-5cd0-4508-8854-751184e4d092
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619573078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.3619573078
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.2855111393
Short name T839
Test name
Test status
Simulation time 367926854 ps
CPU time 1.58 seconds
Started Jun 13 02:17:52 PM PDT 24
Finished Jun 13 02:17:59 PM PDT 24
Peak memory 201136 kb
Host smart-f3740f73-1ca3-4807-b56f-72465271a391
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855111393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.2855111393
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.3579165022
Short name T821
Test name
Test status
Simulation time 297489756 ps
CPU time 0.95 seconds
Started Jun 13 02:17:48 PM PDT 24
Finished Jun 13 02:17:54 PM PDT 24
Peak memory 201148 kb
Host smart-5b406bd9-e02b-4776-8423-e5915efc1a45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579165022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.3579165022
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.326134831
Short name T901
Test name
Test status
Simulation time 426410996 ps
CPU time 1.17 seconds
Started Jun 13 02:17:44 PM PDT 24
Finished Jun 13 02:17:46 PM PDT 24
Peak memory 201144 kb
Host smart-107956d8-6f60-4c8e-8e6a-fe29088709a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326134831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.326134831
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.50442454
Short name T902
Test name
Test status
Simulation time 387358204 ps
CPU time 1.6 seconds
Started Jun 13 02:17:49 PM PDT 24
Finished Jun 13 02:17:56 PM PDT 24
Peak memory 201152 kb
Host smart-5ec1d188-5a39-4c39-aed4-01b465d1d897
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50442454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.50442454
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.1400596449
Short name T859
Test name
Test status
Simulation time 360589289 ps
CPU time 0.85 seconds
Started Jun 13 02:17:48 PM PDT 24
Finished Jun 13 02:17:53 PM PDT 24
Peak memory 201128 kb
Host smart-6c254e78-3cb3-48f8-8e91-83d9b55368cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400596449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.1400596449
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.355393895
Short name T809
Test name
Test status
Simulation time 649763514 ps
CPU time 1.34 seconds
Started Jun 13 02:17:08 PM PDT 24
Finished Jun 13 02:17:16 PM PDT 24
Peak memory 201216 kb
Host smart-ffc1ffb0-eada-4cc3-816b-1952c6c3fa6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355393895 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.355393895
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.4228659802
Short name T873
Test name
Test status
Simulation time 330536371 ps
CPU time 1.15 seconds
Started Jun 13 02:17:07 PM PDT 24
Finished Jun 13 02:17:15 PM PDT 24
Peak memory 201160 kb
Host smart-d696c3ba-c50b-453a-9309-73c56d894ee4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228659802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.4228659802
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3787256401
Short name T908
Test name
Test status
Simulation time 512748542 ps
CPU time 1.73 seconds
Started Jun 13 02:17:10 PM PDT 24
Finished Jun 13 02:17:17 PM PDT 24
Peak memory 201156 kb
Host smart-57370a98-7754-4f5b-b0b7-8c37fda91311
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787256401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.3787256401
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.1379927648
Short name T858
Test name
Test status
Simulation time 5073739797 ps
CPU time 7.59 seconds
Started Jun 13 02:17:10 PM PDT 24
Finished Jun 13 02:17:23 PM PDT 24
Peak memory 201452 kb
Host smart-da7b8d3d-15f3-4cec-a7a9-c2e535baede7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379927648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.1379927648
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.2224248095
Short name T63
Test name
Test status
Simulation time 390413966 ps
CPU time 1.76 seconds
Started Jun 13 02:17:08 PM PDT 24
Finished Jun 13 02:17:16 PM PDT 24
Peak memory 201408 kb
Host smart-2675afd2-c013-443a-bb8d-c6eb870f683f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224248095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.2224248095
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3674934341
Short name T56
Test name
Test status
Simulation time 8493544692 ps
CPU time 22.34 seconds
Started Jun 13 02:17:07 PM PDT 24
Finished Jun 13 02:17:36 PM PDT 24
Peak memory 201364 kb
Host smart-b9f6a087-0564-4f00-a136-8a9162d3d367
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674934341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.3674934341
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1945344737
Short name T60
Test name
Test status
Simulation time 542803086 ps
CPU time 2.15 seconds
Started Jun 13 02:17:07 PM PDT 24
Finished Jun 13 02:17:16 PM PDT 24
Peak memory 201228 kb
Host smart-db10a401-3f05-4e7d-875b-df10b776e9fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945344737 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.1945344737
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.2570905082
Short name T803
Test name
Test status
Simulation time 347065302 ps
CPU time 1.47 seconds
Started Jun 13 02:17:12 PM PDT 24
Finished Jun 13 02:17:19 PM PDT 24
Peak memory 201148 kb
Host smart-d5652d5e-1811-4e80-8f68-6005eda57a95
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570905082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.2570905082
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.3025412800
Short name T827
Test name
Test status
Simulation time 496330802 ps
CPU time 0.9 seconds
Started Jun 13 02:17:08 PM PDT 24
Finished Jun 13 02:17:15 PM PDT 24
Peak memory 201152 kb
Host smart-ed8c8d5a-7538-4fa4-ba1a-d76dfc534416
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025412800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.3025412800
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2230643832
Short name T847
Test name
Test status
Simulation time 3803599470 ps
CPU time 12.16 seconds
Started Jun 13 02:17:08 PM PDT 24
Finished Jun 13 02:17:27 PM PDT 24
Peak memory 201336 kb
Host smart-f780832c-6560-4ca7-8cd7-a5f4eef12484
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230643832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.2230643832
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1853509093
Short name T848
Test name
Test status
Simulation time 493125716 ps
CPU time 2.92 seconds
Started Jun 13 02:17:11 PM PDT 24
Finished Jun 13 02:17:19 PM PDT 24
Peak memory 209656 kb
Host smart-bdf53d7b-7d73-447e-a396-d59e89a4615a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853509093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.1853509093
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.253713415
Short name T71
Test name
Test status
Simulation time 8233947885 ps
CPU time 22.31 seconds
Started Jun 13 02:17:10 PM PDT 24
Finished Jun 13 02:17:38 PM PDT 24
Peak memory 201372 kb
Host smart-994fc82c-51c4-46b3-bf56-8ab9ed28285d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253713415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_int
g_err.253713415
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3116290863
Short name T853
Test name
Test status
Simulation time 474707333 ps
CPU time 1.35 seconds
Started Jun 13 02:17:17 PM PDT 24
Finished Jun 13 02:17:23 PM PDT 24
Peak memory 201216 kb
Host smart-4245f13e-3e8c-4e2b-9531-97ee94e24b93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116290863 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.3116290863
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1227051171
Short name T891
Test name
Test status
Simulation time 491421418 ps
CPU time 1.04 seconds
Started Jun 13 02:17:08 PM PDT 24
Finished Jun 13 02:17:15 PM PDT 24
Peak memory 201148 kb
Host smart-a382826b-4540-427a-8689-66045cefa2f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227051171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.1227051171
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.1074099558
Short name T798
Test name
Test status
Simulation time 319046874 ps
CPU time 0.78 seconds
Started Jun 13 02:17:13 PM PDT 24
Finished Jun 13 02:17:19 PM PDT 24
Peak memory 201132 kb
Host smart-126c457c-8b3c-4220-994c-2b0bcdb03c0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074099558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.1074099558
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1720566760
Short name T816
Test name
Test status
Simulation time 4098245436 ps
CPU time 2.57 seconds
Started Jun 13 02:17:17 PM PDT 24
Finished Jun 13 02:17:24 PM PDT 24
Peak memory 201448 kb
Host smart-d4a7d51a-a6d8-4b87-8626-9a3c737c0e72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720566760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.1720566760
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.3403131185
Short name T842
Test name
Test status
Simulation time 425004265 ps
CPU time 1.84 seconds
Started Jun 13 02:17:07 PM PDT 24
Finished Jun 13 02:17:14 PM PDT 24
Peak memory 201476 kb
Host smart-4f6b5180-5dd8-4c83-82a1-606a726809c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403131185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.3403131185
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2473868582
Short name T70
Test name
Test status
Simulation time 4089972705 ps
CPU time 5.84 seconds
Started Jun 13 02:17:10 PM PDT 24
Finished Jun 13 02:17:21 PM PDT 24
Peak memory 201424 kb
Host smart-f06449c4-08a7-47ad-91c7-f20456f63062
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473868582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.2473868582
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.526988254
Short name T807
Test name
Test status
Simulation time 384525121 ps
CPU time 1.81 seconds
Started Jun 13 02:17:15 PM PDT 24
Finished Jun 13 02:17:22 PM PDT 24
Peak memory 201220 kb
Host smart-621e05b1-7ec7-4d1f-9760-c0546e4ec7dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526988254 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.526988254
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1758958317
Short name T864
Test name
Test status
Simulation time 534221184 ps
CPU time 0.84 seconds
Started Jun 13 02:17:16 PM PDT 24
Finished Jun 13 02:17:22 PM PDT 24
Peak memory 201136 kb
Host smart-03617d6c-cdbd-489d-b79a-31d7088bba54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758958317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.1758958317
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3317996090
Short name T886
Test name
Test status
Simulation time 2333005689 ps
CPU time 2.71 seconds
Started Jun 13 02:17:18 PM PDT 24
Finished Jun 13 02:17:25 PM PDT 24
Peak memory 201208 kb
Host smart-0e0f407d-00d7-45ed-b2ee-9631700b7388
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317996090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.3317996090
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.3516014905
Short name T837
Test name
Test status
Simulation time 426677866 ps
CPU time 2.36 seconds
Started Jun 13 02:17:16 PM PDT 24
Finished Jun 13 02:17:23 PM PDT 24
Peak memory 209588 kb
Host smart-7f34ecc4-fc01-4967-90fd-f0c262cadead
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516014905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.3516014905
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1447482308
Short name T907
Test name
Test status
Simulation time 4314089385 ps
CPU time 12.15 seconds
Started Jun 13 02:17:17 PM PDT 24
Finished Jun 13 02:17:34 PM PDT 24
Peak memory 201388 kb
Host smart-c2683e8c-3776-44d1-ad9d-3a56560dcaad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447482308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.1447482308
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.1341262447
Short name T861
Test name
Test status
Simulation time 421672385 ps
CPU time 1.73 seconds
Started Jun 13 02:17:17 PM PDT 24
Finished Jun 13 02:17:24 PM PDT 24
Peak memory 201232 kb
Host smart-ccba568a-82d8-43aa-9a8f-e9ba1b9f11f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341262447 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.1341262447
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3643446176
Short name T914
Test name
Test status
Simulation time 535411908 ps
CPU time 1.13 seconds
Started Jun 13 02:17:17 PM PDT 24
Finished Jun 13 02:17:23 PM PDT 24
Peak memory 201164 kb
Host smart-fe439d8d-7207-408c-a235-d3ea36075b99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643446176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.3643446176
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.2697601794
Short name T801
Test name
Test status
Simulation time 383592844 ps
CPU time 1.09 seconds
Started Jun 13 02:17:21 PM PDT 24
Finished Jun 13 02:17:26 PM PDT 24
Peak memory 201144 kb
Host smart-498b3dc3-5a7a-48aa-91ad-c4186dd0f762
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697601794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.2697601794
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.1472303316
Short name T820
Test name
Test status
Simulation time 4692300743 ps
CPU time 9.3 seconds
Started Jun 13 02:17:18 PM PDT 24
Finished Jun 13 02:17:32 PM PDT 24
Peak memory 201372 kb
Host smart-f4a49608-0886-41e5-a81d-6ae6f1e810b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472303316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.1472303316
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2452670209
Short name T882
Test name
Test status
Simulation time 613954993 ps
CPU time 2.17 seconds
Started Jun 13 02:17:16 PM PDT 24
Finished Jun 13 02:17:23 PM PDT 24
Peak memory 201420 kb
Host smart-e2fde6f5-eec2-496a-9f86-39189fdd81d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452670209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.2452670209
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.4059889610
Short name T872
Test name
Test status
Simulation time 3832052942 ps
CPU time 3.86 seconds
Started Jun 13 02:17:16 PM PDT 24
Finished Jun 13 02:17:25 PM PDT 24
Peak memory 201376 kb
Host smart-5b1b5a9b-a174-4057-bba4-ac181b70e339
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059889610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.4059889610
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.2037020064
Short name T681
Test name
Test status
Simulation time 588274488 ps
CPU time 0.73 seconds
Started Jun 13 02:31:23 PM PDT 24
Finished Jun 13 02:31:28 PM PDT 24
Peak memory 201924 kb
Host smart-a65ec822-1eef-4294-ad23-a9c67ac3ce3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037020064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.2037020064
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.3645183818
Short name T783
Test name
Test status
Simulation time 327898243536 ps
CPU time 412.95 seconds
Started Jun 13 02:31:24 PM PDT 24
Finished Jun 13 02:38:21 PM PDT 24
Peak memory 202212 kb
Host smart-ce2b87df-21da-4dae-a4b5-99e12a66ca1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645183818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.3645183818
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.163527036
Short name T499
Test name
Test status
Simulation time 168317492657 ps
CPU time 205.56 seconds
Started Jun 13 02:31:21 PM PDT 24
Finished Jun 13 02:34:50 PM PDT 24
Peak memory 202172 kb
Host smart-db96c97f-1d4f-4d94-8b3f-b35eef5f959c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163527036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.163527036
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.2212003815
Short name T468
Test name
Test status
Simulation time 335062785637 ps
CPU time 815.39 seconds
Started Jun 13 02:31:24 PM PDT 24
Finished Jun 13 02:45:04 PM PDT 24
Peak memory 202144 kb
Host smart-38f537d3-a5d1-4532-85c1-a79155b7cf90
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212003815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.2212003815
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.1152418135
Short name T398
Test name
Test status
Simulation time 164086390029 ps
CPU time 196.34 seconds
Started Jun 13 02:31:19 PM PDT 24
Finished Jun 13 02:34:38 PM PDT 24
Peak memory 202320 kb
Host smart-16097232-d70f-4513-ad60-81c3440e328b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152418135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.1152418135
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.2248911292
Short name T780
Test name
Test status
Simulation time 161343175320 ps
CPU time 383.8 seconds
Started Jun 13 02:31:27 PM PDT 24
Finished Jun 13 02:37:56 PM PDT 24
Peak memory 202176 kb
Host smart-69fad559-f8e1-4492-a7d0-1e26e36c89b8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248911292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.2248911292
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.972212431
Short name T142
Test name
Test status
Simulation time 534291971290 ps
CPU time 274.12 seconds
Started Jun 13 02:31:20 PM PDT 24
Finished Jun 13 02:35:57 PM PDT 24
Peak memory 202204 kb
Host smart-ab1c353f-37b2-4491-9b8c-def3a3c0a114
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972212431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_w
akeup.972212431
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.3708969717
Short name T536
Test name
Test status
Simulation time 194242916739 ps
CPU time 112.38 seconds
Started Jun 13 02:31:19 PM PDT 24
Finished Jun 13 02:33:14 PM PDT 24
Peak memory 202152 kb
Host smart-022a08dd-8a61-44c9-b5ef-af960180f98c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708969717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.3708969717
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.738452097
Short name T640
Test name
Test status
Simulation time 114734864112 ps
CPU time 369.67 seconds
Started Jun 13 02:31:19 PM PDT 24
Finished Jun 13 02:37:32 PM PDT 24
Peak memory 202508 kb
Host smart-88a8224a-263d-4285-a6ab-05a07042a232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738452097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.738452097
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.282394045
Short name T688
Test name
Test status
Simulation time 22188003233 ps
CPU time 46.78 seconds
Started Jun 13 02:31:23 PM PDT 24
Finished Jun 13 02:32:14 PM PDT 24
Peak memory 202064 kb
Host smart-baabd70a-89fb-4b0d-ac0b-884f70ce0cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282394045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.282394045
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.2006519954
Short name T751
Test name
Test status
Simulation time 3564175719 ps
CPU time 2.54 seconds
Started Jun 13 02:31:44 PM PDT 24
Finished Jun 13 02:31:50 PM PDT 24
Peak memory 202064 kb
Host smart-6e6508ec-03f9-47e3-8fcd-c80b9a2e81f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006519954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.2006519954
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.493911205
Short name T431
Test name
Test status
Simulation time 6154412719 ps
CPU time 4.85 seconds
Started Jun 13 02:31:21 PM PDT 24
Finished Jun 13 02:31:29 PM PDT 24
Peak memory 202064 kb
Host smart-b1b8ed45-3cbf-4f49-92ac-92eb10a81a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493911205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.493911205
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.3181257286
Short name T784
Test name
Test status
Simulation time 40086119607 ps
CPU time 54.1 seconds
Started Jun 13 02:31:45 PM PDT 24
Finished Jun 13 02:32:43 PM PDT 24
Peak memory 210872 kb
Host smart-af15278a-c363-42dc-bf36-e72f68ff80d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181257286 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.3181257286
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.224795191
Short name T544
Test name
Test status
Simulation time 360245426 ps
CPU time 1.38 seconds
Started Jun 13 02:31:23 PM PDT 24
Finished Jun 13 02:31:30 PM PDT 24
Peak memory 201864 kb
Host smart-4c25c569-97ba-4594-ab1c-5a2b26131877
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224795191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.224795191
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.1129110828
Short name T193
Test name
Test status
Simulation time 198000001670 ps
CPU time 104.17 seconds
Started Jun 13 02:31:46 PM PDT 24
Finished Jun 13 02:33:34 PM PDT 24
Peak memory 202296 kb
Host smart-acc078f8-1a5a-41d4-9709-9583d8a4b57e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129110828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.1129110828
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.2341799128
Short name T752
Test name
Test status
Simulation time 173509251293 ps
CPU time 407.22 seconds
Started Jun 13 02:31:21 PM PDT 24
Finished Jun 13 02:38:12 PM PDT 24
Peak memory 202260 kb
Host smart-7dbdfa0c-2b8b-4ba0-8b9f-7fc1c114dd08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341799128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.2341799128
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.1692858868
Short name T299
Test name
Test status
Simulation time 169921952569 ps
CPU time 193.46 seconds
Started Jun 13 02:31:22 PM PDT 24
Finished Jun 13 02:34:39 PM PDT 24
Peak memory 202188 kb
Host smart-07e2033d-db12-4c58-9214-e1896edd5f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692858868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.1692858868
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.2051276971
Short name T634
Test name
Test status
Simulation time 338244173259 ps
CPU time 649.47 seconds
Started Jun 13 02:31:19 PM PDT 24
Finished Jun 13 02:42:11 PM PDT 24
Peak memory 202180 kb
Host smart-55d315e6-ad67-4e43-b57d-d814eb92b046
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051276971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.2051276971
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.3668765238
Short name T6
Test name
Test status
Simulation time 163217902692 ps
CPU time 88.97 seconds
Started Jun 13 02:31:21 PM PDT 24
Finished Jun 13 02:32:54 PM PDT 24
Peak memory 202296 kb
Host smart-9e558803-adc4-49e1-a48c-b16a9b1396df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668765238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.3668765238
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.1667808448
Short name T720
Test name
Test status
Simulation time 161796612426 ps
CPU time 321.39 seconds
Started Jun 13 02:31:27 PM PDT 24
Finished Jun 13 02:36:53 PM PDT 24
Peak memory 202188 kb
Host smart-ab6588f4-d623-461f-8f41-a01b22e7c3a0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667808448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.1667808448
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.2628432144
Short name T683
Test name
Test status
Simulation time 529506594874 ps
CPU time 1260.24 seconds
Started Jun 13 02:31:20 PM PDT 24
Finished Jun 13 02:52:23 PM PDT 24
Peak memory 202232 kb
Host smart-0477f7a5-e765-4632-81c4-572659ae2d2a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628432144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.2628432144
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.1919733931
Short name T661
Test name
Test status
Simulation time 203475053980 ps
CPU time 123.65 seconds
Started Jun 13 02:31:22 PM PDT 24
Finished Jun 13 02:33:30 PM PDT 24
Peak memory 202264 kb
Host smart-9797668c-3d95-464d-a001-86f38c807111
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919733931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.1919733931
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.1639316695
Short name T326
Test name
Test status
Simulation time 110786340831 ps
CPU time 539.21 seconds
Started Jun 13 02:31:39 PM PDT 24
Finished Jun 13 02:40:43 PM PDT 24
Peak memory 202596 kb
Host smart-24043beb-5c81-40c2-8e83-586851cb395b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639316695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.1639316695
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.3915025212
Short name T391
Test name
Test status
Simulation time 43198507156 ps
CPU time 26.32 seconds
Started Jun 13 02:31:35 PM PDT 24
Finished Jun 13 02:32:07 PM PDT 24
Peak memory 202040 kb
Host smart-c6550fb4-bc9c-4023-95fa-7121a734b4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915025212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.3915025212
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.2478761304
Short name T521
Test name
Test status
Simulation time 4629547114 ps
CPU time 2.16 seconds
Started Jun 13 02:31:20 PM PDT 24
Finished Jun 13 02:31:24 PM PDT 24
Peak memory 202052 kb
Host smart-e2b10364-1a1f-4d5c-9345-650bdec199f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478761304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.2478761304
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.4070899880
Short name T62
Test name
Test status
Simulation time 3829148659 ps
CPU time 9.9 seconds
Started Jun 13 02:31:38 PM PDT 24
Finished Jun 13 02:31:53 PM PDT 24
Peak memory 217676 kb
Host smart-5b50beb1-2722-4c4c-9bc6-cf8171b9883e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070899880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.4070899880
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.2177353512
Short name T696
Test name
Test status
Simulation time 5853508748 ps
CPU time 2.42 seconds
Started Jun 13 02:31:22 PM PDT 24
Finished Jun 13 02:31:28 PM PDT 24
Peak memory 202020 kb
Host smart-be6fb1a5-2096-4bc6-93a6-3f88eed95128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177353512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.2177353512
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.1120902016
Short name T479
Test name
Test status
Simulation time 170007367735 ps
CPU time 312.87 seconds
Started Jun 13 02:31:23 PM PDT 24
Finished Jun 13 02:36:40 PM PDT 24
Peak memory 210896 kb
Host smart-00005811-5e98-4973-a5fb-03ed2b1b19b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120902016 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.1120902016
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.948365698
Short name T526
Test name
Test status
Simulation time 540597917 ps
CPU time 0.98 seconds
Started Jun 13 02:31:43 PM PDT 24
Finished Jun 13 02:31:48 PM PDT 24
Peak memory 201912 kb
Host smart-8db532ce-4611-459e-ba7a-d0ff3da4d119
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948365698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.948365698
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.3730560422
Short name T203
Test name
Test status
Simulation time 165088256742 ps
CPU time 62.56 seconds
Started Jun 13 02:31:53 PM PDT 24
Finished Jun 13 02:33:00 PM PDT 24
Peak memory 202216 kb
Host smart-e2b2b417-dc01-4537-bac1-a89816c29043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730560422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.3730560422
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.48538425
Short name T467
Test name
Test status
Simulation time 329946145610 ps
CPU time 197.91 seconds
Started Jun 13 02:31:52 PM PDT 24
Finished Jun 13 02:35:14 PM PDT 24
Peak memory 202132 kb
Host smart-5bf46544-9725-4ef2-a6cc-05c5de218573
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=48538425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt
_fixed.48538425
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.3011647014
Short name T690
Test name
Test status
Simulation time 167018753306 ps
CPU time 65.3 seconds
Started Jun 13 02:31:51 PM PDT 24
Finished Jun 13 02:33:01 PM PDT 24
Peak memory 202224 kb
Host smart-54213d08-ae4a-47d4-b4c3-f48c3ed8dd90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011647014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.3011647014
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.102291747
Short name T715
Test name
Test status
Simulation time 329518346892 ps
CPU time 370.6 seconds
Started Jun 13 02:31:53 PM PDT 24
Finished Jun 13 02:38:08 PM PDT 24
Peak memory 202084 kb
Host smart-39daf448-dea1-443d-b9c2-e636d18f9020
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=102291747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fixe
d.102291747
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.222542056
Short name T161
Test name
Test status
Simulation time 561840318494 ps
CPU time 357.24 seconds
Started Jun 13 02:31:49 PM PDT 24
Finished Jun 13 02:37:51 PM PDT 24
Peak memory 202288 kb
Host smart-3069b888-f22e-460a-8e80-fa5538c4bf4a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222542056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_
wakeup.222542056
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.1164146524
Short name T387
Test name
Test status
Simulation time 405663091255 ps
CPU time 890.43 seconds
Started Jun 13 02:31:53 PM PDT 24
Finished Jun 13 02:46:48 PM PDT 24
Peak memory 202200 kb
Host smart-99af5835-7b6d-41bf-beac-dcbdd5f18f29
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164146524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.1164146524
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.2898084029
Short name T330
Test name
Test status
Simulation time 34532685395 ps
CPU time 20.56 seconds
Started Jun 13 02:31:48 PM PDT 24
Finished Jun 13 02:32:12 PM PDT 24
Peak memory 201992 kb
Host smart-907bff79-dfd6-46f7-b352-401baf8e8151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898084029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.2898084029
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.815659621
Short name T646
Test name
Test status
Simulation time 4955105393 ps
CPU time 11.51 seconds
Started Jun 13 02:31:52 PM PDT 24
Finished Jun 13 02:32:08 PM PDT 24
Peak memory 202048 kb
Host smart-c20189f6-0bc9-4e9b-bfaf-f737107ba2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815659621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.815659621
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.2423114842
Short name T776
Test name
Test status
Simulation time 5774916250 ps
CPU time 6.35 seconds
Started Jun 13 02:32:00 PM PDT 24
Finished Jun 13 02:32:11 PM PDT 24
Peak memory 202044 kb
Host smart-393f597c-7352-456a-a175-7be64eaf044d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423114842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.2423114842
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.119474707
Short name T607
Test name
Test status
Simulation time 38307457714 ps
CPU time 21.66 seconds
Started Jun 13 02:31:54 PM PDT 24
Finished Jun 13 02:32:20 PM PDT 24
Peak memory 201996 kb
Host smart-a684b2e8-3ef8-4bff-8fb0-9ca955e4d466
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119474707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all.
119474707
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.1189174814
Short name T531
Test name
Test status
Simulation time 195206763493 ps
CPU time 391.14 seconds
Started Jun 13 02:31:51 PM PDT 24
Finished Jun 13 02:38:26 PM PDT 24
Peak memory 218556 kb
Host smart-db0ffa7a-af1c-405e-81be-55e4a0c0a099
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189174814 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.1189174814
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.1086037726
Short name T484
Test name
Test status
Simulation time 296521863 ps
CPU time 1.35 seconds
Started Jun 13 02:31:49 PM PDT 24
Finished Jun 13 02:31:53 PM PDT 24
Peak memory 201868 kb
Host smart-e0baf1cb-5c1a-446d-a74b-68c728daf6e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086037726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.1086037726
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.1139921595
Short name T237
Test name
Test status
Simulation time 162171923374 ps
CPU time 111.25 seconds
Started Jun 13 02:31:50 PM PDT 24
Finished Jun 13 02:33:45 PM PDT 24
Peak memory 202244 kb
Host smart-1b39bc1f-b8cb-44cc-8e22-d80fa38e1c8c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139921595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.1139921595
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.1608095147
Short name T733
Test name
Test status
Simulation time 160621889535 ps
CPU time 60.6 seconds
Started Jun 13 02:31:51 PM PDT 24
Finished Jun 13 02:32:56 PM PDT 24
Peak memory 202212 kb
Host smart-1c9c2c2b-49cd-4eee-98b0-71b52b5b8053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608095147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.1608095147
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.4106661520
Short name T548
Test name
Test status
Simulation time 495094677556 ps
CPU time 305.2 seconds
Started Jun 13 02:31:54 PM PDT 24
Finished Jun 13 02:37:04 PM PDT 24
Peak memory 202176 kb
Host smart-195160db-2671-416c-a4be-04cf43d69e0e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106661520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.4106661520
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.483831302
Short name T209
Test name
Test status
Simulation time 500494859438 ps
CPU time 190.49 seconds
Started Jun 13 02:31:43 PM PDT 24
Finished Jun 13 02:34:58 PM PDT 24
Peak memory 202208 kb
Host smart-0a332de4-7ee1-4ff0-ac8c-64dd7889eaac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483831302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.483831302
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.2132043802
Short name T729
Test name
Test status
Simulation time 328911131205 ps
CPU time 728.06 seconds
Started Jun 13 02:31:44 PM PDT 24
Finished Jun 13 02:43:56 PM PDT 24
Peak memory 202164 kb
Host smart-48419282-74cf-4408-ad10-0834ba2352b4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132043802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.2132043802
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.3424160152
Short name T225
Test name
Test status
Simulation time 180631847583 ps
CPU time 106.31 seconds
Started Jun 13 02:31:52 PM PDT 24
Finished Jun 13 02:33:42 PM PDT 24
Peak memory 202188 kb
Host smart-dcfa99fe-8678-4cb1-9c77-cc2feb9400df
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424160152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.3424160152
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.3563981850
Short name T459
Test name
Test status
Simulation time 118741712176 ps
CPU time 537.35 seconds
Started Jun 13 02:31:52 PM PDT 24
Finished Jun 13 02:40:54 PM PDT 24
Peak memory 202592 kb
Host smart-eaf0636e-5672-43f1-b943-0f92ea7f99ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563981850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.3563981850
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.1678799100
Short name T406
Test name
Test status
Simulation time 27681823748 ps
CPU time 61.24 seconds
Started Jun 13 02:31:56 PM PDT 24
Finished Jun 13 02:33:01 PM PDT 24
Peak memory 202040 kb
Host smart-12dc8477-ad9e-4c16-91b6-ec1c23fb0880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678799100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.1678799100
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.1302060064
Short name T790
Test name
Test status
Simulation time 4969788869 ps
CPU time 12.87 seconds
Started Jun 13 02:31:54 PM PDT 24
Finished Jun 13 02:32:12 PM PDT 24
Peak memory 202044 kb
Host smart-a2b9e356-ddb9-41e5-8c04-7685993c4b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302060064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.1302060064
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.192360921
Short name T747
Test name
Test status
Simulation time 5967793538 ps
CPU time 9.95 seconds
Started Jun 13 02:31:47 PM PDT 24
Finished Jun 13 02:32:00 PM PDT 24
Peak memory 202056 kb
Host smart-10318398-c067-4465-8447-6eab285c2950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192360921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.192360921
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.1906906197
Short name T186
Test name
Test status
Simulation time 108501345199 ps
CPU time 63.41 seconds
Started Jun 13 02:31:54 PM PDT 24
Finished Jun 13 02:33:02 PM PDT 24
Peak memory 210904 kb
Host smart-6f543a5f-8e74-4d3f-a22d-afe4e6f5b8d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906906197 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.1906906197
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.1537538263
Short name T740
Test name
Test status
Simulation time 326472934 ps
CPU time 1.09 seconds
Started Jun 13 02:32:01 PM PDT 24
Finished Jun 13 02:32:07 PM PDT 24
Peak memory 201908 kb
Host smart-fb45f5b5-73e9-40ba-bbbc-2130a9b09686
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537538263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.1537538263
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.4108244042
Short name T212
Test name
Test status
Simulation time 358637583765 ps
CPU time 550.27 seconds
Started Jun 13 02:31:51 PM PDT 24
Finished Jun 13 02:41:06 PM PDT 24
Peak memory 202220 kb
Host smart-029a1188-55b8-4f10-89da-8f2200412341
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108244042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.4108244042
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.3925343448
Short name T163
Test name
Test status
Simulation time 175931221173 ps
CPU time 423.47 seconds
Started Jun 13 02:31:56 PM PDT 24
Finished Jun 13 02:39:04 PM PDT 24
Peak memory 202176 kb
Host smart-6f34a4e2-3f0b-4dd7-83a9-d54fc55fd690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925343448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.3925343448
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.3011172146
Short name T304
Test name
Test status
Simulation time 329095662255 ps
CPU time 167.02 seconds
Started Jun 13 02:31:54 PM PDT 24
Finished Jun 13 02:34:45 PM PDT 24
Peak memory 202268 kb
Host smart-0ba149bd-34af-4ee7-92e5-06e1c2193197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011172146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.3011172146
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.4172769945
Short name T451
Test name
Test status
Simulation time 335891603873 ps
CPU time 188.16 seconds
Started Jun 13 02:31:55 PM PDT 24
Finished Jun 13 02:35:08 PM PDT 24
Peak memory 202156 kb
Host smart-dec606e2-95ab-4d17-89a9-38abdf49e596
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172769945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.4172769945
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.1456473854
Short name T772
Test name
Test status
Simulation time 491714917820 ps
CPU time 528.21 seconds
Started Jun 13 02:31:51 PM PDT 24
Finished Jun 13 02:40:44 PM PDT 24
Peak memory 202300 kb
Host smart-13edb8cd-8cf2-4181-86d8-fb9c5f239d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456473854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.1456473854
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.2615645894
Short name T618
Test name
Test status
Simulation time 161760071532 ps
CPU time 387.47 seconds
Started Jun 13 02:31:49 PM PDT 24
Finished Jun 13 02:38:21 PM PDT 24
Peak memory 202252 kb
Host smart-3ac68516-2bca-45b4-a8f6-34b64ac4f5be
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615645894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.2615645894
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.377922305
Short name T370
Test name
Test status
Simulation time 601531966547 ps
CPU time 321.23 seconds
Started Jun 13 02:31:52 PM PDT 24
Finished Jun 13 02:37:17 PM PDT 24
Peak memory 202200 kb
Host smart-dba8f142-6a67-492c-aee5-b2db9f5e2a26
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377922305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
adc_ctrl_filters_wakeup_fixed.377922305
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.3864075232
Short name T735
Test name
Test status
Simulation time 75520899227 ps
CPU time 341.82 seconds
Started Jun 13 02:31:58 PM PDT 24
Finished Jun 13 02:37:44 PM PDT 24
Peak memory 202548 kb
Host smart-2f6b229a-fcfd-44ed-b5d7-15632ba13745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864075232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.3864075232
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.113232174
Short name T27
Test name
Test status
Simulation time 27208057108 ps
CPU time 11.97 seconds
Started Jun 13 02:32:00 PM PDT 24
Finished Jun 13 02:32:17 PM PDT 24
Peak memory 202052 kb
Host smart-18c5781d-e17f-4f94-95d9-61e08104bd30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113232174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.113232174
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.3982996218
Short name T396
Test name
Test status
Simulation time 3542893564 ps
CPU time 3.8 seconds
Started Jun 13 02:31:54 PM PDT 24
Finished Jun 13 02:32:03 PM PDT 24
Peak memory 202052 kb
Host smart-1c2e2b24-d313-48ea-9b87-5a8e37d4c656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982996218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.3982996218
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.3038710424
Short name T557
Test name
Test status
Simulation time 5983953045 ps
CPU time 13.4 seconds
Started Jun 13 02:31:56 PM PDT 24
Finished Jun 13 02:32:13 PM PDT 24
Peak memory 202024 kb
Host smart-fdf3574d-5d2d-4dfd-bbe9-c45c7d80bf56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038710424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.3038710424
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.2297229475
Short name T136
Test name
Test status
Simulation time 430551062921 ps
CPU time 1114.3 seconds
Started Jun 13 02:31:51 PM PDT 24
Finished Jun 13 02:50:30 PM PDT 24
Peak memory 210788 kb
Host smart-b4bdb228-6897-4006-8c23-6948d6f5e06e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297229475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.2297229475
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.2189708873
Short name T34
Test name
Test status
Simulation time 3263278462 ps
CPU time 8.44 seconds
Started Jun 13 02:31:54 PM PDT 24
Finished Jun 13 02:32:06 PM PDT 24
Peak memory 202164 kb
Host smart-6078401a-bf45-4c4f-803c-b46f4b20cca1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189708873 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.2189708873
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.4196525582
Short name T117
Test name
Test status
Simulation time 513436647878 ps
CPU time 657.36 seconds
Started Jun 13 02:31:51 PM PDT 24
Finished Jun 13 02:42:53 PM PDT 24
Peak memory 202216 kb
Host smart-94dcf31a-b7be-4d84-b7df-28dfda029b92
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196525582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.4196525582
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.1748462663
Short name T239
Test name
Test status
Simulation time 165436490202 ps
CPU time 118.67 seconds
Started Jun 13 02:31:58 PM PDT 24
Finished Jun 13 02:34:01 PM PDT 24
Peak memory 202224 kb
Host smart-3df7b869-fe3d-44e4-8daa-19216efc4125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748462663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.1748462663
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.1810170303
Short name T621
Test name
Test status
Simulation time 328271111909 ps
CPU time 683.67 seconds
Started Jun 13 02:31:50 PM PDT 24
Finished Jun 13 02:43:17 PM PDT 24
Peak memory 202224 kb
Host smart-aa02247a-8af0-4c1c-984d-4e48067ae007
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810170303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.1810170303
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.2304005516
Short name T568
Test name
Test status
Simulation time 493760061544 ps
CPU time 1108.32 seconds
Started Jun 13 02:31:51 PM PDT 24
Finished Jun 13 02:50:24 PM PDT 24
Peak memory 202216 kb
Host smart-c5565ddd-7589-48c1-829d-e3b286e6f442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304005516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.2304005516
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.2510743390
Short name T554
Test name
Test status
Simulation time 163909051385 ps
CPU time 184.08 seconds
Started Jun 13 02:31:56 PM PDT 24
Finished Jun 13 02:35:05 PM PDT 24
Peak memory 202200 kb
Host smart-7db4e1e3-35e0-482f-b5fe-9b5c835aa97e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510743390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.2510743390
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.1956107830
Short name T609
Test name
Test status
Simulation time 171571598605 ps
CPU time 422.53 seconds
Started Jun 13 02:31:57 PM PDT 24
Finished Jun 13 02:39:04 PM PDT 24
Peak memory 202264 kb
Host smart-b844fc33-7d93-46a0-809d-464b5885f11e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956107830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.1956107830
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.3549076704
Short name T487
Test name
Test status
Simulation time 204393109942 ps
CPU time 357.62 seconds
Started Jun 13 02:31:59 PM PDT 24
Finished Jun 13 02:38:02 PM PDT 24
Peak memory 202208 kb
Host smart-e0ad2247-e082-44d4-806b-37090dca5736
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549076704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.3549076704
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.2044460196
Short name T713
Test name
Test status
Simulation time 65590240400 ps
CPU time 248.65 seconds
Started Jun 13 02:31:55 PM PDT 24
Finished Jun 13 02:36:08 PM PDT 24
Peak memory 202612 kb
Host smart-b8e0dae9-4fb3-4542-9134-345ffbb43eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044460196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.2044460196
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.1092981949
Short name T465
Test name
Test status
Simulation time 24953552543 ps
CPU time 54.59 seconds
Started Jun 13 02:31:55 PM PDT 24
Finished Jun 13 02:32:54 PM PDT 24
Peak memory 202008 kb
Host smart-d516a49c-2bf0-4afe-890a-0bbb0e30ce2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092981949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.1092981949
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.3266069488
Short name T542
Test name
Test status
Simulation time 3200896953 ps
CPU time 2.66 seconds
Started Jun 13 02:33:11 PM PDT 24
Finished Jun 13 02:33:15 PM PDT 24
Peak memory 201960 kb
Host smart-d90e2c92-98a3-4777-93fa-791846a23b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266069488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.3266069488
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.2055839554
Short name T687
Test name
Test status
Simulation time 5953685799 ps
CPU time 3.84 seconds
Started Jun 13 02:31:58 PM PDT 24
Finished Jun 13 02:32:06 PM PDT 24
Peak memory 202024 kb
Host smart-f39b9402-bbdd-4939-b35b-399e23f5c1f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055839554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.2055839554
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.2057526184
Short name T191
Test name
Test status
Simulation time 173802545449 ps
CPU time 390.29 seconds
Started Jun 13 02:31:55 PM PDT 24
Finished Jun 13 02:38:29 PM PDT 24
Peak memory 202176 kb
Host smart-e6d2f45f-38f9-4342-807c-7cc595f4fd69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057526184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.2057526184
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.3292596947
Short name T196
Test name
Test status
Simulation time 86571338088 ps
CPU time 164.44 seconds
Started Jun 13 02:31:56 PM PDT 24
Finished Jun 13 02:34:44 PM PDT 24
Peak memory 210892 kb
Host smart-1bdd61a8-4166-4865-bc3e-ea01a90c8e1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292596947 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.3292596947
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.115907917
Short name T760
Test name
Test status
Simulation time 359145798 ps
CPU time 0.75 seconds
Started Jun 13 02:31:51 PM PDT 24
Finished Jun 13 02:31:56 PM PDT 24
Peak memory 201888 kb
Host smart-54fb316f-f558-40dc-89eb-ef9068ce5563
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115907917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.115907917
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.2465806168
Short name T135
Test name
Test status
Simulation time 340517613217 ps
CPU time 431.78 seconds
Started Jun 13 02:32:02 PM PDT 24
Finished Jun 13 02:39:19 PM PDT 24
Peak memory 202212 kb
Host smart-6bba2b8a-0dbf-4805-b257-28f727df6c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465806168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.2465806168
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.1295658018
Short name T571
Test name
Test status
Simulation time 160845453590 ps
CPU time 194.28 seconds
Started Jun 13 02:32:12 PM PDT 24
Finished Jun 13 02:35:34 PM PDT 24
Peak memory 202172 kb
Host smart-fac6c10f-3dac-418e-b8b2-bfae382c2b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295658018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.1295658018
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.1776074913
Short name T516
Test name
Test status
Simulation time 493282173341 ps
CPU time 562.49 seconds
Started Jun 13 02:32:01 PM PDT 24
Finished Jun 13 02:41:29 PM PDT 24
Peak memory 202288 kb
Host smart-96d9d2bb-2cbd-42e2-95e9-107e48850320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776074913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.1776074913
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.2939565425
Short name T641
Test name
Test status
Simulation time 495937449008 ps
CPU time 526.04 seconds
Started Jun 13 02:32:13 PM PDT 24
Finished Jun 13 02:41:07 PM PDT 24
Peak memory 202152 kb
Host smart-7fe28c94-b1eb-4bd1-8514-d53f725ccb6a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939565425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.2939565425
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.1751838959
Short name T498
Test name
Test status
Simulation time 205449802792 ps
CPU time 487.08 seconds
Started Jun 13 02:31:56 PM PDT 24
Finished Jun 13 02:40:07 PM PDT 24
Peak memory 202168 kb
Host smart-eb5e6976-c728-44c4-be75-95a54411e6d6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751838959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.1751838959
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.449915401
Short name T582
Test name
Test status
Simulation time 149716465857 ps
CPU time 453.34 seconds
Started Jun 13 02:31:59 PM PDT 24
Finished Jun 13 02:39:38 PM PDT 24
Peak memory 202600 kb
Host smart-f104aad9-31b5-4a29-9676-d9002db54a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449915401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.449915401
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.1150271398
Short name T616
Test name
Test status
Simulation time 35715253622 ps
CPU time 7.17 seconds
Started Jun 13 02:31:59 PM PDT 24
Finished Jun 13 02:32:11 PM PDT 24
Peak memory 202008 kb
Host smart-2d5814d0-2155-43be-b985-1c87d00167fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150271398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.1150271398
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.410148506
Short name T691
Test name
Test status
Simulation time 4232445209 ps
CPU time 11 seconds
Started Jun 13 02:32:02 PM PDT 24
Finished Jun 13 02:32:18 PM PDT 24
Peak memory 202036 kb
Host smart-fd2ee987-2a84-46db-a822-dd261752c7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410148506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.410148506
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.159249045
Short name T676
Test name
Test status
Simulation time 6117447799 ps
CPU time 4.21 seconds
Started Jun 13 02:31:54 PM PDT 24
Finished Jun 13 02:32:03 PM PDT 24
Peak memory 202016 kb
Host smart-c48ca65c-00ce-4870-a20e-e85978c04510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159249045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.159249045
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.2622817631
Short name T368
Test name
Test status
Simulation time 93953100602 ps
CPU time 293.21 seconds
Started Jun 13 02:32:03 PM PDT 24
Finished Jun 13 02:37:02 PM PDT 24
Peak memory 202548 kb
Host smart-6242dda4-325e-401e-a56b-11d16f240cf4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622817631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.2622817631
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.1430634970
Short name T220
Test name
Test status
Simulation time 88267018643 ps
CPU time 97.14 seconds
Started Jun 13 02:31:56 PM PDT 24
Finished Jun 13 02:33:37 PM PDT 24
Peak memory 210600 kb
Host smart-aa77de92-cef1-4705-8823-9e9174d3aad5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430634970 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.1430634970
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.2171834700
Short name T697
Test name
Test status
Simulation time 378375500 ps
CPU time 0.75 seconds
Started Jun 13 02:31:58 PM PDT 24
Finished Jun 13 02:32:03 PM PDT 24
Peak memory 201816 kb
Host smart-d706c40e-14d6-4b5c-b5b4-d9a0199df09d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171834700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.2171834700
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.2241465325
Short name T323
Test name
Test status
Simulation time 502763338276 ps
CPU time 287.55 seconds
Started Jun 13 02:31:58 PM PDT 24
Finished Jun 13 02:36:49 PM PDT 24
Peak memory 202304 kb
Host smart-c241fdd0-7cc4-4f8f-aa08-6b16faa631e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241465325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.2241465325
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.422772543
Short name T768
Test name
Test status
Simulation time 483781872127 ps
CPU time 123.89 seconds
Started Jun 13 02:31:55 PM PDT 24
Finished Jun 13 02:34:03 PM PDT 24
Peak memory 202180 kb
Host smart-f8b93a00-e5b7-4c25-a1a5-dae81581b19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422772543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.422772543
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.3746440039
Short name T545
Test name
Test status
Simulation time 492223593903 ps
CPU time 285.31 seconds
Started Jun 13 02:32:04 PM PDT 24
Finished Jun 13 02:36:55 PM PDT 24
Peak memory 202236 kb
Host smart-d076d1f6-2308-4778-85be-a19e1937510d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746440039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.3746440039
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.4222367648
Short name T320
Test name
Test status
Simulation time 165438168829 ps
CPU time 355.29 seconds
Started Jun 13 02:32:03 PM PDT 24
Finished Jun 13 02:38:04 PM PDT 24
Peak memory 202464 kb
Host smart-beb00c3e-d936-44dd-b3eb-979dfe5347c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222367648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.4222367648
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.1413265836
Short name T774
Test name
Test status
Simulation time 171740006668 ps
CPU time 98.34 seconds
Started Jun 13 02:32:01 PM PDT 24
Finished Jun 13 02:33:45 PM PDT 24
Peak memory 202208 kb
Host smart-e7b580c0-d8e0-479d-90ad-f7962a3a642b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413265836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.1413265836
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.1140459255
Short name T285
Test name
Test status
Simulation time 186226386362 ps
CPU time 218.15 seconds
Started Jun 13 02:32:04 PM PDT 24
Finished Jun 13 02:35:48 PM PDT 24
Peak memory 202252 kb
Host smart-030b8fbc-c28a-4e6a-915d-f793b36e246d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140459255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.1140459255
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.1293525471
Short name T366
Test name
Test status
Simulation time 198868480685 ps
CPU time 111.29 seconds
Started Jun 13 02:32:11 PM PDT 24
Finished Jun 13 02:34:09 PM PDT 24
Peak memory 202140 kb
Host smart-86345f87-4aa3-4ae2-aaae-e35f94ee5640
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293525471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.1293525471
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.1190467286
Short name T471
Test name
Test status
Simulation time 125390638124 ps
CPU time 434.73 seconds
Started Jun 13 02:32:03 PM PDT 24
Finished Jun 13 02:39:23 PM PDT 24
Peak memory 202616 kb
Host smart-3f0d773a-4c33-4053-b820-dc40aad15232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190467286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.1190467286
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.3717359700
Short name T338
Test name
Test status
Simulation time 41736817116 ps
CPU time 94.47 seconds
Started Jun 13 02:32:08 PM PDT 24
Finished Jun 13 02:33:49 PM PDT 24
Peak memory 202028 kb
Host smart-d072a121-eef8-49b9-989b-18c202df7f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717359700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.3717359700
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.3540951643
Short name T781
Test name
Test status
Simulation time 4041860459 ps
CPU time 5.57 seconds
Started Jun 13 02:32:02 PM PDT 24
Finished Jun 13 02:32:13 PM PDT 24
Peak memory 202024 kb
Host smart-efca9a99-4751-422b-992e-eee7f02a8bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540951643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.3540951643
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.1102309310
Short name T416
Test name
Test status
Simulation time 5735911220 ps
CPU time 2.32 seconds
Started Jun 13 02:32:02 PM PDT 24
Finished Jun 13 02:32:10 PM PDT 24
Peak memory 202048 kb
Host smart-65c47245-0821-4042-bf80-3ed754aa3fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102309310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.1102309310
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.423939209
Short name T717
Test name
Test status
Simulation time 196072384321 ps
CPU time 105.4 seconds
Started Jun 13 02:32:05 PM PDT 24
Finished Jun 13 02:33:56 PM PDT 24
Peak memory 202184 kb
Host smart-911989ac-a108-4def-b60f-5f7b7fbeab74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423939209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all.
423939209
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.1316824248
Short name T23
Test name
Test status
Simulation time 1156402969698 ps
CPU time 199.64 seconds
Started Jun 13 02:32:09 PM PDT 24
Finished Jun 13 02:35:35 PM PDT 24
Peak memory 210928 kb
Host smart-e83c1be5-0681-443e-8a85-b235bc736d99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316824248 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.1316824248
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.2210336806
Short name T550
Test name
Test status
Simulation time 293763994 ps
CPU time 1.28 seconds
Started Jun 13 02:32:09 PM PDT 24
Finished Jun 13 02:32:17 PM PDT 24
Peak memory 201640 kb
Host smart-3f77fb9b-4622-4fd1-b07c-362e99428e7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210336806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.2210336806
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.85399780
Short name T197
Test name
Test status
Simulation time 160255537259 ps
CPU time 172.92 seconds
Started Jun 13 02:32:03 PM PDT 24
Finished Jun 13 02:35:01 PM PDT 24
Peak memory 202244 kb
Host smart-de8f88ec-2e6f-487a-ae83-0d212a40414b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85399780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gatin
g.85399780
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.123748102
Short name T114
Test name
Test status
Simulation time 356542132572 ps
CPU time 783.21 seconds
Started Jun 13 02:31:59 PM PDT 24
Finished Jun 13 02:45:07 PM PDT 24
Peak memory 202320 kb
Host smart-34601f28-faf9-4999-8e28-f1df2c2ca4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123748102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.123748102
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.1108511865
Short name T231
Test name
Test status
Simulation time 165364374369 ps
CPU time 74.55 seconds
Started Jun 13 02:31:59 PM PDT 24
Finished Jun 13 02:33:19 PM PDT 24
Peak memory 202216 kb
Host smart-f817d212-d81c-4b35-b209-a367624bbb18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108511865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.1108511865
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.3391138102
Short name T707
Test name
Test status
Simulation time 498016692167 ps
CPU time 626.26 seconds
Started Jun 13 02:32:01 PM PDT 24
Finished Jun 13 02:42:32 PM PDT 24
Peak memory 202200 kb
Host smart-ebf60248-7fbe-4fb7-8560-cf5b0dc81fa3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391138102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.3391138102
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.574865337
Short name T311
Test name
Test status
Simulation time 166519619266 ps
CPU time 60.55 seconds
Started Jun 13 02:32:00 PM PDT 24
Finished Jun 13 02:33:05 PM PDT 24
Peak memory 202208 kb
Host smart-973d8683-215e-46b8-82e2-20ab80e3caa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574865337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.574865337
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.1966387021
Short name T546
Test name
Test status
Simulation time 326738098275 ps
CPU time 619.2 seconds
Started Jun 13 02:32:11 PM PDT 24
Finished Jun 13 02:42:38 PM PDT 24
Peak memory 202128 kb
Host smart-722814ce-7a1f-4134-b036-4ab0e100bde2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966387021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.1966387021
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.2568682888
Short name T611
Test name
Test status
Simulation time 505502736668 ps
CPU time 297.35 seconds
Started Jun 13 02:31:55 PM PDT 24
Finished Jun 13 02:36:57 PM PDT 24
Peak memory 202172 kb
Host smart-197171c8-fb4b-4194-92d7-82a6825d56e4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568682888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.2568682888
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.145996327
Short name T342
Test name
Test status
Simulation time 195389712919 ps
CPU time 424.37 seconds
Started Jun 13 02:31:59 PM PDT 24
Finished Jun 13 02:39:09 PM PDT 24
Peak memory 202248 kb
Host smart-633e7b51-c2f8-4162-8284-a231f0fbf368
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145996327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
adc_ctrl_filters_wakeup_fixed.145996327
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.3633825881
Short name T518
Test name
Test status
Simulation time 101492042134 ps
CPU time 306.82 seconds
Started Jun 13 02:32:03 PM PDT 24
Finished Jun 13 02:37:15 PM PDT 24
Peak memory 202616 kb
Host smart-2ad18233-49d9-47d4-9eb7-ed713d3ad4ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633825881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.3633825881
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.2936411998
Short name T332
Test name
Test status
Simulation time 24804719053 ps
CPU time 54.01 seconds
Started Jun 13 02:32:00 PM PDT 24
Finished Jun 13 02:32:59 PM PDT 24
Peak memory 201996 kb
Host smart-7c5eb367-4ce2-42e6-821d-2a92eceedb8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936411998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.2936411998
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.1653593928
Short name T723
Test name
Test status
Simulation time 4169625024 ps
CPU time 2.22 seconds
Started Jun 13 02:31:51 PM PDT 24
Finished Jun 13 02:31:58 PM PDT 24
Peak memory 202076 kb
Host smart-8ff606ab-b936-44de-81d4-4d45284e2ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653593928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.1653593928
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.3509950073
Short name T543
Test name
Test status
Simulation time 5749248719 ps
CPU time 3.93 seconds
Started Jun 13 02:32:09 PM PDT 24
Finished Jun 13 02:32:20 PM PDT 24
Peak memory 201956 kb
Host smart-d3b6cb85-d617-401f-84f8-1aaf2e6dd78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509950073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.3509950073
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.2488667682
Short name T564
Test name
Test status
Simulation time 83625103721 ps
CPU time 176.86 seconds
Started Jun 13 02:32:02 PM PDT 24
Finished Jun 13 02:35:04 PM PDT 24
Peak memory 213460 kb
Host smart-0d68290d-bd80-44a1-bc50-080ebb2e2b04
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488667682 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.2488667682
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.2812985482
Short name T513
Test name
Test status
Simulation time 448426723 ps
CPU time 1.6 seconds
Started Jun 13 02:32:06 PM PDT 24
Finished Jun 13 02:32:13 PM PDT 24
Peak memory 201880 kb
Host smart-4a1f75db-b837-4e9c-8d2a-80666d4eb0bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812985482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.2812985482
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.3809419001
Short name T230
Test name
Test status
Simulation time 482108410954 ps
CPU time 514.28 seconds
Started Jun 13 02:32:02 PM PDT 24
Finished Jun 13 02:40:42 PM PDT 24
Peak memory 202220 kb
Host smart-0db15f7d-77e9-4cf9-80f1-519ad1892cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809419001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.3809419001
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.2186904953
Short name T355
Test name
Test status
Simulation time 167786573753 ps
CPU time 96.49 seconds
Started Jun 13 02:32:12 PM PDT 24
Finished Jun 13 02:33:56 PM PDT 24
Peak memory 202252 kb
Host smart-4f1414b1-1e1f-47f2-a676-256bd4bc632d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186904953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.2186904953
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.3274572546
Short name T599
Test name
Test status
Simulation time 494810229153 ps
CPU time 293.03 seconds
Started Jun 13 02:31:59 PM PDT 24
Finished Jun 13 02:36:57 PM PDT 24
Peak memory 202216 kb
Host smart-a1e4a3f9-ca86-4e6c-9b10-31587c0dd780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274572546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.3274572546
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.678755522
Short name T679
Test name
Test status
Simulation time 318802757604 ps
CPU time 355.56 seconds
Started Jun 13 02:32:04 PM PDT 24
Finished Jun 13 02:38:06 PM PDT 24
Peak memory 202176 kb
Host smart-7361c054-1482-43b9-975c-fc7a7b16e44a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=678755522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fixe
d.678755522
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.2778639040
Short name T146
Test name
Test status
Simulation time 625894875208 ps
CPU time 253.39 seconds
Started Jun 13 02:32:08 PM PDT 24
Finished Jun 13 02:36:28 PM PDT 24
Peak memory 202208 kb
Host smart-e01903df-9364-40f3-b8fc-fbc28b5394f2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778639040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.2778639040
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.2591008018
Short name T424
Test name
Test status
Simulation time 607346868209 ps
CPU time 423.5 seconds
Started Jun 13 02:32:01 PM PDT 24
Finished Jun 13 02:39:09 PM PDT 24
Peak memory 202264 kb
Host smart-5f5ac840-2a90-40b4-95fb-7009b9437365
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591008018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.2591008018
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.2996983550
Short name T725
Test name
Test status
Simulation time 113272066163 ps
CPU time 420.1 seconds
Started Jun 13 02:32:10 PM PDT 24
Finished Jun 13 02:39:18 PM PDT 24
Peak memory 202640 kb
Host smart-0dc78a30-1a82-4d3e-8667-f02bd9f89945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996983550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.2996983550
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.359961760
Short name T633
Test name
Test status
Simulation time 38289857792 ps
CPU time 23.85 seconds
Started Jun 13 02:32:11 PM PDT 24
Finished Jun 13 02:32:42 PM PDT 24
Peak memory 202036 kb
Host smart-2d172446-0aad-4ceb-b49f-6e85450c422d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359961760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.359961760
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.1781739288
Short name T438
Test name
Test status
Simulation time 4230211892 ps
CPU time 10.57 seconds
Started Jun 13 02:32:04 PM PDT 24
Finished Jun 13 02:32:21 PM PDT 24
Peak memory 202016 kb
Host smart-85f8d083-d505-42cc-bf5c-f1cae4ed36e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781739288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.1781739288
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.3275942525
Short name T444
Test name
Test status
Simulation time 5703813704 ps
CPU time 13.14 seconds
Started Jun 13 02:32:06 PM PDT 24
Finished Jun 13 02:32:25 PM PDT 24
Peak memory 202220 kb
Host smart-a1e7844e-210f-4fe1-83f1-18cf6acc264d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275942525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.3275942525
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.3375513613
Short name T727
Test name
Test status
Simulation time 141806576971 ps
CPU time 632.08 seconds
Started Jun 13 02:32:08 PM PDT 24
Finished Jun 13 02:42:46 PM PDT 24
Peak memory 202544 kb
Host smart-b4a087d1-2b48-4218-aeec-5733028b1bac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375513613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.3375513613
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.1671094975
Short name T242
Test name
Test status
Simulation time 47388788921 ps
CPU time 111.49 seconds
Started Jun 13 02:32:09 PM PDT 24
Finished Jun 13 02:34:07 PM PDT 24
Peak memory 210752 kb
Host smart-b84cba56-ad3a-484d-b061-bee6cda273f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671094975 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.1671094975
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.4229290397
Short name T636
Test name
Test status
Simulation time 347342570 ps
CPU time 0.97 seconds
Started Jun 13 02:32:03 PM PDT 24
Finished Jun 13 02:32:09 PM PDT 24
Peak memory 201908 kb
Host smart-ee4b732a-f302-4541-b160-100172cbb0da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229290397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.4229290397
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.277204439
Short name T257
Test name
Test status
Simulation time 323387728426 ps
CPU time 205.15 seconds
Started Jun 13 02:32:02 PM PDT 24
Finished Jun 13 02:35:33 PM PDT 24
Peak memory 202252 kb
Host smart-a9ca14b5-6bd0-4185-aba3-fa434c1c517b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277204439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.277204439
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.3207353
Short name T455
Test name
Test status
Simulation time 334709362745 ps
CPU time 740.34 seconds
Started Jun 13 02:32:06 PM PDT 24
Finished Jun 13 02:44:32 PM PDT 24
Peak memory 202176 kb
Host smart-5c154d1a-1d67-4e0b-980e-a391496ade7c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt_
fixed.3207353
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.3932345072
Short name T603
Test name
Test status
Simulation time 332574323847 ps
CPU time 393.43 seconds
Started Jun 13 02:32:07 PM PDT 24
Finished Jun 13 02:38:46 PM PDT 24
Peak memory 202212 kb
Host smart-33e2e839-8dd9-474e-8f20-d381ae59f419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932345072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.3932345072
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.475513589
Short name T583
Test name
Test status
Simulation time 161408478906 ps
CPU time 87.7 seconds
Started Jun 13 02:32:14 PM PDT 24
Finished Jun 13 02:33:49 PM PDT 24
Peak memory 202200 kb
Host smart-dca42497-eb45-4b36-a2b4-e485ff66442f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=475513589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fixe
d.475513589
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.2060375825
Short name T153
Test name
Test status
Simulation time 573785258575 ps
CPU time 1227.48 seconds
Started Jun 13 02:32:05 PM PDT 24
Finished Jun 13 02:52:39 PM PDT 24
Peak memory 202280 kb
Host smart-e9854d2b-d644-455a-ad4f-c4c4433265cc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060375825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.2060375825
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.2290400774
Short name T759
Test name
Test status
Simulation time 382522768181 ps
CPU time 241.77 seconds
Started Jun 13 02:32:04 PM PDT 24
Finished Jun 13 02:36:11 PM PDT 24
Peak memory 202172 kb
Host smart-36d3a9a6-2037-4078-a4e2-ceec1b8900e9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290400774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.2290400774
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.1791619008
Short name T643
Test name
Test status
Simulation time 99924296937 ps
CPU time 350.74 seconds
Started Jun 13 02:31:59 PM PDT 24
Finished Jun 13 02:37:54 PM PDT 24
Peak memory 202560 kb
Host smart-ee875b0d-4e10-4730-9c19-78c55e13d8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791619008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.1791619008
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.3584620971
Short name T506
Test name
Test status
Simulation time 45670623317 ps
CPU time 56.53 seconds
Started Jun 13 02:32:04 PM PDT 24
Finished Jun 13 02:33:07 PM PDT 24
Peak memory 202064 kb
Host smart-e7835a70-123a-4733-8054-eaad9ce7aa63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584620971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.3584620971
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.2191411242
Short name T388
Test name
Test status
Simulation time 3993148175 ps
CPU time 3.24 seconds
Started Jun 13 02:32:03 PM PDT 24
Finished Jun 13 02:32:12 PM PDT 24
Peak memory 202032 kb
Host smart-4974c373-afc4-4cdc-bf46-40ceec15a8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191411242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.2191411242
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.3094364645
Short name T452
Test name
Test status
Simulation time 5828162913 ps
CPU time 13.26 seconds
Started Jun 13 02:32:07 PM PDT 24
Finished Jun 13 02:32:26 PM PDT 24
Peak memory 202048 kb
Host smart-a043e2bb-9e65-4274-bebd-c767c902785e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094364645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.3094364645
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.633468537
Short name T766
Test name
Test status
Simulation time 45966222351 ps
CPU time 55.72 seconds
Started Jun 13 02:32:07 PM PDT 24
Finished Jun 13 02:33:09 PM PDT 24
Peak memory 202276 kb
Host smart-a428c3d3-e03d-4df1-8810-4f071d270444
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633468537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all.
633468537
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.1582949404
Short name T428
Test name
Test status
Simulation time 376560967 ps
CPU time 1.49 seconds
Started Jun 13 02:32:16 PM PDT 24
Finished Jun 13 02:32:25 PM PDT 24
Peak memory 201912 kb
Host smart-ee439496-e494-4ba7-8c76-ecb36f12a614
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582949404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.1582949404
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.259541943
Short name T204
Test name
Test status
Simulation time 322977834643 ps
CPU time 710.92 seconds
Started Jun 13 02:32:08 PM PDT 24
Finished Jun 13 02:44:06 PM PDT 24
Peak memory 202208 kb
Host smart-0d441015-275f-425d-855c-bb74056ffd19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259541943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.259541943
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.3179609907
Short name T453
Test name
Test status
Simulation time 488055811789 ps
CPU time 74.6 seconds
Started Jun 13 02:32:04 PM PDT 24
Finished Jun 13 02:33:24 PM PDT 24
Peak memory 202180 kb
Host smart-371b473f-2efc-4817-a7b2-8e35e31bf6da
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179609907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.3179609907
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.1001979177
Short name T551
Test name
Test status
Simulation time 160421578054 ps
CPU time 92.36 seconds
Started Jun 13 02:32:07 PM PDT 24
Finished Jun 13 02:33:46 PM PDT 24
Peak memory 202104 kb
Host smart-da60103c-b9d6-496c-90c6-89980b290306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001979177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.1001979177
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.2156320419
Short name T476
Test name
Test status
Simulation time 330017133359 ps
CPU time 192.2 seconds
Started Jun 13 02:32:12 PM PDT 24
Finished Jun 13 02:35:32 PM PDT 24
Peak memory 202176 kb
Host smart-5a69ef4e-3e65-4462-a06d-00257b47147e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156320419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.2156320419
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.3099606607
Short name T219
Test name
Test status
Simulation time 368303167064 ps
CPU time 413.79 seconds
Started Jun 13 02:32:04 PM PDT 24
Finished Jun 13 02:39:03 PM PDT 24
Peak memory 202292 kb
Host smart-9aea87f3-9121-4e72-a233-62e13a7c8c06
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099606607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.3099606607
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.2509309015
Short name T588
Test name
Test status
Simulation time 392645661610 ps
CPU time 822.67 seconds
Started Jun 13 02:32:05 PM PDT 24
Finished Jun 13 02:45:54 PM PDT 24
Peak memory 202180 kb
Host smart-31e583ea-1db2-4d8e-a628-0053e1170e53
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509309015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.2509309015
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.3552311710
Short name T620
Test name
Test status
Simulation time 107189826735 ps
CPU time 331.24 seconds
Started Jun 13 02:32:05 PM PDT 24
Finished Jun 13 02:37:42 PM PDT 24
Peak memory 202604 kb
Host smart-01fbab3b-0be2-445c-93b0-aea98ad389d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552311710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.3552311710
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.3993159117
Short name T29
Test name
Test status
Simulation time 24902400880 ps
CPU time 53.96 seconds
Started Jun 13 02:32:08 PM PDT 24
Finished Jun 13 02:33:09 PM PDT 24
Peak memory 202040 kb
Host smart-a6381696-e2ef-4b73-9772-9dcd5dbe2730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993159117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.3993159117
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.3653757987
Short name T572
Test name
Test status
Simulation time 2802090052 ps
CPU time 2.36 seconds
Started Jun 13 02:32:04 PM PDT 24
Finished Jun 13 02:32:12 PM PDT 24
Peak memory 202040 kb
Host smart-307093fa-4158-41b6-b9cf-ccfb28862c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653757987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.3653757987
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.2498298987
Short name T384
Test name
Test status
Simulation time 5938460609 ps
CPU time 14.95 seconds
Started Jun 13 02:32:11 PM PDT 24
Finished Jun 13 02:32:34 PM PDT 24
Peak memory 202072 kb
Host smart-c5ff7914-a48b-4134-a4b1-8f27582885fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498298987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.2498298987
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.1172561567
Short name T748
Test name
Test status
Simulation time 335117605730 ps
CPU time 765.66 seconds
Started Jun 13 02:32:17 PM PDT 24
Finished Jun 13 02:45:11 PM PDT 24
Peak memory 202192 kb
Host smart-78038de0-7eba-4e75-abfa-4187d6d7c7a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172561567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.1172561567
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.4250522519
Short name T21
Test name
Test status
Simulation time 87060921318 ps
CPU time 40.24 seconds
Started Jun 13 02:32:04 PM PDT 24
Finished Jun 13 02:32:50 PM PDT 24
Peak memory 202332 kb
Host smart-85c4978c-bf89-49b6-86f9-1756e7829e82
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250522519 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.4250522519
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.2403426319
Short name T359
Test name
Test status
Simulation time 396632681 ps
CPU time 0.85 seconds
Started Jun 13 02:31:28 PM PDT 24
Finished Jun 13 02:31:34 PM PDT 24
Peak memory 201900 kb
Host smart-09b6ae61-5ed2-44ba-b50a-82293fb4716b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403426319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.2403426319
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.2656071333
Short name T202
Test name
Test status
Simulation time 179662229905 ps
CPU time 218.83 seconds
Started Jun 13 02:31:27 PM PDT 24
Finished Jun 13 02:35:11 PM PDT 24
Peak memory 202188 kb
Host smart-38782a69-e76a-43cf-94ea-2444611c8aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656071333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.2656071333
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.1584874950
Short name T280
Test name
Test status
Simulation time 163286735317 ps
CPU time 99.37 seconds
Started Jun 13 02:31:27 PM PDT 24
Finished Jun 13 02:33:11 PM PDT 24
Peak memory 202200 kb
Host smart-4cde54f6-8644-4c4f-a503-859f7c1bd57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584874950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.1584874950
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.2171722277
Short name T360
Test name
Test status
Simulation time 500841378037 ps
CPU time 519.65 seconds
Started Jun 13 02:31:26 PM PDT 24
Finished Jun 13 02:40:11 PM PDT 24
Peak memory 202144 kb
Host smart-000b780f-3155-481e-8e73-c2dc36fa877d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171722277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.2171722277
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.3586773786
Short name T394
Test name
Test status
Simulation time 481798189689 ps
CPU time 547.72 seconds
Started Jun 13 02:31:21 PM PDT 24
Finished Jun 13 02:40:31 PM PDT 24
Peak memory 202220 kb
Host smart-96f2142f-8bcd-4740-9553-57e3b2832da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586773786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.3586773786
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.1858463808
Short name T600
Test name
Test status
Simulation time 161119317541 ps
CPU time 356.42 seconds
Started Jun 13 02:31:26 PM PDT 24
Finished Jun 13 02:37:27 PM PDT 24
Peak memory 202248 kb
Host smart-f31fa001-69c8-4709-89ad-8db5269846f2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858463808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.1858463808
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.3654070053
Short name T164
Test name
Test status
Simulation time 357849001337 ps
CPU time 416.22 seconds
Started Jun 13 02:31:48 PM PDT 24
Finished Jun 13 02:38:47 PM PDT 24
Peak memory 202192 kb
Host smart-f76b1e4e-a55e-41c1-8dc1-5b52b5eff3de
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654070053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.3654070053
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.1751075343
Short name T123
Test name
Test status
Simulation time 197387036324 ps
CPU time 67.97 seconds
Started Jun 13 02:31:36 PM PDT 24
Finished Jun 13 02:32:50 PM PDT 24
Peak memory 202184 kb
Host smart-0653ae35-f640-42dd-82db-99a2c37a5ba7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751075343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.1751075343
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.3114087642
Short name T456
Test name
Test status
Simulation time 82610730983 ps
CPU time 446 seconds
Started Jun 13 02:31:25 PM PDT 24
Finished Jun 13 02:38:56 PM PDT 24
Peak memory 202592 kb
Host smart-7ac0d522-862d-485f-bc9b-8d97231b045a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114087642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.3114087642
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.3383404022
Short name T547
Test name
Test status
Simulation time 26689627768 ps
CPU time 62.39 seconds
Started Jun 13 02:31:32 PM PDT 24
Finished Jun 13 02:32:41 PM PDT 24
Peak memory 202016 kb
Host smart-912b2416-2bce-46f4-9ba3-115ae63c5c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383404022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.3383404022
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.3622403036
Short name T361
Test name
Test status
Simulation time 4027951864 ps
CPU time 4.96 seconds
Started Jun 13 02:31:34 PM PDT 24
Finished Jun 13 02:31:45 PM PDT 24
Peak memory 202052 kb
Host smart-47864d04-f2ba-4600-8073-1d423db8a8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622403036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.3622403036
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.58338374
Short name T75
Test name
Test status
Simulation time 8422651709 ps
CPU time 4.18 seconds
Started Jun 13 02:31:32 PM PDT 24
Finished Jun 13 02:31:42 PM PDT 24
Peak memory 218856 kb
Host smart-292c89fc-4d74-415e-8fdc-629392c229eb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58338374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.58338374
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.393396433
Short name T103
Test name
Test status
Simulation time 5795841788 ps
CPU time 2.71 seconds
Started Jun 13 02:31:22 PM PDT 24
Finished Jun 13 02:31:29 PM PDT 24
Peak memory 202028 kb
Host smart-2ad5b530-26af-4051-a0e5-ddbccdbceffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393396433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.393396433
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.2547511694
Short name T177
Test name
Test status
Simulation time 279685479959 ps
CPU time 410.5 seconds
Started Jun 13 02:31:35 PM PDT 24
Finished Jun 13 02:38:31 PM PDT 24
Peak memory 212908 kb
Host smart-4cb88f8d-5d63-443d-86ad-b7cdf3bb5550
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547511694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
2547511694
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.213744455
Short name T118
Test name
Test status
Simulation time 90372862035 ps
CPU time 262.23 seconds
Started Jun 13 02:31:25 PM PDT 24
Finished Jun 13 02:35:52 PM PDT 24
Peak memory 211932 kb
Host smart-4d836219-281c-45fc-8f72-9eb0acc797b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213744455 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.213744455
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.926771171
Short name T505
Test name
Test status
Simulation time 498749653 ps
CPU time 0.88 seconds
Started Jun 13 02:32:17 PM PDT 24
Finished Jun 13 02:32:26 PM PDT 24
Peak memory 201912 kb
Host smart-71a66fb5-fa89-4042-9ce6-a1259aa72794
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926771171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.926771171
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.1062891351
Short name T507
Test name
Test status
Simulation time 325871856587 ps
CPU time 199.86 seconds
Started Jun 13 02:32:08 PM PDT 24
Finished Jun 13 02:35:34 PM PDT 24
Peak memory 202268 kb
Host smart-e9383920-90f2-4ca3-9be6-e048d8f31c5a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062891351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.1062891351
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.3824030505
Short name T210
Test name
Test status
Simulation time 172480159360 ps
CPU time 348.75 seconds
Started Jun 13 02:32:05 PM PDT 24
Finished Jun 13 02:37:59 PM PDT 24
Peak memory 202176 kb
Host smart-6a967d40-d2f8-4d0c-803b-10a2033d2b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824030505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.3824030505
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.384464352
Short name T458
Test name
Test status
Simulation time 331304454884 ps
CPU time 82.28 seconds
Started Jun 13 02:32:07 PM PDT 24
Finished Jun 13 02:33:35 PM PDT 24
Peak memory 202312 kb
Host smart-bf62f4e8-75ab-49eb-b16a-19a073f8b059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384464352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.384464352
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.2841131401
Short name T523
Test name
Test status
Simulation time 324891267722 ps
CPU time 189.72 seconds
Started Jun 13 02:32:16 PM PDT 24
Finished Jun 13 02:35:33 PM PDT 24
Peak memory 202168 kb
Host smart-efab1856-528d-45fa-adb2-d5d115dcc214
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841131401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.2841131401
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.1231522567
Short name T491
Test name
Test status
Simulation time 169123490427 ps
CPU time 97.15 seconds
Started Jun 13 02:32:08 PM PDT 24
Finished Jun 13 02:33:51 PM PDT 24
Peak memory 202220 kb
Host smart-01ce8739-a86c-40f9-a46a-bdce5428c7b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231522567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.1231522567
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.2349424903
Short name T422
Test name
Test status
Simulation time 488119917860 ps
CPU time 494.34 seconds
Started Jun 13 02:32:08 PM PDT 24
Finished Jun 13 02:40:29 PM PDT 24
Peak memory 202148 kb
Host smart-b567f837-1fcb-4c7f-af36-65a9bdce22ee
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349424903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.2349424903
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.447208824
Short name T252
Test name
Test status
Simulation time 643284033039 ps
CPU time 1391.31 seconds
Started Jun 13 02:32:16 PM PDT 24
Finished Jun 13 02:55:36 PM PDT 24
Peak memory 202192 kb
Host smart-514f9beb-2259-4362-970c-923743ef8d61
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447208824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_
wakeup.447208824
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.4077255121
Short name T363
Test name
Test status
Simulation time 401038883826 ps
CPU time 948.32 seconds
Started Jun 13 02:32:07 PM PDT 24
Finished Jun 13 02:48:01 PM PDT 24
Peak memory 202292 kb
Host smart-a180237a-9ae5-4d3b-b435-312823236fe4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077255121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.4077255121
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.3591310302
Short name T376
Test name
Test status
Simulation time 124892093567 ps
CPU time 522.66 seconds
Started Jun 13 02:32:16 PM PDT 24
Finished Jun 13 02:41:07 PM PDT 24
Peak memory 202580 kb
Host smart-eb2b16e3-9f80-4fea-a95a-bc0d15fb02eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591310302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.3591310302
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.4140325862
Short name T447
Test name
Test status
Simulation time 25971985594 ps
CPU time 9.25 seconds
Started Jun 13 02:32:04 PM PDT 24
Finished Jun 13 02:32:18 PM PDT 24
Peak memory 202008 kb
Host smart-989d0d21-e0cf-4848-8ed4-177153dc12f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140325862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.4140325862
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.685016617
Short name T155
Test name
Test status
Simulation time 3995714854 ps
CPU time 10.45 seconds
Started Jun 13 02:32:07 PM PDT 24
Finished Jun 13 02:32:22 PM PDT 24
Peak memory 202064 kb
Host smart-9e687a1e-8e41-4460-b81f-1eea580294eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685016617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.685016617
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.2177928419
Short name T655
Test name
Test status
Simulation time 5815399635 ps
CPU time 8.3 seconds
Started Jun 13 02:32:15 PM PDT 24
Finished Jun 13 02:32:31 PM PDT 24
Peak memory 201996 kb
Host smart-1f1c3cdc-6c6b-4426-b5d7-e7844eace443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177928419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.2177928419
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.2962889289
Short name T764
Test name
Test status
Simulation time 337661101325 ps
CPU time 1799.76 seconds
Started Jun 13 02:32:08 PM PDT 24
Finished Jun 13 03:02:13 PM PDT 24
Peak memory 202312 kb
Host smart-ccbabf10-e74a-49cc-b78e-687797c1bb9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962889289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.2962889289
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.4245894358
Short name T561
Test name
Test status
Simulation time 408535984 ps
CPU time 0.7 seconds
Started Jun 13 02:32:10 PM PDT 24
Finished Jun 13 02:32:18 PM PDT 24
Peak memory 201920 kb
Host smart-92de5b52-b5bb-417d-b3f6-98a791b98acf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245894358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.4245894358
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.3375349806
Short name T653
Test name
Test status
Simulation time 325137209719 ps
CPU time 365.7 seconds
Started Jun 13 02:32:16 PM PDT 24
Finished Jun 13 02:38:30 PM PDT 24
Peak memory 202216 kb
Host smart-25b42527-d6fa-4a0d-b696-4e145ebf7f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375349806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.3375349806
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.3093959776
Short name T589
Test name
Test status
Simulation time 503322239252 ps
CPU time 1085.52 seconds
Started Jun 13 02:32:11 PM PDT 24
Finished Jun 13 02:50:24 PM PDT 24
Peak memory 202176 kb
Host smart-f495e408-321f-460b-a156-49cf5d4e054d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093959776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.3093959776
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.2711376814
Short name T664
Test name
Test status
Simulation time 494087618136 ps
CPU time 367.47 seconds
Started Jun 13 02:32:13 PM PDT 24
Finished Jun 13 02:38:28 PM PDT 24
Peak memory 202268 kb
Host smart-19a36723-017a-4b49-8d39-abb87454ac9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711376814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.2711376814
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.1714990360
Short name T668
Test name
Test status
Simulation time 330773354046 ps
CPU time 728.77 seconds
Started Jun 13 02:32:09 PM PDT 24
Finished Jun 13 02:44:25 PM PDT 24
Peak memory 202172 kb
Host smart-e2df5f97-3276-4e96-81a3-0af77d4fb8ab
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714990360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.1714990360
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.1835602579
Short name T228
Test name
Test status
Simulation time 354428209886 ps
CPU time 76.85 seconds
Started Jun 13 02:32:10 PM PDT 24
Finished Jun 13 02:33:34 PM PDT 24
Peak memory 202272 kb
Host smart-11908a0c-3e6f-45a8-a941-bd0fb7f0c224
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835602579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.1835602579
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.3341923829
Short name T81
Test name
Test status
Simulation time 396654304381 ps
CPU time 646.61 seconds
Started Jun 13 02:32:12 PM PDT 24
Finished Jun 13 02:43:07 PM PDT 24
Peak memory 202252 kb
Host smart-c1276fa5-08d3-4f5d-89ee-9c2d4b93b25a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341923829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.3341923829
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.4005061105
Short name T470
Test name
Test status
Simulation time 132435791938 ps
CPU time 419.03 seconds
Started Jun 13 02:32:09 PM PDT 24
Finished Jun 13 02:39:15 PM PDT 24
Peak memory 202532 kb
Host smart-dc23eb4c-b531-4f13-9a16-679e52ed5f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005061105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.4005061105
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.1162301612
Short name T654
Test name
Test status
Simulation time 30473211995 ps
CPU time 39.45 seconds
Started Jun 13 02:32:10 PM PDT 24
Finished Jun 13 02:32:56 PM PDT 24
Peak memory 202040 kb
Host smart-162c160e-58e5-4ee8-8888-9813d495cd51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162301612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.1162301612
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.4234569589
Short name T369
Test name
Test status
Simulation time 5282814284 ps
CPU time 13.29 seconds
Started Jun 13 02:32:12 PM PDT 24
Finished Jun 13 02:32:33 PM PDT 24
Peak memory 202036 kb
Host smart-5342ecfc-a29f-4e89-b271-697bb5492331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234569589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.4234569589
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.4280148438
Short name T478
Test name
Test status
Simulation time 5924587537 ps
CPU time 4.18 seconds
Started Jun 13 02:32:11 PM PDT 24
Finished Jun 13 02:32:22 PM PDT 24
Peak memory 202060 kb
Host smart-f67cf740-b61f-436b-b6be-148849ebd71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280148438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.4280148438
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.215427804
Short name T675
Test name
Test status
Simulation time 33231740763 ps
CPU time 20.94 seconds
Started Jun 13 02:32:11 PM PDT 24
Finished Jun 13 02:32:38 PM PDT 24
Peak memory 202032 kb
Host smart-998479e5-b6fd-4107-9d6b-8b0298bd8f11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215427804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all.
215427804
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.4043832316
Short name T20
Test name
Test status
Simulation time 34468202827 ps
CPU time 84.18 seconds
Started Jun 13 02:32:12 PM PDT 24
Finished Jun 13 02:33:44 PM PDT 24
Peak memory 210916 kb
Host smart-f6324285-add4-44f9-93ec-988357a2f4fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043832316 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.4043832316
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.2847023136
Short name T16
Test name
Test status
Simulation time 434969106 ps
CPU time 0.88 seconds
Started Jun 13 02:32:16 PM PDT 24
Finished Jun 13 02:32:25 PM PDT 24
Peak memory 201912 kb
Host smart-d14c9100-0396-4778-a011-b3613ef03d39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847023136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.2847023136
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.2899309753
Short name T167
Test name
Test status
Simulation time 349674301870 ps
CPU time 351.58 seconds
Started Jun 13 02:32:18 PM PDT 24
Finished Jun 13 02:38:18 PM PDT 24
Peak memory 202300 kb
Host smart-7e40effe-bd2d-4c09-958f-9991873e79c9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899309753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.2899309753
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.2990463381
Short name T756
Test name
Test status
Simulation time 522821785136 ps
CPU time 434.92 seconds
Started Jun 13 02:32:16 PM PDT 24
Finished Jun 13 02:39:39 PM PDT 24
Peak memory 202176 kb
Host smart-aa9bc802-f8df-47e6-8dce-1057923108f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990463381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.2990463381
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.3719927290
Short name T310
Test name
Test status
Simulation time 161441285166 ps
CPU time 156.21 seconds
Started Jun 13 02:32:18 PM PDT 24
Finished Jun 13 02:35:03 PM PDT 24
Peak memory 202212 kb
Host smart-a281c6e4-ee7c-44d7-952d-98d07a4f34a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719927290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.3719927290
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.1656258456
Short name T405
Test name
Test status
Simulation time 493355681275 ps
CPU time 826.58 seconds
Started Jun 13 02:32:17 PM PDT 24
Finished Jun 13 02:46:11 PM PDT 24
Peak memory 202176 kb
Host smart-612203e5-4e8f-412f-a547-37990cd676a3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656258456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.1656258456
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.3568537269
Short name T325
Test name
Test status
Simulation time 334226442293 ps
CPU time 350.75 seconds
Started Jun 13 02:32:17 PM PDT 24
Finished Jun 13 02:38:16 PM PDT 24
Peak memory 202276 kb
Host smart-7e9aa454-dc93-45ad-828a-bfbbeed13b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568537269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.3568537269
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.3012381610
Short name T657
Test name
Test status
Simulation time 490543937335 ps
CPU time 881.73 seconds
Started Jun 13 02:32:16 PM PDT 24
Finished Jun 13 02:47:05 PM PDT 24
Peak memory 202172 kb
Host smart-0791fff8-fb34-4743-b7fa-180837d8afc7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012381610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.3012381610
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.3726566709
Short name T143
Test name
Test status
Simulation time 546658415988 ps
CPU time 75.11 seconds
Started Jun 13 02:32:17 PM PDT 24
Finished Jun 13 02:33:40 PM PDT 24
Peak memory 202196 kb
Host smart-3087be44-10b2-4e6e-8f16-84322b9dfdba
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726566709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.3726566709
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.1715705079
Short name T382
Test name
Test status
Simulation time 394733849236 ps
CPU time 187.04 seconds
Started Jun 13 02:32:18 PM PDT 24
Finished Jun 13 02:35:33 PM PDT 24
Peak memory 202280 kb
Host smart-c923a325-7a13-4088-952b-340f0a8ca112
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715705079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.1715705079
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.1048604781
Short name T176
Test name
Test status
Simulation time 110103521242 ps
CPU time 402.17 seconds
Started Jun 13 02:32:17 PM PDT 24
Finished Jun 13 02:39:07 PM PDT 24
Peak memory 202516 kb
Host smart-ef6c420b-d9a2-451b-9c65-9f60fc873a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048604781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.1048604781
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.1086300696
Short name T84
Test name
Test status
Simulation time 25020005692 ps
CPU time 54.61 seconds
Started Jun 13 02:32:16 PM PDT 24
Finished Jun 13 02:33:19 PM PDT 24
Peak memory 202056 kb
Host smart-c9244275-83bc-458f-b1f5-85f62f165b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086300696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.1086300696
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.2131726112
Short name T663
Test name
Test status
Simulation time 4206948426 ps
CPU time 10.28 seconds
Started Jun 13 02:32:18 PM PDT 24
Finished Jun 13 02:32:37 PM PDT 24
Peak memory 202040 kb
Host smart-82042401-0e99-4293-a51e-7810742f06e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131726112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.2131726112
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.118196805
Short name T427
Test name
Test status
Simulation time 6023149314 ps
CPU time 7.79 seconds
Started Jun 13 02:32:12 PM PDT 24
Finished Jun 13 02:32:27 PM PDT 24
Peak memory 202000 kb
Host smart-046d4c73-cd5f-43e8-85a0-9cd8c4a1a649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118196805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.118196805
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.1105175909
Short name T701
Test name
Test status
Simulation time 18227057011 ps
CPU time 6.03 seconds
Started Jun 13 02:32:16 PM PDT 24
Finished Jun 13 02:32:30 PM PDT 24
Peak memory 202204 kb
Host smart-c6fa1c61-9153-4cf5-8b32-986eae12b471
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105175909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.1105175909
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.3702880625
Short name T302
Test name
Test status
Simulation time 180014335738 ps
CPU time 280.52 seconds
Started Jun 13 02:32:15 PM PDT 24
Finished Jun 13 02:37:03 PM PDT 24
Peak memory 211180 kb
Host smart-519b8579-7044-4da5-939d-d27bd9e1a3d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702880625 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.3702880625
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.2660823386
Short name T667
Test name
Test status
Simulation time 318585320 ps
CPU time 1.33 seconds
Started Jun 13 02:32:24 PM PDT 24
Finished Jun 13 02:32:32 PM PDT 24
Peak memory 201892 kb
Host smart-325092f8-5fb8-47b7-b71e-081607adbdba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660823386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.2660823386
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.2736016517
Short name T709
Test name
Test status
Simulation time 333336071627 ps
CPU time 613.02 seconds
Started Jun 13 02:32:19 PM PDT 24
Finished Jun 13 02:42:40 PM PDT 24
Peak memory 202304 kb
Host smart-7f733ad4-4fb0-44b4-8c23-8c518dc8a0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736016517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.2736016517
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.3363904736
Short name T357
Test name
Test status
Simulation time 160732281477 ps
CPU time 89.24 seconds
Started Jun 13 02:32:18 PM PDT 24
Finished Jun 13 02:33:56 PM PDT 24
Peak memory 202188 kb
Host smart-cd847ffd-c8d4-4651-891b-bee32b6db7a5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363904736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.3363904736
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.2893498556
Short name T477
Test name
Test status
Simulation time 504778060018 ps
CPU time 1188.31 seconds
Started Jun 13 02:32:17 PM PDT 24
Finished Jun 13 02:52:14 PM PDT 24
Peak memory 202252 kb
Host smart-cc06609a-3273-4086-acda-c35e354b57c6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893498556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.2893498556
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.1296391544
Short name T565
Test name
Test status
Simulation time 594628002407 ps
CPU time 1401.05 seconds
Started Jun 13 02:32:24 PM PDT 24
Finished Jun 13 02:55:52 PM PDT 24
Peak memory 202152 kb
Host smart-6e79b87b-a60e-4b6b-8394-36d757eb4a81
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296391544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.1296391544
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.3417888909
Short name T563
Test name
Test status
Simulation time 84338254338 ps
CPU time 349.79 seconds
Started Jun 13 02:32:21 PM PDT 24
Finished Jun 13 02:38:19 PM PDT 24
Peak memory 202576 kb
Host smart-ebeacc48-68fa-458b-a636-ce279c30f8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417888909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.3417888909
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.2463024238
Short name T530
Test name
Test status
Simulation time 36256951966 ps
CPU time 12.32 seconds
Started Jun 13 02:32:23 PM PDT 24
Finished Jun 13 02:32:43 PM PDT 24
Peak memory 202044 kb
Host smart-bc92cf8d-f59b-44e9-8f63-7d98bf7da5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463024238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.2463024238
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.2897477389
Short name T712
Test name
Test status
Simulation time 4967800440 ps
CPU time 7.51 seconds
Started Jun 13 02:32:24 PM PDT 24
Finished Jun 13 02:32:39 PM PDT 24
Peak memory 202052 kb
Host smart-0da847c6-5c04-4b47-8fd4-04fc41cdf99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897477389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.2897477389
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.3811634589
Short name T399
Test name
Test status
Simulation time 5847951131 ps
CPU time 15.05 seconds
Started Jun 13 02:32:18 PM PDT 24
Finished Jun 13 02:32:42 PM PDT 24
Peak memory 202044 kb
Host smart-162ef74c-f895-4959-ab77-ab3763e7da03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811634589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.3811634589
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.1865033430
Short name T274
Test name
Test status
Simulation time 344521924020 ps
CPU time 789.31 seconds
Started Jun 13 02:32:25 PM PDT 24
Finished Jun 13 02:45:42 PM PDT 24
Peak memory 202260 kb
Host smart-4c17dc1e-d598-4168-8f6c-48d2ec79f1c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865033430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.1865033430
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.2308305262
Short name T334
Test name
Test status
Simulation time 415733810 ps
CPU time 1.53 seconds
Started Jun 13 02:32:27 PM PDT 24
Finished Jun 13 02:32:34 PM PDT 24
Peak memory 201924 kb
Host smart-ac3748d5-52fd-484b-8c80-5c20bb1ac231
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308305262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.2308305262
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.67533274
Short name T785
Test name
Test status
Simulation time 484763219834 ps
CPU time 257.2 seconds
Started Jun 13 02:32:23 PM PDT 24
Finished Jun 13 02:36:48 PM PDT 24
Peak memory 202176 kb
Host smart-f7ca6c58-161a-4c6d-ae02-9f0e98c2711d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67533274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gatin
g.67533274
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.2369491858
Short name T612
Test name
Test status
Simulation time 163619474059 ps
CPU time 368.93 seconds
Started Jun 13 02:32:22 PM PDT 24
Finished Jun 13 02:38:39 PM PDT 24
Peak memory 202204 kb
Host smart-f60aed08-e95a-42b7-b301-a077f802fd5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369491858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.2369491858
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.2684106813
Short name T82
Test name
Test status
Simulation time 488724015466 ps
CPU time 1195.73 seconds
Started Jun 13 02:32:21 PM PDT 24
Finished Jun 13 02:52:25 PM PDT 24
Peak memory 202152 kb
Host smart-b4f6a077-9b09-4b17-ac21-378fc71c5f01
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684106813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.2684106813
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.2910174846
Short name T165
Test name
Test status
Simulation time 495667755278 ps
CPU time 92.25 seconds
Started Jun 13 02:32:22 PM PDT 24
Finished Jun 13 02:34:02 PM PDT 24
Peak memory 202212 kb
Host smart-b73993c2-92c1-4116-b024-3a882777c1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910174846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.2910174846
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.701880239
Short name T352
Test name
Test status
Simulation time 328002833976 ps
CPU time 697.62 seconds
Started Jun 13 02:32:23 PM PDT 24
Finished Jun 13 02:44:08 PM PDT 24
Peak memory 202176 kb
Host smart-24c14be8-224d-4459-a4fc-8dd5c4392278
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=701880239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fixe
d.701880239
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.4039892739
Short name T128
Test name
Test status
Simulation time 519189189779 ps
CPU time 476.48 seconds
Started Jun 13 02:32:22 PM PDT 24
Finished Jun 13 02:40:26 PM PDT 24
Peak memory 202468 kb
Host smart-96401a79-54ac-447a-bcf1-140a8c0ce90b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039892739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.4039892739
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.345470643
Short name T213
Test name
Test status
Simulation time 410906294584 ps
CPU time 955.09 seconds
Started Jun 13 02:32:23 PM PDT 24
Finished Jun 13 02:48:26 PM PDT 24
Peak memory 202176 kb
Host smart-b8e7b7ce-443a-4cc1-b91a-176257c1c17d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345470643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
adc_ctrl_filters_wakeup_fixed.345470643
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.2893370021
Short name T327
Test name
Test status
Simulation time 92244506140 ps
CPU time 478.13 seconds
Started Jun 13 02:32:23 PM PDT 24
Finished Jun 13 02:40:29 PM PDT 24
Peak memory 202544 kb
Host smart-4cc74bb3-fd1f-4567-87a4-0d954c0a4c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893370021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.2893370021
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.3065665328
Short name T734
Test name
Test status
Simulation time 23781082457 ps
CPU time 51.71 seconds
Started Jun 13 02:32:22 PM PDT 24
Finished Jun 13 02:33:22 PM PDT 24
Peak memory 202004 kb
Host smart-cbfb2f4f-6bef-4895-9089-01627734075a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065665328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.3065665328
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.4133255931
Short name T412
Test name
Test status
Simulation time 5765206633 ps
CPU time 2.35 seconds
Started Jun 13 02:32:21 PM PDT 24
Finished Jun 13 02:32:32 PM PDT 24
Peak memory 202000 kb
Host smart-8903600c-7161-4ca3-bcfa-eb014b9346a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133255931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.4133255931
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.3017821845
Short name T598
Test name
Test status
Simulation time 5790349728 ps
CPU time 10.23 seconds
Started Jun 13 02:32:25 PM PDT 24
Finished Jun 13 02:32:42 PM PDT 24
Peak memory 202048 kb
Host smart-e7c3991c-351b-4098-8125-2ce6832ca13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017821845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.3017821845
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.3764751446
Short name T587
Test name
Test status
Simulation time 505406973908 ps
CPU time 276.35 seconds
Started Jun 13 02:32:27 PM PDT 24
Finished Jun 13 02:37:09 PM PDT 24
Peak memory 202228 kb
Host smart-cb6a5311-63fd-47a0-b931-f00d06196663
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764751446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.3764751446
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.330567636
Short name T686
Test name
Test status
Simulation time 325524866 ps
CPU time 1.36 seconds
Started Jun 13 02:32:36 PM PDT 24
Finished Jun 13 02:32:39 PM PDT 24
Peak memory 201880 kb
Host smart-2ca3ab58-0897-4ccf-92c9-b34c290b7ddd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330567636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.330567636
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.1734759714
Short name T159
Test name
Test status
Simulation time 527424796042 ps
CPU time 308.7 seconds
Started Jun 13 02:32:40 PM PDT 24
Finished Jun 13 02:37:51 PM PDT 24
Peak memory 202272 kb
Host smart-a89628c5-e96c-4b68-aee5-881c52f2195d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734759714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.1734759714
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.4052858322
Short name T787
Test name
Test status
Simulation time 162896191440 ps
CPU time 203.26 seconds
Started Jun 13 02:32:40 PM PDT 24
Finished Jun 13 02:36:05 PM PDT 24
Peak memory 202188 kb
Host smart-fb139ab3-9314-487c-8f47-84919b33bd36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052858322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.4052858322
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.1533357080
Short name T642
Test name
Test status
Simulation time 494073304405 ps
CPU time 583.56 seconds
Started Jun 13 02:32:28 PM PDT 24
Finished Jun 13 02:42:17 PM PDT 24
Peak memory 202160 kb
Host smart-631dc144-df21-4f21-bf75-e0f84a394ec3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533357080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.1533357080
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.1405402801
Short name T773
Test name
Test status
Simulation time 498208140503 ps
CPU time 1068.77 seconds
Started Jun 13 02:32:29 PM PDT 24
Finished Jun 13 02:50:22 PM PDT 24
Peak memory 202224 kb
Host smart-88e6f9f2-a2ef-40b1-b14f-32226df9e03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405402801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.1405402801
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.3521344110
Short name T750
Test name
Test status
Simulation time 326681344511 ps
CPU time 189.05 seconds
Started Jun 13 02:32:33 PM PDT 24
Finished Jun 13 02:35:46 PM PDT 24
Peak memory 202124 kb
Host smart-b26ee0fe-6f4e-4160-a378-4af808c9a1eb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521344110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.3521344110
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.165388464
Short name T753
Test name
Test status
Simulation time 390175876660 ps
CPU time 915.26 seconds
Started Jun 13 02:32:40 PM PDT 24
Finished Jun 13 02:47:57 PM PDT 24
Peak memory 202192 kb
Host smart-494418fc-5d8f-4436-9560-36eb043d5805
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165388464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_
wakeup.165388464
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.1426361483
Short name T665
Test name
Test status
Simulation time 194158981948 ps
CPU time 426.72 seconds
Started Jun 13 02:32:41 PM PDT 24
Finished Jun 13 02:39:49 PM PDT 24
Peak memory 202176 kb
Host smart-cca78edb-76a6-4713-85f4-39b81669c4c6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426361483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.1426361483
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.147636914
Short name T184
Test name
Test status
Simulation time 92286268073 ps
CPU time 392.85 seconds
Started Jun 13 02:32:34 PM PDT 24
Finished Jun 13 02:39:10 PM PDT 24
Peak memory 202568 kb
Host smart-a6a6949c-8046-4cb3-9e3e-225641431844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147636914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.147636914
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.1091393059
Short name T12
Test name
Test status
Simulation time 22924211570 ps
CPU time 14.3 seconds
Started Jun 13 02:32:34 PM PDT 24
Finished Jun 13 02:32:51 PM PDT 24
Peak memory 202040 kb
Host smart-b6779543-1d98-461c-a0b3-af0c27caa2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091393059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.1091393059
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.926723761
Short name T511
Test name
Test status
Simulation time 5032887406 ps
CPU time 3.22 seconds
Started Jun 13 02:32:34 PM PDT 24
Finished Jun 13 02:32:40 PM PDT 24
Peak memory 202052 kb
Host smart-d3de3cee-fb94-40a7-867e-a4ffd5a95bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926723761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.926723761
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.2197221406
Short name T779
Test name
Test status
Simulation time 5483494673 ps
CPU time 4.15 seconds
Started Jun 13 02:32:33 PM PDT 24
Finished Jun 13 02:32:41 PM PDT 24
Peak memory 201996 kb
Host smart-780922f6-cea5-485b-ba0c-e793b7624556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197221406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.2197221406
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.3643703656
Short name T403
Test name
Test status
Simulation time 48966149130 ps
CPU time 102.42 seconds
Started Jun 13 02:32:40 PM PDT 24
Finished Jun 13 02:34:25 PM PDT 24
Peak memory 202024 kb
Host smart-89d76735-fc75-4d33-8f3c-0b0240bc1bb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643703656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.3643703656
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.1624522463
Short name T10
Test name
Test status
Simulation time 266227755322 ps
CPU time 149.85 seconds
Started Jun 13 02:32:36 PM PDT 24
Finished Jun 13 02:35:07 PM PDT 24
Peak memory 202320 kb
Host smart-127594e7-7e8d-40e0-b270-0cc69a37493a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624522463 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.1624522463
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.4263433817
Short name T489
Test name
Test status
Simulation time 440097606 ps
CPU time 0.84 seconds
Started Jun 13 02:32:39 PM PDT 24
Finished Jun 13 02:32:42 PM PDT 24
Peak memory 201944 kb
Host smart-265929da-394d-4f46-a3f2-353ad3211167
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263433817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.4263433817
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.3365723677
Short name T610
Test name
Test status
Simulation time 256800506692 ps
CPU time 166.94 seconds
Started Jun 13 02:32:41 PM PDT 24
Finished Jun 13 02:35:30 PM PDT 24
Peak memory 202272 kb
Host smart-df25a7db-07f5-4716-a479-d6250508569b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365723677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.3365723677
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.187872195
Short name T208
Test name
Test status
Simulation time 166874424047 ps
CPU time 382.11 seconds
Started Jun 13 02:32:41 PM PDT 24
Finished Jun 13 02:39:05 PM PDT 24
Peak memory 202208 kb
Host smart-9ea332f3-71c1-4b46-a92a-8cb84d00b9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187872195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.187872195
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.3940552656
Short name T390
Test name
Test status
Simulation time 484876670772 ps
CPU time 1054.62 seconds
Started Jun 13 02:32:38 PM PDT 24
Finished Jun 13 02:50:14 PM PDT 24
Peak memory 202176 kb
Host smart-7aae8bdc-9500-498c-ae70-771427294ed8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940552656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.3940552656
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.880691027
Short name T140
Test name
Test status
Simulation time 162895536560 ps
CPU time 78.09 seconds
Started Jun 13 02:32:41 PM PDT 24
Finished Jun 13 02:34:01 PM PDT 24
Peak memory 202300 kb
Host smart-4309b2b6-087a-4fdb-a50b-2e87f5704582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880691027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.880691027
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.4015544222
Short name T426
Test name
Test status
Simulation time 328312322796 ps
CPU time 301.41 seconds
Started Jun 13 02:32:39 PM PDT 24
Finished Jun 13 02:37:42 PM PDT 24
Peak memory 202156 kb
Host smart-11679dee-f3ea-4e7e-a46f-f22db7ed787e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015544222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.4015544222
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.140540232
Short name T689
Test name
Test status
Simulation time 347319674625 ps
CPU time 370.21 seconds
Started Jun 13 02:32:43 PM PDT 24
Finished Jun 13 02:38:54 PM PDT 24
Peak memory 202196 kb
Host smart-6a1356d0-b469-4218-adc5-7196841e7875
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140540232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_
wakeup.140540232
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.3251364787
Short name T728
Test name
Test status
Simulation time 419589458923 ps
CPU time 224.63 seconds
Started Jun 13 02:32:41 PM PDT 24
Finished Jun 13 02:36:27 PM PDT 24
Peak memory 202152 kb
Host smart-c6655aea-d5e0-4af2-a323-ff38a5388719
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251364787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.3251364787
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.4274564250
Short name T585
Test name
Test status
Simulation time 97869387788 ps
CPU time 366.37 seconds
Started Jun 13 02:32:38 PM PDT 24
Finished Jun 13 02:38:46 PM PDT 24
Peak memory 202576 kb
Host smart-57da966b-8db0-40e9-8b53-f68690686dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274564250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.4274564250
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.495736296
Short name T386
Test name
Test status
Simulation time 21457436574 ps
CPU time 4.5 seconds
Started Jun 13 02:32:39 PM PDT 24
Finished Jun 13 02:32:45 PM PDT 24
Peak memory 202016 kb
Host smart-7461434d-4bde-4f0d-8d5c-0ceeaed85755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495736296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.495736296
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.3146486530
Short name T402
Test name
Test status
Simulation time 5216741005 ps
CPU time 12.19 seconds
Started Jun 13 02:32:41 PM PDT 24
Finished Jun 13 02:32:54 PM PDT 24
Peak memory 202036 kb
Host smart-e720f02f-ee93-4563-af13-1b5da378bc94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146486530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.3146486530
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.476287713
Short name T522
Test name
Test status
Simulation time 5772186928 ps
CPU time 9.93 seconds
Started Jun 13 02:32:38 PM PDT 24
Finished Jun 13 02:32:50 PM PDT 24
Peak memory 202060 kb
Host smart-d2a1bd28-9d2b-45c7-bb71-e94af983316d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476287713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.476287713
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.2365546806
Short name T275
Test name
Test status
Simulation time 188668221038 ps
CPU time 105.66 seconds
Started Jun 13 02:32:40 PM PDT 24
Finished Jun 13 02:34:28 PM PDT 24
Peak memory 210564 kb
Host smart-cb6f21ce-7740-4b49-97f3-4371aaac29fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365546806 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.2365546806
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.351821958
Short name T540
Test name
Test status
Simulation time 430231392 ps
CPU time 0.86 seconds
Started Jun 13 02:32:48 PM PDT 24
Finished Jun 13 02:32:50 PM PDT 24
Peak memory 201892 kb
Host smart-26f3bc41-5c94-44fc-a723-068eeb4e13bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351821958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.351821958
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.973537249
Short name T207
Test name
Test status
Simulation time 513011330518 ps
CPU time 876.72 seconds
Started Jun 13 02:32:46 PM PDT 24
Finished Jun 13 02:47:24 PM PDT 24
Peak memory 202252 kb
Host smart-7b5eb981-9839-48e4-92f9-c4111ffeb152
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973537249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gati
ng.973537249
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.3045790241
Short name T481
Test name
Test status
Simulation time 171905141527 ps
CPU time 38.61 seconds
Started Jun 13 02:32:46 PM PDT 24
Finished Jun 13 02:33:26 PM PDT 24
Peak memory 202208 kb
Host smart-3daf16f0-7abb-4b2c-b215-52d30a9c4623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045790241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.3045790241
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.3188841470
Short name T510
Test name
Test status
Simulation time 166401633737 ps
CPU time 357.82 seconds
Started Jun 13 02:32:47 PM PDT 24
Finished Jun 13 02:38:46 PM PDT 24
Peak memory 202180 kb
Host smart-8e8de532-80bb-42b2-aa2b-9d311189871b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188841470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.3188841470
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.1493628809
Short name T469
Test name
Test status
Simulation time 495919283053 ps
CPU time 1157.67 seconds
Started Jun 13 02:32:41 PM PDT 24
Finished Jun 13 02:52:00 PM PDT 24
Peak memory 202308 kb
Host smart-2fa643d0-3045-43e2-95f6-5008cb29140c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493628809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.1493628809
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.2150590513
Short name T344
Test name
Test status
Simulation time 497701993595 ps
CPU time 552.65 seconds
Started Jun 13 02:32:40 PM PDT 24
Finished Jun 13 02:41:54 PM PDT 24
Peak memory 202076 kb
Host smart-05a35223-843d-4a34-88d2-70cf4445f33c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150590513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.2150590513
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.99214045
Short name T397
Test name
Test status
Simulation time 403443252022 ps
CPU time 934.62 seconds
Started Jun 13 02:32:47 PM PDT 24
Finished Jun 13 02:48:23 PM PDT 24
Peak memory 202184 kb
Host smart-79eaf0fe-f1f9-4b67-8b02-cf6c53cbeb7e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99214045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.a
dc_ctrl_filters_wakeup_fixed.99214045
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.2294252646
Short name T493
Test name
Test status
Simulation time 139603064566 ps
CPU time 482.32 seconds
Started Jun 13 02:32:48 PM PDT 24
Finished Jun 13 02:40:52 PM PDT 24
Peak memory 202536 kb
Host smart-5a5d644a-5f9f-4c9d-a299-fba50f837ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294252646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.2294252646
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.3859755910
Short name T437
Test name
Test status
Simulation time 33065225999 ps
CPU time 19.74 seconds
Started Jun 13 02:32:45 PM PDT 24
Finished Jun 13 02:33:06 PM PDT 24
Peak memory 202044 kb
Host smart-5ef60c23-928e-41a2-9f29-98ba4cfe6ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859755910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.3859755910
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.2731229426
Short name T742
Test name
Test status
Simulation time 5038457702 ps
CPU time 5.36 seconds
Started Jun 13 02:48:05 PM PDT 24
Finished Jun 13 02:48:23 PM PDT 24
Peak memory 202040 kb
Host smart-e9a18ed8-2f15-4f32-8d31-3043e1c52a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731229426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.2731229426
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.988112351
Short name T450
Test name
Test status
Simulation time 5960336661 ps
CPU time 3.62 seconds
Started Jun 13 02:32:41 PM PDT 24
Finished Jun 13 02:32:47 PM PDT 24
Peak memory 202016 kb
Host smart-90f8d5ad-e122-4446-b2d0-738cf26c8b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988112351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.988112351
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.837351518
Short name T602
Test name
Test status
Simulation time 506208572709 ps
CPU time 213.14 seconds
Started Jun 13 02:32:47 PM PDT 24
Finished Jun 13 02:36:21 PM PDT 24
Peak memory 202276 kb
Host smart-d1266a3b-e5ac-4633-ae56-08904b496524
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837351518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all.
837351518
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.2248156613
Short name T680
Test name
Test status
Simulation time 455938305476 ps
CPU time 195.41 seconds
Started Jun 13 02:32:47 PM PDT 24
Finished Jun 13 02:36:04 PM PDT 24
Peak memory 210804 kb
Host smart-981ca7a6-00bb-48a3-b853-1db8786ebefe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248156613 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.2248156613
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.3043584588
Short name T4
Test name
Test status
Simulation time 446557185 ps
CPU time 0.88 seconds
Started Jun 13 02:33:01 PM PDT 24
Finished Jun 13 02:33:04 PM PDT 24
Peak memory 201912 kb
Host smart-3e3256df-a706-4667-b04d-8f1a13333f85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043584588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.3043584588
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.3506776215
Short name T28
Test name
Test status
Simulation time 338486136402 ps
CPU time 372.43 seconds
Started Jun 13 02:32:51 PM PDT 24
Finished Jun 13 02:39:05 PM PDT 24
Peak memory 202284 kb
Host smart-44c07a06-69f4-477b-ae09-cb888bea1cfa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506776215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.3506776215
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.1824562051
Short name T635
Test name
Test status
Simulation time 179466496435 ps
CPU time 101.95 seconds
Started Jun 13 02:32:51 PM PDT 24
Finished Jun 13 02:34:34 PM PDT 24
Peak memory 202264 kb
Host smart-5031af94-412c-46f0-8e79-9c21406d9e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824562051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.1824562051
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.2693948883
Short name T771
Test name
Test status
Simulation time 487975163858 ps
CPU time 280.8 seconds
Started Jun 13 02:32:48 PM PDT 24
Finished Jun 13 02:37:30 PM PDT 24
Peak memory 202396 kb
Host smart-d3bc60f6-5135-4d8b-9dc2-7f694454d363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693948883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.2693948883
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.1055807150
Short name T586
Test name
Test status
Simulation time 493352284152 ps
CPU time 326.98 seconds
Started Jun 13 02:32:48 PM PDT 24
Finished Jun 13 02:38:16 PM PDT 24
Peak memory 202340 kb
Host smart-aefa312e-4183-4ce5-8fc5-65afb5c91815
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055807150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.1055807150
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.3806226791
Short name T413
Test name
Test status
Simulation time 161128018364 ps
CPU time 56.09 seconds
Started Jun 13 02:32:46 PM PDT 24
Finished Jun 13 02:33:44 PM PDT 24
Peak memory 202208 kb
Host smart-30c73f24-989b-4b4f-ab73-bb167778b216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806226791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.3806226791
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.2622344497
Short name T560
Test name
Test status
Simulation time 492274121733 ps
CPU time 375.99 seconds
Started Jun 13 02:32:46 PM PDT 24
Finished Jun 13 02:39:03 PM PDT 24
Peak memory 202236 kb
Host smart-e968db5d-1a67-4e45-ba3b-c0a5c3511f9e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622344497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.2622344497
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.4118091564
Short name T253
Test name
Test status
Simulation time 380148104156 ps
CPU time 167.19 seconds
Started Jun 13 02:32:53 PM PDT 24
Finished Jun 13 02:35:41 PM PDT 24
Peak memory 202240 kb
Host smart-9bedb7a2-a989-4e34-8688-0b2fa5f61167
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118091564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.4118091564
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.3223569189
Short name T754
Test name
Test status
Simulation time 610655793204 ps
CPU time 307.44 seconds
Started Jun 13 02:32:53 PM PDT 24
Finished Jun 13 02:38:01 PM PDT 24
Peak memory 202144 kb
Host smart-da1536d6-2c17-4965-a676-659887b8a741
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223569189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.3223569189
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.4100701822
Short name T50
Test name
Test status
Simulation time 104135666432 ps
CPU time 379.79 seconds
Started Jun 13 02:32:52 PM PDT 24
Finished Jun 13 02:39:13 PM PDT 24
Peak memory 202520 kb
Host smart-97f8d7ba-640b-400f-aa6a-55f5cd7cd93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100701822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.4100701822
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.3122942308
Short name T156
Test name
Test status
Simulation time 24033195794 ps
CPU time 15.65 seconds
Started Jun 13 02:32:51 PM PDT 24
Finished Jun 13 02:33:07 PM PDT 24
Peak memory 202032 kb
Host smart-6be59e47-b59a-438f-b2f6-1cad4557c957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122942308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.3122942308
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.2225518759
Short name T553
Test name
Test status
Simulation time 5136389751 ps
CPU time 3.57 seconds
Started Jun 13 02:32:52 PM PDT 24
Finished Jun 13 02:32:56 PM PDT 24
Peak memory 202000 kb
Host smart-d9790405-421b-4d74-82f8-6a41731901f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225518759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.2225518759
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.709857961
Short name T577
Test name
Test status
Simulation time 5689231576 ps
CPU time 7.45 seconds
Started Jun 13 02:32:45 PM PDT 24
Finished Jun 13 02:32:54 PM PDT 24
Peak memory 202052 kb
Host smart-b78092ac-9104-42fc-a5da-d364e7dbc805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709857961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.709857961
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.3049303213
Short name T73
Test name
Test status
Simulation time 312332982 ps
CPU time 0.82 seconds
Started Jun 13 02:32:58 PM PDT 24
Finished Jun 13 02:33:00 PM PDT 24
Peak memory 201916 kb
Host smart-0004e5fe-3b11-4c8a-8de9-8c46f48cbb38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049303213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.3049303213
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.34451992
Short name T107
Test name
Test status
Simulation time 488517050359 ps
CPU time 204.1 seconds
Started Jun 13 02:32:52 PM PDT 24
Finished Jun 13 02:36:17 PM PDT 24
Peak memory 202200 kb
Host smart-2ac18476-c194-4213-aee8-fe6812d97026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34451992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.34451992
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.1966886918
Short name T630
Test name
Test status
Simulation time 326582682186 ps
CPU time 690.3 seconds
Started Jun 13 02:33:05 PM PDT 24
Finished Jun 13 02:44:38 PM PDT 24
Peak memory 202248 kb
Host smart-b03ce54e-17f7-4a9b-9307-04fc4d1d2627
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966886918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.1966886918
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.3566563373
Short name T316
Test name
Test status
Simulation time 332679221902 ps
CPU time 755.62 seconds
Started Jun 13 02:33:03 PM PDT 24
Finished Jun 13 02:45:40 PM PDT 24
Peak memory 202264 kb
Host smart-e91878b1-3cfe-4e99-89cf-ed14e5d28dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566563373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.3566563373
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.3851941908
Short name T660
Test name
Test status
Simulation time 484658295245 ps
CPU time 282.56 seconds
Started Jun 13 02:37:30 PM PDT 24
Finished Jun 13 02:42:14 PM PDT 24
Peak memory 202252 kb
Host smart-e393c175-5676-495c-bef4-2ef7bdcb4096
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851941908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.3851941908
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.4227184893
Short name T190
Test name
Test status
Simulation time 275682948142 ps
CPU time 613.71 seconds
Started Jun 13 02:33:06 PM PDT 24
Finished Jun 13 02:43:22 PM PDT 24
Peak memory 202276 kb
Host smart-d2897b52-bcea-412d-99ef-206514426f28
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227184893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.4227184893
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.3301918131
Short name T678
Test name
Test status
Simulation time 592016441114 ps
CPU time 501.51 seconds
Started Jun 13 02:32:53 PM PDT 24
Finished Jun 13 02:41:15 PM PDT 24
Peak memory 202208 kb
Host smart-9725b6dc-9a2d-44b3-9422-3aa00e5aed74
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301918131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.3301918131
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.3746797003
Short name T42
Test name
Test status
Simulation time 94324475424 ps
CPU time 350.95 seconds
Started Jun 13 02:32:53 PM PDT 24
Finished Jun 13 02:38:45 PM PDT 24
Peak memory 202604 kb
Host smart-ebd4cc57-0385-4eef-939a-3487e0b15582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746797003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.3746797003
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.1310350726
Short name T496
Test name
Test status
Simulation time 30093174161 ps
CPU time 67.75 seconds
Started Jun 13 02:33:01 PM PDT 24
Finished Jun 13 02:34:10 PM PDT 24
Peak memory 202044 kb
Host smart-8f88dabb-3be0-4d24-8b8e-88a0ae02a0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310350726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.1310350726
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.411952073
Short name T567
Test name
Test status
Simulation time 4480382688 ps
CPU time 3.6 seconds
Started Jun 13 02:32:52 PM PDT 24
Finished Jun 13 02:32:56 PM PDT 24
Peak memory 202040 kb
Host smart-79c34f93-0b72-476c-b4be-17e62164b88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411952073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.411952073
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.3455756209
Short name T418
Test name
Test status
Simulation time 5770253428 ps
CPU time 14.45 seconds
Started Jun 13 02:32:52 PM PDT 24
Finished Jun 13 02:33:08 PM PDT 24
Peak memory 202012 kb
Host smart-2f444d16-f517-4e99-89e1-53f63ec4f5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455756209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.3455756209
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.4196915867
Short name T46
Test name
Test status
Simulation time 237859234789 ps
CPU time 774.81 seconds
Started Jun 13 02:32:59 PM PDT 24
Finished Jun 13 02:45:55 PM PDT 24
Peak memory 202520 kb
Host smart-6c1f06bd-aebe-45e2-a7d0-c0717aebd2b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196915867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.4196915867
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.2571415970
Short name T502
Test name
Test status
Simulation time 527821782 ps
CPU time 1.22 seconds
Started Jun 13 02:31:36 PM PDT 24
Finished Jun 13 02:31:43 PM PDT 24
Peak memory 201912 kb
Host smart-e9d80ec3-2ee5-402b-9002-a73d724986a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571415970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.2571415970
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.930828582
Short name T223
Test name
Test status
Simulation time 380167357338 ps
CPU time 825.3 seconds
Started Jun 13 02:32:02 PM PDT 24
Finished Jun 13 02:45:53 PM PDT 24
Peak memory 202100 kb
Host smart-1d58569a-3852-474b-9d6b-b7ce65a283a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930828582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.930828582
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.3351367419
Short name T149
Test name
Test status
Simulation time 333945630337 ps
CPU time 187.77 seconds
Started Jun 13 02:31:35 PM PDT 24
Finished Jun 13 02:34:49 PM PDT 24
Peak memory 202232 kb
Host smart-4aaa60c4-a499-4db2-b314-4b036b6b68d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351367419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.3351367419
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.3067089028
Short name T407
Test name
Test status
Simulation time 499286500953 ps
CPU time 1087.63 seconds
Started Jun 13 02:31:26 PM PDT 24
Finished Jun 13 02:49:39 PM PDT 24
Peak memory 202244 kb
Host smart-47459045-6a0d-405e-aa8f-1a9a01157b88
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067089028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.3067089028
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.3312389838
Short name T500
Test name
Test status
Simulation time 327327923849 ps
CPU time 82.99 seconds
Started Jun 13 02:32:00 PM PDT 24
Finished Jun 13 02:33:28 PM PDT 24
Peak memory 202124 kb
Host smart-98f9449c-22d2-4c33-befc-3f873b35cd9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312389838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.3312389838
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.2560489692
Short name T708
Test name
Test status
Simulation time 326486182439 ps
CPU time 138.92 seconds
Started Jun 13 02:31:29 PM PDT 24
Finished Jun 13 02:33:59 PM PDT 24
Peak memory 202156 kb
Host smart-bf41247e-5d90-4f84-b9f9-b778039815f8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560489692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.2560489692
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.3661997498
Short name T270
Test name
Test status
Simulation time 508789589446 ps
CPU time 427.91 seconds
Started Jun 13 02:31:31 PM PDT 24
Finished Jun 13 02:38:44 PM PDT 24
Peak memory 202276 kb
Host smart-4df02f19-9966-4811-ad70-debc585297e4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661997498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.3661997498
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.1054652369
Short name T367
Test name
Test status
Simulation time 599829758720 ps
CPU time 694.98 seconds
Started Jun 13 02:31:31 PM PDT 24
Finished Jun 13 02:43:12 PM PDT 24
Peak memory 202180 kb
Host smart-c6aa9ab3-8296-4697-a82e-123ff86829fc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054652369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.1054652369
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.1430273232
Short name T601
Test name
Test status
Simulation time 101319737802 ps
CPU time 573.05 seconds
Started Jun 13 02:31:28 PM PDT 24
Finished Jun 13 02:41:07 PM PDT 24
Peak memory 202552 kb
Host smart-c789f94f-9650-442e-a3a7-1a19e336154c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430273232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.1430273232
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.629359497
Short name T483
Test name
Test status
Simulation time 33722929435 ps
CPU time 76.36 seconds
Started Jun 13 02:31:42 PM PDT 24
Finished Jun 13 02:33:04 PM PDT 24
Peak memory 202052 kb
Host smart-990339bf-c251-4210-8ccc-79ad143b9cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629359497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.629359497
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.2076141346
Short name T440
Test name
Test status
Simulation time 3727301529 ps
CPU time 8.81 seconds
Started Jun 13 02:31:32 PM PDT 24
Finished Jun 13 02:31:46 PM PDT 24
Peak memory 202012 kb
Host smart-ee29944a-a3e0-475c-af38-229731706dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076141346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.2076141346
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.2277134007
Short name T74
Test name
Test status
Simulation time 3803809847 ps
CPU time 9.04 seconds
Started Jun 13 02:31:29 PM PDT 24
Finished Jun 13 02:31:44 PM PDT 24
Peak memory 217684 kb
Host smart-eeaa5e47-893e-4291-9688-b8fa1020917e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277134007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.2277134007
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.1164785184
Short name T626
Test name
Test status
Simulation time 5909753671 ps
CPU time 13.68 seconds
Started Jun 13 02:31:26 PM PDT 24
Finished Jun 13 02:31:45 PM PDT 24
Peak memory 202004 kb
Host smart-c25d0314-4499-41e0-9796-d8431a95a27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164785184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.1164785184
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.522449417
Short name T726
Test name
Test status
Simulation time 179143806268 ps
CPU time 391.97 seconds
Started Jun 13 02:31:27 PM PDT 24
Finished Jun 13 02:38:05 PM PDT 24
Peak memory 202268 kb
Host smart-fd3e6e14-ba6b-48bd-84f7-e0a1ca945648
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522449417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.522449417
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.2687417801
Short name T38
Test name
Test status
Simulation time 114444807649 ps
CPU time 191.43 seconds
Started Jun 13 02:31:31 PM PDT 24
Finished Jun 13 02:34:48 PM PDT 24
Peak memory 210908 kb
Host smart-834064d3-7f27-4d99-b957-6baa43b800eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687417801 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.2687417801
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.2602370178
Short name T362
Test name
Test status
Simulation time 387844426 ps
CPU time 1.55 seconds
Started Jun 13 02:33:06 PM PDT 24
Finished Jun 13 02:33:10 PM PDT 24
Peak memory 201928 kb
Host smart-72869a75-fd7a-4e3e-b247-0f58510281e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602370178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.2602370178
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.2368469453
Short name T762
Test name
Test status
Simulation time 164931220755 ps
CPU time 167.1 seconds
Started Jun 13 02:32:58 PM PDT 24
Finished Jun 13 02:35:47 PM PDT 24
Peak memory 202112 kb
Host smart-6e4ce6b8-9309-4f53-b1d6-af62f3c36e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368469453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.2368469453
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.3867417836
Short name T770
Test name
Test status
Simulation time 327961832782 ps
CPU time 681.89 seconds
Started Jun 13 02:32:58 PM PDT 24
Finished Jun 13 02:44:22 PM PDT 24
Peak memory 202208 kb
Host smart-3d8d00e8-bda2-4be9-8035-e4ffc32ff9d0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867417836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.3867417836
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.4278369254
Short name T232
Test name
Test status
Simulation time 503263273423 ps
CPU time 1182.92 seconds
Started Jun 13 02:32:57 PM PDT 24
Finished Jun 13 02:52:41 PM PDT 24
Peak memory 202204 kb
Host smart-01f19002-5d7c-48db-b2a8-a04e007cfddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278369254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.4278369254
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.1912408109
Short name T411
Test name
Test status
Simulation time 166053727246 ps
CPU time 380.86 seconds
Started Jun 13 02:32:58 PM PDT 24
Finished Jun 13 02:39:21 PM PDT 24
Peak memory 202184 kb
Host smart-e8556dfb-c06f-499b-addb-88850ffbf45f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912408109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.1912408109
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.3090230845
Short name T623
Test name
Test status
Simulation time 523396404493 ps
CPU time 849.39 seconds
Started Jun 13 02:32:58 PM PDT 24
Finished Jun 13 02:47:09 PM PDT 24
Peak memory 202276 kb
Host smart-d9390245-c0ed-4e6e-9d92-4602bcab4f6f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090230845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.3090230845
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.3790027860
Short name T381
Test name
Test status
Simulation time 203038850320 ps
CPU time 122.32 seconds
Started Jun 13 02:33:06 PM PDT 24
Finished Jun 13 02:35:11 PM PDT 24
Peak memory 202188 kb
Host smart-bceb3606-346a-4f80-8b08-8f85d9b5f1ae
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790027860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.3790027860
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.2169725759
Short name T43
Test name
Test status
Simulation time 89764481141 ps
CPU time 463.11 seconds
Started Jun 13 02:32:59 PM PDT 24
Finished Jun 13 02:40:44 PM PDT 24
Peak memory 202564 kb
Host smart-3b316322-9594-4bdc-8e44-95d1f0c098e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169725759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.2169725759
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.2411769283
Short name T786
Test name
Test status
Simulation time 42780522252 ps
CPU time 7.71 seconds
Started Jun 13 02:32:58 PM PDT 24
Finished Jun 13 02:33:07 PM PDT 24
Peak memory 202044 kb
Host smart-fc9c7280-28c4-405f-bd67-ccf91454798d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411769283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.2411769283
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.1775231467
Short name T439
Test name
Test status
Simulation time 3879300449 ps
CPU time 2.99 seconds
Started Jun 13 02:32:58 PM PDT 24
Finished Jun 13 02:33:03 PM PDT 24
Peak memory 202040 kb
Host smart-f2d35df5-6008-44ed-ab41-027924fc7008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775231467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.1775231467
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.3354529941
Short name T533
Test name
Test status
Simulation time 5745503727 ps
CPU time 13.65 seconds
Started Jun 13 02:32:58 PM PDT 24
Finished Jun 13 02:33:14 PM PDT 24
Peak memory 202052 kb
Host smart-8525b49e-4e1a-4567-9590-900c737e90e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354529941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.3354529941
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.1160582199
Short name T429
Test name
Test status
Simulation time 449557931 ps
CPU time 0.88 seconds
Started Jun 13 02:33:11 PM PDT 24
Finished Jun 13 02:33:14 PM PDT 24
Peak memory 201888 kb
Host smart-02434266-6fed-407e-a33f-d900b96626a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160582199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.1160582199
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.3703039622
Short name T698
Test name
Test status
Simulation time 400470021635 ps
CPU time 512.95 seconds
Started Jun 13 02:33:06 PM PDT 24
Finished Jun 13 02:41:41 PM PDT 24
Peak memory 202212 kb
Host smart-f3adb024-aaa7-4a56-905f-b29a2224c8b8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703039622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.3703039622
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.642076357
Short name T145
Test name
Test status
Simulation time 545441469540 ps
CPU time 329.82 seconds
Started Jun 13 02:45:15 PM PDT 24
Finished Jun 13 02:51:00 PM PDT 24
Peak memory 202236 kb
Host smart-d8e8963e-9dd1-4897-aaa9-5ae727f5b75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642076357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.642076357
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.209530252
Short name T298
Test name
Test status
Simulation time 165202101603 ps
CPU time 39.33 seconds
Started Jun 13 02:33:06 PM PDT 24
Finished Jun 13 02:33:47 PM PDT 24
Peak memory 202392 kb
Host smart-bc1139a7-33d5-4a13-9464-b4162f179acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209530252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.209530252
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.399361480
Short name T605
Test name
Test status
Simulation time 490056752451 ps
CPU time 285.7 seconds
Started Jun 13 02:33:05 PM PDT 24
Finished Jun 13 02:37:52 PM PDT 24
Peak memory 202184 kb
Host smart-fe908cfe-78a0-4296-8b5a-da12fa946b87
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=399361480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrup
t_fixed.399361480
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.2912331222
Short name T287
Test name
Test status
Simulation time 323896090445 ps
CPU time 730.57 seconds
Started Jun 13 02:33:06 PM PDT 24
Finished Jun 13 02:45:19 PM PDT 24
Peak memory 202228 kb
Host smart-deb95cd6-fbc4-430d-807d-616a48dd379f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912331222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.2912331222
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.2664488546
Short name T383
Test name
Test status
Simulation time 330782137691 ps
CPU time 188.44 seconds
Started Jun 13 02:33:05 PM PDT 24
Finished Jun 13 02:36:16 PM PDT 24
Peak memory 202172 kb
Host smart-be868196-5e4e-493f-9797-33aad2ace7bd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664488546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.2664488546
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.2526786533
Short name T486
Test name
Test status
Simulation time 395870382972 ps
CPU time 889.33 seconds
Started Jun 13 02:33:05 PM PDT 24
Finished Jun 13 02:47:57 PM PDT 24
Peak memory 202244 kb
Host smart-ce6afb25-3fae-46f3-b1c1-937bc323d714
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526786533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.2526786533
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.2782837102
Short name T179
Test name
Test status
Simulation time 99037144159 ps
CPU time 518.59 seconds
Started Jun 13 02:33:05 PM PDT 24
Finished Jun 13 02:41:45 PM PDT 24
Peak memory 202524 kb
Host smart-4929bc25-e382-4a2d-a28b-c138a500e614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782837102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.2782837102
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.2756024726
Short name T340
Test name
Test status
Simulation time 31561384053 ps
CPU time 64.73 seconds
Started Jun 13 02:33:05 PM PDT 24
Finished Jun 13 02:34:12 PM PDT 24
Peak memory 202040 kb
Host smart-4807325e-d6c3-45f9-b45f-e1b88707cbd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756024726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.2756024726
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.3391123082
Short name T625
Test name
Test status
Simulation time 3141360063 ps
CPU time 2.52 seconds
Started Jun 13 02:33:04 PM PDT 24
Finished Jun 13 02:33:07 PM PDT 24
Peak memory 202052 kb
Host smart-dfe94933-ca95-4429-b888-f9c15ef06e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391123082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.3391123082
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.1874055381
Short name T503
Test name
Test status
Simulation time 5580820967 ps
CPU time 5.82 seconds
Started Jun 13 02:33:04 PM PDT 24
Finished Jun 13 02:33:11 PM PDT 24
Peak memory 202016 kb
Host smart-d5b786e6-c06d-41ae-a99d-8d8f03538f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874055381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.1874055381
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.2586861266
Short name T248
Test name
Test status
Simulation time 1098485967749 ps
CPU time 505.17 seconds
Started Jun 13 02:33:12 PM PDT 24
Finished Jun 13 02:41:39 PM PDT 24
Peak memory 210712 kb
Host smart-f45aa808-9598-4f2b-a58d-f9495ef079b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586861266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.2586861266
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.2606384481
Short name T48
Test name
Test status
Simulation time 161004071596 ps
CPU time 148.67 seconds
Started Jun 13 02:33:05 PM PDT 24
Finished Jun 13 02:35:36 PM PDT 24
Peak memory 211824 kb
Host smart-274229ba-1a4b-4f05-bca6-282e6ef150b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606384481 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.2606384481
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.3653723620
Short name T5
Test name
Test status
Simulation time 326471993 ps
CPU time 0.82 seconds
Started Jun 13 02:33:18 PM PDT 24
Finished Jun 13 02:33:20 PM PDT 24
Peak memory 201908 kb
Host smart-79d96f58-0dcd-4b02-885d-006415fbc6e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653723620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.3653723620
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.167688600
Short name T141
Test name
Test status
Simulation time 347117347050 ps
CPU time 46.38 seconds
Started Jun 13 02:33:11 PM PDT 24
Finished Jun 13 02:33:59 PM PDT 24
Peak memory 202208 kb
Host smart-b60de12a-1fe9-4049-9f94-baf8ec842d1f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167688600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gati
ng.167688600
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.2700622629
Short name T201
Test name
Test status
Simulation time 323942201442 ps
CPU time 192.82 seconds
Started Jun 13 02:33:12 PM PDT 24
Finished Jun 13 02:36:26 PM PDT 24
Peak memory 202288 kb
Host smart-a5933e9d-ccf5-42d0-ae3c-aef1c146b74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700622629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.2700622629
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.958179948
Short name T157
Test name
Test status
Simulation time 329687837255 ps
CPU time 401.78 seconds
Started Jun 13 02:33:11 PM PDT 24
Finished Jun 13 02:39:55 PM PDT 24
Peak memory 202148 kb
Host smart-02e2504a-cedc-4294-9e2f-41b99aeaf254
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=958179948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrup
t_fixed.958179948
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.1127482414
Short name T286
Test name
Test status
Simulation time 327787096526 ps
CPU time 723.37 seconds
Started Jun 13 02:33:12 PM PDT 24
Finished Jun 13 02:45:16 PM PDT 24
Peak memory 202172 kb
Host smart-792f16c7-9bc1-44fd-85fe-08716f349363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127482414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.1127482414
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.1916295409
Short name T639
Test name
Test status
Simulation time 169065691983 ps
CPU time 107.98 seconds
Started Jun 13 02:33:13 PM PDT 24
Finished Jun 13 02:35:02 PM PDT 24
Peak memory 202188 kb
Host smart-f1df410e-5ac1-4334-a58d-797d3e2245ad
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916295409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.1916295409
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.1916924199
Short name T138
Test name
Test status
Simulation time 194020145920 ps
CPU time 115.35 seconds
Started Jun 13 02:33:18 PM PDT 24
Finished Jun 13 02:35:15 PM PDT 24
Peak memory 202192 kb
Host smart-d577288a-7be3-41f3-9f6b-f32981fbf597
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916924199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.1916924199
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.2838775793
Short name T670
Test name
Test status
Simulation time 31785960470 ps
CPU time 17.61 seconds
Started Jun 13 02:33:10 PM PDT 24
Finished Jun 13 02:33:29 PM PDT 24
Peak memory 202044 kb
Host smart-402fc5c1-1812-4a5b-bff5-f9c07526bf4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838775793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.2838775793
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.2139865064
Short name T497
Test name
Test status
Simulation time 3906591910 ps
CPU time 1.49 seconds
Started Jun 13 02:33:11 PM PDT 24
Finished Jun 13 02:33:14 PM PDT 24
Peak memory 202052 kb
Host smart-38f56d76-440f-4b69-9d46-6389dad57263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139865064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.2139865064
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.1467474377
Short name T349
Test name
Test status
Simulation time 5858883654 ps
CPU time 12.55 seconds
Started Jun 13 02:33:10 PM PDT 24
Finished Jun 13 02:33:24 PM PDT 24
Peak memory 202048 kb
Host smart-862d40b7-780f-4cd7-9bae-3734f9396b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467474377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.1467474377
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.58169746
Short name T279
Test name
Test status
Simulation time 539818451134 ps
CPU time 1253.85 seconds
Started Jun 13 02:33:18 PM PDT 24
Finished Jun 13 02:54:14 PM PDT 24
Peak memory 202212 kb
Host smart-337adf83-65fb-4441-ab73-a4cc5c6cb0f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58169746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all.58169746
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.2521922623
Short name T37
Test name
Test status
Simulation time 76248226727 ps
CPU time 141.13 seconds
Started Jun 13 02:33:17 PM PDT 24
Finished Jun 13 02:35:39 PM PDT 24
Peak memory 210856 kb
Host smart-4c9e4486-de17-40fe-8f5f-e5c172634fa9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521922623 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.2521922623
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.450010527
Short name T472
Test name
Test status
Simulation time 444905926 ps
CPU time 0.86 seconds
Started Jun 13 02:33:18 PM PDT 24
Finished Jun 13 02:33:21 PM PDT 24
Peak memory 201880 kb
Host smart-541eda38-92e4-488b-94a7-bcde106fc043
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450010527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.450010527
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.3723472773
Short name T14
Test name
Test status
Simulation time 518637250238 ps
CPU time 479.5 seconds
Started Jun 13 02:33:17 PM PDT 24
Finished Jun 13 02:41:18 PM PDT 24
Peak memory 202208 kb
Host smart-37d6363a-2411-4029-8107-2608169a062d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723472773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.3723472773
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.428693552
Short name T283
Test name
Test status
Simulation time 205494728943 ps
CPU time 107.94 seconds
Started Jun 13 02:33:15 PM PDT 24
Finished Jun 13 02:35:05 PM PDT 24
Peak memory 202176 kb
Host smart-02f868ea-b13d-454b-b079-357ddc37cd52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428693552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.428693552
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.1927855719
Short name T106
Test name
Test status
Simulation time 487219090229 ps
CPU time 588 seconds
Started Jun 13 02:44:26 PM PDT 24
Finished Jun 13 02:54:22 PM PDT 24
Peak memory 202236 kb
Host smart-707439cb-5bf4-47c9-92f8-a254826daf84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927855719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.1927855719
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.3512980646
Short name T7
Test name
Test status
Simulation time 320302196029 ps
CPU time 101.8 seconds
Started Jun 13 02:33:17 PM PDT 24
Finished Jun 13 02:35:00 PM PDT 24
Peak memory 202188 kb
Host smart-e31089c5-c6c0-43e7-846d-c068b655f3e2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512980646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.3512980646
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.697500285
Short name T590
Test name
Test status
Simulation time 329035554393 ps
CPU time 349.81 seconds
Started Jun 13 02:48:04 PM PDT 24
Finished Jun 13 02:54:06 PM PDT 24
Peak memory 202256 kb
Host smart-f486ffca-f98d-4fd4-8229-22fe0a7470ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697500285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.697500285
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.573469277
Short name T552
Test name
Test status
Simulation time 160578524656 ps
CPU time 181.49 seconds
Started Jun 13 02:33:17 PM PDT 24
Finished Jun 13 02:36:20 PM PDT 24
Peak memory 202208 kb
Host smart-85e5989a-1e85-463c-bc3f-3aaa5fb662fd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=573469277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fixe
d.573469277
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.3678631584
Short name T704
Test name
Test status
Simulation time 361601196682 ps
CPU time 284.4 seconds
Started Jun 13 02:33:22 PM PDT 24
Finished Jun 13 02:38:07 PM PDT 24
Peak memory 202196 kb
Host smart-b0afa794-1a93-46d0-8144-63d931fae4b9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678631584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.3678631584
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.110267592
Short name T139
Test name
Test status
Simulation time 395948922805 ps
CPU time 212.26 seconds
Started Jun 13 02:36:37 PM PDT 24
Finished Jun 13 02:40:10 PM PDT 24
Peak memory 202212 kb
Host smart-fa0d456f-d1ee-4ab0-89f0-26ca6d9e2435
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110267592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
adc_ctrl_filters_wakeup_fixed.110267592
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.471847738
Short name T371
Test name
Test status
Simulation time 126344436448 ps
CPU time 445.53 seconds
Started Jun 13 02:33:17 PM PDT 24
Finished Jun 13 02:40:44 PM PDT 24
Peak memory 202536 kb
Host smart-b841c531-91c9-48ad-be14-675b0a3ff3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471847738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.471847738
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.1100706697
Short name T581
Test name
Test status
Simulation time 27547744238 ps
CPU time 67.54 seconds
Started Jun 13 02:33:18 PM PDT 24
Finished Jun 13 02:34:27 PM PDT 24
Peak memory 202056 kb
Host smart-41779bfe-0373-4773-91e9-6e929d45b6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100706697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.1100706697
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.3616294111
Short name T335
Test name
Test status
Simulation time 3869039520 ps
CPU time 8.86 seconds
Started Jun 13 02:33:15 PM PDT 24
Finished Jun 13 02:33:26 PM PDT 24
Peak memory 202052 kb
Host smart-873bb0a7-45bb-4da2-951d-0b091a81f2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616294111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.3616294111
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.3673768558
Short name T757
Test name
Test status
Simulation time 5727283484 ps
CPU time 13.52 seconds
Started Jun 13 02:33:19 PM PDT 24
Finished Jun 13 02:33:34 PM PDT 24
Peak memory 202028 kb
Host smart-3fac8c55-0fe2-49ae-9c22-dfc409d2fd5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673768558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.3673768558
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.158081920
Short name T442
Test name
Test status
Simulation time 1057347746755 ps
CPU time 2754.06 seconds
Started Jun 13 02:33:20 PM PDT 24
Finished Jun 13 03:19:16 PM PDT 24
Peak memory 213568 kb
Host smart-4a03c832-76a8-4bd1-9d80-a669641c33dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158081920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all.
158081920
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.853781408
Short name T303
Test name
Test status
Simulation time 20840654665 ps
CPU time 49.97 seconds
Started Jun 13 02:33:17 PM PDT 24
Finished Jun 13 02:34:08 PM PDT 24
Peak memory 210884 kb
Host smart-d5ba1889-71d3-4348-bad6-690d96c7427d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853781408 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.853781408
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.3587724282
Short name T528
Test name
Test status
Simulation time 382543611 ps
CPU time 1.45 seconds
Started Jun 13 02:33:29 PM PDT 24
Finished Jun 13 02:33:32 PM PDT 24
Peak memory 201880 kb
Host smart-b446a8de-5159-4cf1-8b93-787bd0b0761b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587724282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.3587724282
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.3895719985
Short name T262
Test name
Test status
Simulation time 162128591258 ps
CPU time 114.78 seconds
Started Jun 13 02:33:21 PM PDT 24
Finished Jun 13 02:35:17 PM PDT 24
Peak memory 202212 kb
Host smart-57137eee-aea5-4483-8817-905eaee9c214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895719985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.3895719985
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.2223360245
Short name T385
Test name
Test status
Simulation time 486235780641 ps
CPU time 309.1 seconds
Started Jun 13 02:33:24 PM PDT 24
Finished Jun 13 02:38:34 PM PDT 24
Peak memory 202212 kb
Host smart-8c54dcf4-9471-485a-b01d-25b6673d2a94
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223360245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.2223360245
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.1635344130
Short name T297
Test name
Test status
Simulation time 323168851593 ps
CPU time 198.31 seconds
Started Jun 13 02:33:21 PM PDT 24
Finished Jun 13 02:36:40 PM PDT 24
Peak memory 202280 kb
Host smart-527d3145-2155-4436-a4f8-7775d9f0be85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635344130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.1635344130
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.1178814056
Short name T78
Test name
Test status
Simulation time 325455488290 ps
CPU time 181.39 seconds
Started Jun 13 02:48:16 PM PDT 24
Finished Jun 13 02:51:33 PM PDT 24
Peak memory 202184 kb
Host smart-132334db-a623-49e4-895a-ccc0f86848d0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178814056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.1178814056
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.2444406626
Short name T121
Test name
Test status
Simulation time 210648222654 ps
CPU time 115.5 seconds
Started Jun 13 02:33:27 PM PDT 24
Finished Jun 13 02:35:23 PM PDT 24
Peak memory 202224 kb
Host smart-40ffc36a-d4da-437e-a20f-839e2c2214da
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444406626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.2444406626
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.3043323591
Short name T404
Test name
Test status
Simulation time 605834180314 ps
CPU time 1354.11 seconds
Started Jun 13 02:33:21 PM PDT 24
Finished Jun 13 02:55:56 PM PDT 24
Peak memory 202184 kb
Host smart-26389815-2b60-4f1e-b569-df47aae642dc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043323591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.3043323591
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.1832835441
Short name T492
Test name
Test status
Simulation time 104191710077 ps
CPU time 327.65 seconds
Started Jun 13 02:33:28 PM PDT 24
Finished Jun 13 02:38:57 PM PDT 24
Peak memory 202536 kb
Host smart-67ef87a7-fecb-49ef-8be5-30f191c8f251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832835441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.1832835441
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.3659986967
Short name T673
Test name
Test status
Simulation time 31539678683 ps
CPU time 37.11 seconds
Started Jun 13 02:33:29 PM PDT 24
Finished Jun 13 02:34:07 PM PDT 24
Peak memory 202040 kb
Host smart-846f136a-00d8-4598-9754-39d6aef23ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659986967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.3659986967
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.3987159340
Short name T379
Test name
Test status
Simulation time 4375831477 ps
CPU time 9.53 seconds
Started Jun 13 02:33:33 PM PDT 24
Finished Jun 13 02:33:44 PM PDT 24
Peak memory 202020 kb
Host smart-87c8d25f-1fe7-42af-9ebd-da91ebda6a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987159340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.3987159340
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.137784923
Short name T519
Test name
Test status
Simulation time 5903140417 ps
CPU time 15.09 seconds
Started Jun 13 02:33:19 PM PDT 24
Finished Jun 13 02:33:35 PM PDT 24
Peak memory 202048 kb
Host smart-d3ffbd86-3fcd-4bb1-bb99-8d0decf87be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137784923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.137784923
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.2298234275
Short name T637
Test name
Test status
Simulation time 89514011296 ps
CPU time 169.66 seconds
Started Jun 13 02:33:28 PM PDT 24
Finished Jun 13 02:36:20 PM PDT 24
Peak memory 218332 kb
Host smart-a0ddec3a-1b08-4ebc-bbcd-f96caff6e618
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298234275 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.2298234275
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.687017448
Short name T417
Test name
Test status
Simulation time 491146132 ps
CPU time 0.94 seconds
Started Jun 13 02:33:34 PM PDT 24
Finished Jun 13 02:33:38 PM PDT 24
Peak memory 201920 kb
Host smart-2ecfe11d-bfa2-4883-bb97-e772e8a0c4a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687017448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.687017448
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.654078436
Short name T306
Test name
Test status
Simulation time 195374001533 ps
CPU time 230.48 seconds
Started Jun 13 02:33:34 PM PDT 24
Finished Jun 13 02:37:27 PM PDT 24
Peak memory 202184 kb
Host smart-e3865eb9-412e-444d-a343-d350b853abb6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654078436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gati
ng.654078436
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.1904557547
Short name T296
Test name
Test status
Simulation time 324714027714 ps
CPU time 689.82 seconds
Started Jun 13 02:33:34 PM PDT 24
Finished Jun 13 02:45:06 PM PDT 24
Peak memory 202180 kb
Host smart-3fc47acc-2a81-4fec-92e2-689ab2d76974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904557547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.1904557547
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.455490249
Short name T593
Test name
Test status
Simulation time 330395768261 ps
CPU time 745.98 seconds
Started Jun 13 02:33:33 PM PDT 24
Finished Jun 13 02:46:02 PM PDT 24
Peak memory 202180 kb
Host smart-4c6f3327-68f4-4c3a-a338-b97137d56468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455490249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.455490249
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.2687547988
Short name T525
Test name
Test status
Simulation time 489606528028 ps
CPU time 593.55 seconds
Started Jun 13 02:33:33 PM PDT 24
Finished Jun 13 02:43:29 PM PDT 24
Peak memory 202140 kb
Host smart-3be068bf-04d5-4980-8bc2-4fb964751cb4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687547988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.2687547988
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.228223256
Short name T295
Test name
Test status
Simulation time 499225720378 ps
CPU time 1119.35 seconds
Started Jun 13 02:33:27 PM PDT 24
Finished Jun 13 02:52:08 PM PDT 24
Peak memory 202312 kb
Host smart-491bffed-c8c1-499a-befa-5f1f200451b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228223256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.228223256
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.930576397
Short name T631
Test name
Test status
Simulation time 161051667705 ps
CPU time 348.99 seconds
Started Jun 13 02:33:29 PM PDT 24
Finished Jun 13 02:39:20 PM PDT 24
Peak memory 202172 kb
Host smart-058d39f9-3186-42ca-81e1-aa37ac26b80f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=930576397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fixe
d.930576397
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.2765730543
Short name T284
Test name
Test status
Simulation time 394705047971 ps
CPU time 884.08 seconds
Started Jun 13 02:33:32 PM PDT 24
Finished Jun 13 02:48:17 PM PDT 24
Peak memory 202204 kb
Host smart-aced530f-fcd3-4ec2-a2ac-e7b9193855b0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765730543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.2765730543
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.2281873808
Short name T604
Test name
Test status
Simulation time 199541955062 ps
CPU time 418.94 seconds
Started Jun 13 02:33:33 PM PDT 24
Finished Jun 13 02:40:34 PM PDT 24
Peak memory 202156 kb
Host smart-6aace416-5389-4be6-801d-34f4d1401667
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281873808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.2281873808
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.3507269351
Short name T49
Test name
Test status
Simulation time 122211818723 ps
CPU time 616.58 seconds
Started Jun 13 02:33:34 PM PDT 24
Finished Jun 13 02:43:53 PM PDT 24
Peak memory 202472 kb
Host smart-955176fa-e14a-45a6-8ff7-fd3b328a0b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507269351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.3507269351
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.3489225212
Short name T77
Test name
Test status
Simulation time 31121939654 ps
CPU time 17.28 seconds
Started Jun 13 02:33:33 PM PDT 24
Finished Jun 13 02:33:53 PM PDT 24
Peak memory 202032 kb
Host smart-2ba970e0-b45c-4299-9910-1960ea8b1033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489225212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.3489225212
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.3361155076
Short name T158
Test name
Test status
Simulation time 4514522650 ps
CPU time 11.97 seconds
Started Jun 13 02:33:35 PM PDT 24
Finished Jun 13 02:33:49 PM PDT 24
Peak memory 202016 kb
Host smart-0d70ee85-b5a4-4f97-bc09-a8d74ba18d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361155076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.3361155076
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.4103887661
Short name T443
Test name
Test status
Simulation time 5569890586 ps
CPU time 7.26 seconds
Started Jun 13 02:33:29 PM PDT 24
Finished Jun 13 02:33:38 PM PDT 24
Peak memory 202012 kb
Host smart-0aa4c6c1-e286-4c66-8157-cb01f4dd80ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103887661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.4103887661
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.867722073
Short name T318
Test name
Test status
Simulation time 316744723708 ps
CPU time 186.54 seconds
Started Jun 13 02:33:36 PM PDT 24
Finished Jun 13 02:36:44 PM PDT 24
Peak memory 202196 kb
Host smart-bdd7b042-7d6e-4581-a987-cb6d3389e031
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867722073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all.
867722073
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.3666026426
Short name T18
Test name
Test status
Simulation time 103872938607 ps
CPU time 61.2 seconds
Started Jun 13 02:33:34 PM PDT 24
Finished Jun 13 02:34:38 PM PDT 24
Peak memory 202332 kb
Host smart-fec0edab-a954-4622-8029-50e18c1bac1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666026426 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.3666026426
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.3929065665
Short name T743
Test name
Test status
Simulation time 298411603 ps
CPU time 1.36 seconds
Started Jun 13 02:33:49 PM PDT 24
Finished Jun 13 02:33:51 PM PDT 24
Peak memory 201908 kb
Host smart-51585bd2-1978-4792-9ff6-58dea2f23748
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929065665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.3929065665
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.3406092186
Short name T249
Test name
Test status
Simulation time 168990943391 ps
CPU time 373.12 seconds
Started Jun 13 02:33:41 PM PDT 24
Finished Jun 13 02:39:55 PM PDT 24
Peak memory 202212 kb
Host smart-3b4392e8-38c5-4f2a-a77a-8050726c50cf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406092186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.3406092186
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.4175392512
Short name T300
Test name
Test status
Simulation time 330756221841 ps
CPU time 761.49 seconds
Started Jun 13 02:33:42 PM PDT 24
Finished Jun 13 02:46:25 PM PDT 24
Peak memory 202228 kb
Host smart-8e4e2869-4382-484d-8efa-a7c8ca8dd5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175392512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.4175392512
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.1735944722
Short name T558
Test name
Test status
Simulation time 477073760683 ps
CPU time 291.05 seconds
Started Jun 13 02:33:41 PM PDT 24
Finished Jun 13 02:38:33 PM PDT 24
Peak memory 202268 kb
Host smart-a045eced-fa15-4e2c-bf9c-545ce3d9c475
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735944722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.1735944722
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.1732702776
Short name T317
Test name
Test status
Simulation time 497207122535 ps
CPU time 448.87 seconds
Started Jun 13 02:33:41 PM PDT 24
Finished Jun 13 02:41:12 PM PDT 24
Peak memory 202252 kb
Host smart-038a8dd7-544a-486e-be7c-9d700ffcc201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732702776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.1732702776
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.2937598788
Short name T504
Test name
Test status
Simulation time 164424406694 ps
CPU time 90.85 seconds
Started Jun 13 02:33:40 PM PDT 24
Finished Jun 13 02:35:12 PM PDT 24
Peak memory 202176 kb
Host smart-b18df696-398a-47f5-921e-45f42237ff2c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937598788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.2937598788
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.2949675005
Short name T578
Test name
Test status
Simulation time 399037154729 ps
CPU time 846.78 seconds
Started Jun 13 02:33:40 PM PDT 24
Finished Jun 13 02:47:48 PM PDT 24
Peak memory 202220 kb
Host smart-dd8fbd80-3905-4068-997e-59b25efb618b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949675005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.2949675005
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.4063048242
Short name T778
Test name
Test status
Simulation time 105478899513 ps
CPU time 570.97 seconds
Started Jun 13 02:33:40 PM PDT 24
Finished Jun 13 02:43:12 PM PDT 24
Peak memory 202576 kb
Host smart-ef258264-7236-4d0d-b5f6-6f38c96c6091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063048242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.4063048242
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.2386271274
Short name T746
Test name
Test status
Simulation time 29628584910 ps
CPU time 17.13 seconds
Started Jun 13 02:33:40 PM PDT 24
Finished Jun 13 02:33:59 PM PDT 24
Peak memory 202028 kb
Host smart-9a0209b6-ac13-48ae-9ef6-d41cd417adc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386271274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.2386271274
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.3829358822
Short name T351
Test name
Test status
Simulation time 3900655769 ps
CPU time 3.87 seconds
Started Jun 13 02:33:39 PM PDT 24
Finished Jun 13 02:33:44 PM PDT 24
Peak memory 202076 kb
Host smart-2e127271-86ef-417d-b833-8a0449af1431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829358822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.3829358822
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.4286411067
Short name T454
Test name
Test status
Simulation time 5902201732 ps
CPU time 13.37 seconds
Started Jun 13 02:33:32 PM PDT 24
Finished Jun 13 02:33:48 PM PDT 24
Peak memory 202012 kb
Host smart-98561320-dd2a-4e88-abb2-3e90836d849a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286411067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.4286411067
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.2876731874
Short name T596
Test name
Test status
Simulation time 329759621756 ps
CPU time 209.59 seconds
Started Jun 13 02:33:47 PM PDT 24
Finished Jun 13 02:37:18 PM PDT 24
Peak memory 202276 kb
Host smart-28921be6-2daf-4a7d-a408-b32a29c4d468
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876731874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.2876731874
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.932500504
Short name T672
Test name
Test status
Simulation time 84396286643 ps
CPU time 178.97 seconds
Started Jun 13 02:33:39 PM PDT 24
Finished Jun 13 02:36:40 PM PDT 24
Peak memory 210604 kb
Host smart-f6686f51-6121-45eb-abda-92810c9c1211
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932500504 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.932500504
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.969719678
Short name T595
Test name
Test status
Simulation time 315984546 ps
CPU time 1.58 seconds
Started Jun 13 02:33:59 PM PDT 24
Finished Jun 13 02:34:02 PM PDT 24
Peak memory 201912 kb
Host smart-b4e145d9-77fe-4ae9-94ed-daa170d5790b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969719678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.969719678
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.3996372
Short name T313
Test name
Test status
Simulation time 181836969400 ps
CPU time 397.17 seconds
Started Jun 13 02:33:48 PM PDT 24
Finished Jun 13 02:40:26 PM PDT 24
Peak memory 202216 kb
Host smart-2af89c25-017e-46a6-ab17-892677149fb5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gat
ing_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gating.3996372
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.1640248350
Short name T308
Test name
Test status
Simulation time 328347152939 ps
CPU time 181.75 seconds
Started Jun 13 02:33:48 PM PDT 24
Finished Jun 13 02:36:51 PM PDT 24
Peak memory 202200 kb
Host smart-dc633763-902e-4337-90fa-8d0682006050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640248350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.1640248350
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.447028147
Short name T684
Test name
Test status
Simulation time 165233530337 ps
CPU time 182.02 seconds
Started Jun 13 02:33:49 PM PDT 24
Finished Jun 13 02:36:52 PM PDT 24
Peak memory 202136 kb
Host smart-7a9743d3-a60e-4bf4-ad6b-5577979f8748
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=447028147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrup
t_fixed.447028147
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.1921577044
Short name T695
Test name
Test status
Simulation time 160277626293 ps
CPU time 98.24 seconds
Started Jun 13 02:33:48 PM PDT 24
Finished Jun 13 02:35:27 PM PDT 24
Peak memory 202176 kb
Host smart-c32219dd-4799-4262-ac27-07f641c2607d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921577044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.1921577044
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.2493649444
Short name T722
Test name
Test status
Simulation time 597275905563 ps
CPU time 1379.4 seconds
Started Jun 13 02:33:47 PM PDT 24
Finished Jun 13 02:56:48 PM PDT 24
Peak memory 202272 kb
Host smart-770da7a2-9f60-4e7b-a8aa-84337b362bf9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493649444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.2493649444
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.749017900
Short name T575
Test name
Test status
Simulation time 203399949142 ps
CPU time 456.48 seconds
Started Jun 13 02:33:49 PM PDT 24
Finished Jun 13 02:41:26 PM PDT 24
Peak memory 202184 kb
Host smart-7252fa06-977c-4ba2-8150-396fdd08bf0e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749017900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
adc_ctrl_filters_wakeup_fixed.749017900
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.3085744443
Short name T182
Test name
Test status
Simulation time 83083836396 ps
CPU time 329.23 seconds
Started Jun 13 02:33:56 PM PDT 24
Finished Jun 13 02:39:26 PM PDT 24
Peak memory 202588 kb
Host smart-05cd9bab-efc1-4b7d-b9d4-022286f23b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085744443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.3085744443
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.559099847
Short name T705
Test name
Test status
Simulation time 36238391856 ps
CPU time 86.43 seconds
Started Jun 13 02:33:54 PM PDT 24
Finished Jun 13 02:35:21 PM PDT 24
Peak memory 202056 kb
Host smart-4bb8d509-6727-4158-b3cc-06bd6f468d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559099847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.559099847
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.3167596526
Short name T343
Test name
Test status
Simulation time 5011614064 ps
CPU time 2.23 seconds
Started Jun 13 02:33:47 PM PDT 24
Finished Jun 13 02:33:50 PM PDT 24
Peak memory 202028 kb
Host smart-84fb36e4-4693-4673-8065-dc27767cb67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167596526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.3167596526
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.2608537849
Short name T692
Test name
Test status
Simulation time 6063002185 ps
CPU time 13.65 seconds
Started Jun 13 02:33:49 PM PDT 24
Finished Jun 13 02:34:04 PM PDT 24
Peak memory 202012 kb
Host smart-66ebbda9-32ef-487f-ac73-53fab9962a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608537849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.2608537849
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.459357590
Short name T761
Test name
Test status
Simulation time 496383361611 ps
CPU time 1105.92 seconds
Started Jun 13 02:33:57 PM PDT 24
Finished Jun 13 02:52:24 PM PDT 24
Peak memory 202196 kb
Host smart-3ab89bc1-3d13-4208-956d-e0f425c0ce03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459357590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all.
459357590
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.177121244
Short name T645
Test name
Test status
Simulation time 419086244 ps
CPU time 1.16 seconds
Started Jun 13 02:34:01 PM PDT 24
Finished Jun 13 02:34:04 PM PDT 24
Peak memory 201908 kb
Host smart-8045d491-3aff-484a-8017-7563e28100e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177121244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.177121244
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.903163184
Short name T324
Test name
Test status
Simulation time 336090957663 ps
CPU time 202.21 seconds
Started Jun 13 03:01:49 PM PDT 24
Finished Jun 13 03:05:12 PM PDT 24
Peak memory 202172 kb
Host smart-4988e589-7185-4647-9230-159cd2692bfe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903163184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gati
ng.903163184
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.775028552
Short name T788
Test name
Test status
Simulation time 338533328583 ps
CPU time 401.94 seconds
Started Jun 13 02:34:01 PM PDT 24
Finished Jun 13 02:40:45 PM PDT 24
Peak memory 202196 kb
Host smart-ec8bdb96-56da-443d-b031-0df1619621b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775028552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.775028552
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.636348694
Short name T474
Test name
Test status
Simulation time 497411326951 ps
CPU time 1028.13 seconds
Started Jun 13 02:33:55 PM PDT 24
Finished Jun 13 02:51:03 PM PDT 24
Peak memory 202220 kb
Host smart-35a001a3-081f-4538-9892-14796b8789d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636348694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.636348694
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.1576182505
Short name T281
Test name
Test status
Simulation time 162889155445 ps
CPU time 101.41 seconds
Started Jun 13 02:33:56 PM PDT 24
Finished Jun 13 02:35:39 PM PDT 24
Peak memory 202236 kb
Host smart-634120e4-e8e8-45f6-bac7-10f9c1c79cce
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576182505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.1576182505
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.3140329763
Short name T408
Test name
Test status
Simulation time 166583448573 ps
CPU time 110.17 seconds
Started Jun 13 02:33:56 PM PDT 24
Finished Jun 13 02:35:47 PM PDT 24
Peak memory 202168 kb
Host smart-769280ed-d9b2-402f-b96f-6f4226e0aee0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140329763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.3140329763
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.2687463447
Short name T162
Test name
Test status
Simulation time 189371630265 ps
CPU time 34.64 seconds
Started Jun 13 02:33:55 PM PDT 24
Finished Jun 13 02:34:31 PM PDT 24
Peak memory 202240 kb
Host smart-0681cc4d-8285-4397-9346-12b5e706458c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687463447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.2687463447
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.2547541598
Short name T354
Test name
Test status
Simulation time 609059627642 ps
CPU time 713.11 seconds
Started Jun 13 02:33:57 PM PDT 24
Finished Jun 13 02:45:52 PM PDT 24
Peak memory 202160 kb
Host smart-9ac2b385-06f3-4742-ad5f-b86a61d9f859
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547541598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.2547541598
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.2546138040
Short name T378
Test name
Test status
Simulation time 46377016110 ps
CPU time 110.68 seconds
Started Jun 13 02:34:01 PM PDT 24
Finished Jun 13 02:35:53 PM PDT 24
Peak memory 201992 kb
Host smart-8c67e41c-773e-41fe-a695-1f2241ab3319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546138040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.2546138040
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.1568579380
Short name T539
Test name
Test status
Simulation time 3038001585 ps
CPU time 8.13 seconds
Started Jun 13 02:34:01 PM PDT 24
Finished Jun 13 02:34:10 PM PDT 24
Peak memory 202052 kb
Host smart-51324caf-a4c0-4626-a757-305fb315941d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568579380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.1568579380
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.4061819584
Short name T79
Test name
Test status
Simulation time 6121774130 ps
CPU time 2.24 seconds
Started Jun 13 02:33:57 PM PDT 24
Finished Jun 13 02:34:00 PM PDT 24
Peak memory 202044 kb
Host smart-f85c1c53-3744-4ab4-9dbe-91fa7035271b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061819584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.4061819584
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.14823771
Short name T490
Test name
Test status
Simulation time 530757656892 ps
CPU time 203.84 seconds
Started Jun 13 02:34:00 PM PDT 24
Finished Jun 13 02:37:25 PM PDT 24
Peak memory 202252 kb
Host smart-752bdc27-53c9-497b-b0af-33cbf50a988a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14823771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all.14823771
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.1885052073
Short name T737
Test name
Test status
Simulation time 79812251876 ps
CPU time 45.57 seconds
Started Jun 13 02:34:00 PM PDT 24
Finished Jun 13 02:34:47 PM PDT 24
Peak memory 202424 kb
Host smart-d6a5cee7-5f88-481a-b8dc-98534f3a88a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885052073 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.1885052073
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.748597429
Short name T515
Test name
Test status
Simulation time 435331945 ps
CPU time 0.88 seconds
Started Jun 13 02:34:13 PM PDT 24
Finished Jun 13 02:34:16 PM PDT 24
Peak memory 201916 kb
Host smart-fd97e857-6e13-405d-955f-6a04c2dacbf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748597429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.748597429
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.3596185524
Short name T222
Test name
Test status
Simulation time 327516509324 ps
CPU time 186.87 seconds
Started Jun 13 02:34:11 PM PDT 24
Finished Jun 13 02:37:18 PM PDT 24
Peak memory 202196 kb
Host smart-3945d03d-0faa-4576-8685-fa99f2bff399
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596185524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.3596185524
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.2574160146
Short name T211
Test name
Test status
Simulation time 167703859809 ps
CPU time 340.04 seconds
Started Jun 13 02:34:11 PM PDT 24
Finished Jun 13 02:39:52 PM PDT 24
Peak memory 202292 kb
Host smart-bb12e1de-aeb7-4e73-83d3-98cd5e812f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574160146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.2574160146
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.1320691051
Short name T702
Test name
Test status
Simulation time 484984852730 ps
CPU time 1151.26 seconds
Started Jun 13 02:34:11 PM PDT 24
Finished Jun 13 02:53:23 PM PDT 24
Peak memory 202316 kb
Host smart-104f66f8-6fca-45d1-bf90-ceccc69f61dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320691051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.1320691051
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.1998047625
Short name T464
Test name
Test status
Simulation time 333479845558 ps
CPU time 205.45 seconds
Started Jun 13 02:34:10 PM PDT 24
Finished Jun 13 02:37:36 PM PDT 24
Peak memory 202212 kb
Host smart-844121e1-d486-4af2-bad0-0a819890196e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998047625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.1998047625
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.377463023
Short name T731
Test name
Test status
Simulation time 164188069314 ps
CPU time 152.21 seconds
Started Jun 13 02:34:01 PM PDT 24
Finished Jun 13 02:36:34 PM PDT 24
Peak memory 202112 kb
Host smart-531172e6-f952-4f3b-bc66-5d0f9b84255e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=377463023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fixe
d.377463023
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.2447804214
Short name T251
Test name
Test status
Simulation time 171418028279 ps
CPU time 29.61 seconds
Started Jun 13 02:34:09 PM PDT 24
Finished Jun 13 02:34:40 PM PDT 24
Peak memory 202208 kb
Host smart-030aecec-6f9e-4a39-9888-393630515c0a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447804214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.2447804214
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.3818535960
Short name T658
Test name
Test status
Simulation time 603034311182 ps
CPU time 1302.69 seconds
Started Jun 13 02:34:07 PM PDT 24
Finished Jun 13 02:55:51 PM PDT 24
Peak memory 202280 kb
Host smart-4225592e-2896-42e4-9f75-d417acaadc2d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818535960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.3818535960
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.1038561121
Short name T677
Test name
Test status
Simulation time 121185855287 ps
CPU time 634.29 seconds
Started Jun 13 02:34:09 PM PDT 24
Finished Jun 13 02:44:45 PM PDT 24
Peak memory 202484 kb
Host smart-6b5f9834-ec8f-4151-8762-2e40faf47e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038561121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.1038561121
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.2623402701
Short name T617
Test name
Test status
Simulation time 33809457019 ps
CPU time 20.43 seconds
Started Jun 13 02:34:08 PM PDT 24
Finished Jun 13 02:34:30 PM PDT 24
Peak memory 201972 kb
Host smart-dad0473a-da5e-4811-8236-c2e9aa18d18c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623402701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.2623402701
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.2637399961
Short name T3
Test name
Test status
Simulation time 5191804590 ps
CPU time 12.54 seconds
Started Jun 13 02:34:08 PM PDT 24
Finished Jun 13 02:34:22 PM PDT 24
Peak memory 202064 kb
Host smart-dbf61687-7081-4c8a-9fca-e045d2770e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637399961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.2637399961
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.922491038
Short name T364
Test name
Test status
Simulation time 5645343858 ps
CPU time 14.02 seconds
Started Jun 13 02:34:00 PM PDT 24
Finished Jun 13 02:34:15 PM PDT 24
Peak memory 202024 kb
Host smart-5f1e0ea9-0491-4348-921a-08dba19d5c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922491038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.922491038
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.2425099621
Short name T629
Test name
Test status
Simulation time 186603458114 ps
CPU time 107.66 seconds
Started Jun 13 02:34:10 PM PDT 24
Finished Jun 13 02:35:59 PM PDT 24
Peak memory 202268 kb
Host smart-2e3965ea-3207-450d-a676-a92996b81b86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425099621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.2425099621
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.1728045185
Short name T119
Test name
Test status
Simulation time 101570737297 ps
CPU time 105.87 seconds
Started Jun 13 02:43:24 PM PDT 24
Finished Jun 13 02:45:12 PM PDT 24
Peak memory 210572 kb
Host smart-4f24563f-a0a9-484e-aa72-6e4949c40dfe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728045185 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.1728045185
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.4012280402
Short name T420
Test name
Test status
Simulation time 330287182 ps
CPU time 1.39 seconds
Started Jun 13 02:31:28 PM PDT 24
Finished Jun 13 02:31:36 PM PDT 24
Peak memory 201896 kb
Host smart-410430fc-75e0-4811-8c5f-6f6b171c90ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012280402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.4012280402
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.2187176740
Short name T449
Test name
Test status
Simulation time 181526263746 ps
CPU time 110.65 seconds
Started Jun 13 02:31:33 PM PDT 24
Finished Jun 13 02:33:30 PM PDT 24
Peak memory 202248 kb
Host smart-925387d3-36b5-44d1-8657-af97fcab16c6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187176740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.2187176740
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.1390681224
Short name T15
Test name
Test status
Simulation time 165815939863 ps
CPU time 360.35 seconds
Started Jun 13 02:31:34 PM PDT 24
Finished Jun 13 02:37:40 PM PDT 24
Peak memory 202228 kb
Host smart-f1fca38a-9208-4429-aec5-f733cc8f0de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390681224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.1390681224
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.41722197
Short name T628
Test name
Test status
Simulation time 161679415162 ps
CPU time 98.37 seconds
Started Jun 13 02:31:27 PM PDT 24
Finished Jun 13 02:33:11 PM PDT 24
Peak memory 202216 kb
Host smart-5f4b9c6b-27cf-41ec-a30f-fbf5ea5f870f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41722197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.41722197
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.114567924
Short name T736
Test name
Test status
Simulation time 498413941119 ps
CPU time 1116.28 seconds
Started Jun 13 02:31:46 PM PDT 24
Finished Jun 13 02:50:25 PM PDT 24
Peak memory 202244 kb
Host smart-6b3adfa7-9ba4-4a7b-8bd6-0e972264ac85
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=114567924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt
_fixed.114567924
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.369171577
Short name T1
Test name
Test status
Simulation time 167001173895 ps
CPU time 371.73 seconds
Started Jun 13 02:31:25 PM PDT 24
Finished Jun 13 02:37:42 PM PDT 24
Peak memory 202296 kb
Host smart-12757ead-2090-4bd6-be7b-1df2b2b36451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369171577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.369171577
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.4246087557
Short name T168
Test name
Test status
Simulation time 164463966569 ps
CPU time 399.97 seconds
Started Jun 13 02:31:27 PM PDT 24
Finished Jun 13 02:38:13 PM PDT 24
Peak memory 202168 kb
Host smart-00282005-67ad-4857-89ca-b082d237b793
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246087557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.4246087557
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.1005917013
Short name T716
Test name
Test status
Simulation time 190345000377 ps
CPU time 119.91 seconds
Started Jun 13 02:31:38 PM PDT 24
Finished Jun 13 02:33:43 PM PDT 24
Peak memory 202184 kb
Host smart-ee04ce0a-1e4d-406c-b6a3-cf2667ccfd8d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005917013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.1005917013
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.1357426871
Short name T488
Test name
Test status
Simulation time 29489027550 ps
CPU time 72.43 seconds
Started Jun 13 02:31:29 PM PDT 24
Finished Jun 13 02:32:47 PM PDT 24
Peak memory 201988 kb
Host smart-28775f44-5224-40c9-8955-fdb8c2b5e580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357426871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.1357426871
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.231273758
Short name T608
Test name
Test status
Simulation time 2919663247 ps
CPU time 7.43 seconds
Started Jun 13 02:31:29 PM PDT 24
Finished Jun 13 02:31:42 PM PDT 24
Peak memory 201976 kb
Host smart-b3ff7ce2-f0f9-4f38-af6f-c59e3fd05f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231273758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.231273758
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.3493923008
Short name T17
Test name
Test status
Simulation time 7712875423 ps
CPU time 5.32 seconds
Started Jun 13 02:31:29 PM PDT 24
Finished Jun 13 02:31:40 PM PDT 24
Peak memory 218764 kb
Host smart-c021a163-58c7-4a7f-9c49-76bb58aa0b8d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493923008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.3493923008
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.931579520
Short name T512
Test name
Test status
Simulation time 6062340336 ps
CPU time 4.06 seconds
Started Jun 13 02:31:28 PM PDT 24
Finished Jun 13 02:31:38 PM PDT 24
Peak memory 202020 kb
Host smart-9176efbc-6cf2-41a8-9959-82d2cf8b9b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931579520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.931579520
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.3126466707
Short name T319
Test name
Test status
Simulation time 537947273470 ps
CPU time 291.56 seconds
Started Jun 13 02:31:39 PM PDT 24
Finished Jun 13 02:36:35 PM PDT 24
Peak memory 202196 kb
Host smart-2c04ad18-d31a-431e-9f85-6d3fb6a6e9e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126466707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
3126466707
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.2313822023
Short name T710
Test name
Test status
Simulation time 268625645188 ps
CPU time 146.12 seconds
Started Jun 13 02:31:36 PM PDT 24
Finished Jun 13 02:34:08 PM PDT 24
Peak memory 210900 kb
Host smart-07b9f774-8c81-473e-bdc1-f54e00edb0fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313822023 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.2313822023
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.1295514419
Short name T714
Test name
Test status
Simulation time 465504146 ps
CPU time 1.73 seconds
Started Jun 13 02:34:12 PM PDT 24
Finished Jun 13 02:34:14 PM PDT 24
Peak memory 201944 kb
Host smart-7237be5b-3d3d-40d0-8be5-4f5d7ac69f30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295514419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.1295514419
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.1312611639
Short name T738
Test name
Test status
Simulation time 166009766158 ps
CPU time 50.2 seconds
Started Jun 13 02:34:13 PM PDT 24
Finished Jun 13 02:35:04 PM PDT 24
Peak memory 202196 kb
Host smart-4695c878-247b-4c9d-b66c-9b3830b6ba00
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312611639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.1312611639
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.1797695115
Short name T694
Test name
Test status
Simulation time 208088511187 ps
CPU time 116.03 seconds
Started Jun 13 02:34:12 PM PDT 24
Finished Jun 13 02:36:09 PM PDT 24
Peak memory 202236 kb
Host smart-4819a898-0fc0-4835-b601-5508b700513c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797695115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.1797695115
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.155995026
Short name T265
Test name
Test status
Simulation time 327709340702 ps
CPU time 749.48 seconds
Started Jun 13 02:34:12 PM PDT 24
Finished Jun 13 02:46:42 PM PDT 24
Peak memory 202204 kb
Host smart-344d14dd-2c19-4db7-91e9-b7dd913250cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155995026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.155995026
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.586010367
Short name T671
Test name
Test status
Simulation time 324625384906 ps
CPU time 705.84 seconds
Started Jun 13 02:34:13 PM PDT 24
Finished Jun 13 02:46:00 PM PDT 24
Peak memory 202168 kb
Host smart-b3284217-fbce-4e1a-9653-804b34144ff9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=586010367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrup
t_fixed.586010367
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.4229102434
Short name T307
Test name
Test status
Simulation time 166379983367 ps
CPU time 53.52 seconds
Started Jun 13 02:34:14 PM PDT 24
Finished Jun 13 02:35:09 PM PDT 24
Peak memory 202312 kb
Host smart-95134ee2-0b82-4e49-8cd3-4c4a67b695b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229102434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.4229102434
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.1135927169
Short name T374
Test name
Test status
Simulation time 159829219298 ps
CPU time 77.6 seconds
Started Jun 13 02:34:13 PM PDT 24
Finished Jun 13 02:35:32 PM PDT 24
Peak memory 202140 kb
Host smart-296dbb9e-1825-492d-bcd8-44e945faf574
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135927169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.1135927169
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.1649261091
Short name T669
Test name
Test status
Simulation time 565258896128 ps
CPU time 1306.73 seconds
Started Jun 13 02:34:14 PM PDT 24
Finished Jun 13 02:56:02 PM PDT 24
Peak memory 202196 kb
Host smart-e9eeae25-1977-49f6-885a-8774b078f80f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649261091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.1649261091
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.2133361065
Short name T380
Test name
Test status
Simulation time 196149918734 ps
CPU time 166.63 seconds
Started Jun 13 02:34:15 PM PDT 24
Finished Jun 13 02:37:03 PM PDT 24
Peak memory 202212 kb
Host smart-6aa43ab2-e437-4209-9b96-aa9d1591b770
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133361065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.2133361065
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.1779521337
Short name T421
Test name
Test status
Simulation time 29590514322 ps
CPU time 17.62 seconds
Started Jun 13 02:34:13 PM PDT 24
Finished Jun 13 02:34:32 PM PDT 24
Peak memory 201992 kb
Host smart-91074c84-00e2-4529-8ec1-875f89c2d960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779521337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.1779521337
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.3800372982
Short name T584
Test name
Test status
Simulation time 4324515364 ps
CPU time 1.88 seconds
Started Jun 13 02:34:13 PM PDT 24
Finished Jun 13 02:34:17 PM PDT 24
Peak memory 202052 kb
Host smart-2e929b09-6390-4ad2-b3c8-200c4d5895eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800372982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.3800372982
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.975179570
Short name T353
Test name
Test status
Simulation time 5949407135 ps
CPU time 7.83 seconds
Started Jun 13 02:34:14 PM PDT 24
Finished Jun 13 02:34:23 PM PDT 24
Peak memory 202052 kb
Host smart-d9287e7c-e751-4101-acea-52f9e4e45296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975179570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.975179570
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.2658804653
Short name T425
Test name
Test status
Simulation time 401262494 ps
CPU time 1.56 seconds
Started Jun 13 02:34:20 PM PDT 24
Finished Jun 13 02:34:23 PM PDT 24
Peak memory 201904 kb
Host smart-8817ca21-b679-4ec2-9fdf-92fcc06078db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658804653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.2658804653
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.1731742145
Short name T650
Test name
Test status
Simulation time 538365267674 ps
CPU time 1303.44 seconds
Started Jun 13 02:34:24 PM PDT 24
Finished Jun 13 02:56:09 PM PDT 24
Peak memory 202188 kb
Host smart-825a9ae8-5c7a-46da-83ad-802d9b0f4d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731742145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.1731742145
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.1892651303
Short name T791
Test name
Test status
Simulation time 342492657105 ps
CPU time 213.83 seconds
Started Jun 13 02:34:19 PM PDT 24
Finished Jun 13 02:37:54 PM PDT 24
Peak memory 202216 kb
Host smart-bc631559-93b0-49b4-bd7f-bfae450b5d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892651303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.1892651303
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.3398946618
Short name T627
Test name
Test status
Simulation time 484889544742 ps
CPU time 1129.34 seconds
Started Jun 13 02:34:18 PM PDT 24
Finished Jun 13 02:53:08 PM PDT 24
Peak memory 202144 kb
Host smart-950cfdf8-bc39-4d89-8cc7-fd60dfe391d4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398946618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.3398946618
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.1227523768
Short name T473
Test name
Test status
Simulation time 159622791110 ps
CPU time 93.4 seconds
Started Jun 13 02:34:13 PM PDT 24
Finished Jun 13 02:35:49 PM PDT 24
Peak memory 202280 kb
Host smart-db4d9f2f-f9a3-4969-b484-60fa0edf9a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227523768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.1227523768
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.3591715972
Short name T395
Test name
Test status
Simulation time 162737397839 ps
CPU time 98.16 seconds
Started Jun 13 02:34:20 PM PDT 24
Finished Jun 13 02:36:00 PM PDT 24
Peak memory 202176 kb
Host smart-5f9270a1-cbe4-4f57-8342-44b6d839e959
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591715972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.3591715972
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.1464870053
Short name T126
Test name
Test status
Simulation time 355632966918 ps
CPU time 766.74 seconds
Started Jun 13 02:34:19 PM PDT 24
Finished Jun 13 02:47:07 PM PDT 24
Peak memory 202184 kb
Host smart-c7091148-863e-4f7f-acf6-7497b725e040
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464870053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.1464870053
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.1978365418
Short name T647
Test name
Test status
Simulation time 196775014494 ps
CPU time 449.79 seconds
Started Jun 13 02:34:19 PM PDT 24
Finished Jun 13 02:41:51 PM PDT 24
Peak memory 202196 kb
Host smart-dcc71aa7-6c02-451c-9445-abf75faad7ee
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978365418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.1978365418
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.1079383544
Short name T9
Test name
Test status
Simulation time 119704925288 ps
CPU time 657.62 seconds
Started Jun 13 02:34:18 PM PDT 24
Finished Jun 13 02:45:17 PM PDT 24
Peak memory 202504 kb
Host smart-9db39d62-5c1c-474a-994f-7f82a6211237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079383544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.1079383544
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.3783410038
Short name T763
Test name
Test status
Simulation time 34205599424 ps
CPU time 20.5 seconds
Started Jun 13 02:34:24 PM PDT 24
Finished Jun 13 02:34:46 PM PDT 24
Peak memory 202020 kb
Host smart-c406fc3b-0610-443e-8573-77a7c3565457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783410038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.3783410038
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.2255890811
Short name T579
Test name
Test status
Simulation time 3565231425 ps
CPU time 1.9 seconds
Started Jun 13 02:34:18 PM PDT 24
Finished Jun 13 02:34:21 PM PDT 24
Peak memory 201940 kb
Host smart-e877d40f-59d2-4f16-acad-2efc265cecd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255890811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.2255890811
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.745744219
Short name T348
Test name
Test status
Simulation time 5763606714 ps
CPU time 2.28 seconds
Started Jun 13 02:34:13 PM PDT 24
Finished Jun 13 02:34:17 PM PDT 24
Peak memory 202020 kb
Host smart-9a123543-bbaf-46f7-81fb-fc74ce98814c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745744219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.745744219
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.896622920
Short name T33
Test name
Test status
Simulation time 396589824568 ps
CPU time 926.07 seconds
Started Jun 13 02:34:19 PM PDT 24
Finished Jun 13 02:49:46 PM PDT 24
Peak memory 202196 kb
Host smart-8d622c22-5afc-4c98-acb8-beabd8137d0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896622920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all.
896622920
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.1760612569
Short name T26
Test name
Test status
Simulation time 506940447632 ps
CPU time 927.86 seconds
Started Jun 13 02:34:19 PM PDT 24
Finished Jun 13 02:49:48 PM PDT 24
Peak memory 210900 kb
Host smart-cef9e16b-2674-415f-a43d-dd3aec00474f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760612569 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.1760612569
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.1410051876
Short name T414
Test name
Test status
Simulation time 380285919 ps
CPU time 1.49 seconds
Started Jun 13 02:34:31 PM PDT 24
Finished Jun 13 02:34:33 PM PDT 24
Peak memory 201912 kb
Host smart-61022beb-da63-46cc-8a2d-9cad0f4fc9f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410051876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.1410051876
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.3685688665
Short name T125
Test name
Test status
Simulation time 336347033787 ps
CPU time 215.57 seconds
Started Jun 13 02:34:24 PM PDT 24
Finished Jun 13 02:38:01 PM PDT 24
Peak memory 202252 kb
Host smart-fc3915f8-a7c8-4e24-ac6e-2954c13a797b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685688665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.3685688665
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.3416086876
Short name T243
Test name
Test status
Simulation time 429004004264 ps
CPU time 474.89 seconds
Started Jun 13 02:34:25 PM PDT 24
Finished Jun 13 02:42:21 PM PDT 24
Peak memory 202368 kb
Host smart-a634dbf1-debb-463e-8d5b-79f2fc3c7570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416086876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.3416086876
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.1586179004
Short name T288
Test name
Test status
Simulation time 485778826973 ps
CPU time 1133.15 seconds
Started Jun 13 02:34:24 PM PDT 24
Finished Jun 13 02:53:18 PM PDT 24
Peak memory 202264 kb
Host smart-1eab5418-2e16-4c4e-9c6c-fead4d25b700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586179004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.1586179004
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.3539355631
Short name T463
Test name
Test status
Simulation time 482744977728 ps
CPU time 1047.75 seconds
Started Jun 13 02:34:26 PM PDT 24
Finished Jun 13 02:51:55 PM PDT 24
Peak memory 202248 kb
Host smart-ad162f50-71b2-42ac-a249-267f814b6b04
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539355631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.3539355631
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.3595130693
Short name T535
Test name
Test status
Simulation time 326563812281 ps
CPU time 185.62 seconds
Started Jun 13 02:34:26 PM PDT 24
Finished Jun 13 02:37:32 PM PDT 24
Peak memory 202268 kb
Host smart-278ab393-2fc9-4268-928a-7cde383a167a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595130693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.3595130693
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.145711205
Short name T792
Test name
Test status
Simulation time 209437054603 ps
CPU time 247.21 seconds
Started Jun 13 02:34:24 PM PDT 24
Finished Jun 13 02:38:33 PM PDT 24
Peak memory 202188 kb
Host smart-c7a461c7-c0e2-4444-955d-eff0c2863803
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145711205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
adc_ctrl_filters_wakeup_fixed.145711205
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.2472145834
Short name T180
Test name
Test status
Simulation time 105803075539 ps
CPU time 549.46 seconds
Started Jun 13 02:34:25 PM PDT 24
Finished Jun 13 02:43:36 PM PDT 24
Peak memory 202608 kb
Host smart-bc96ce49-a800-45a8-901a-1a76fefd93e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472145834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.2472145834
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.645239769
Short name T462
Test name
Test status
Simulation time 25282323515 ps
CPU time 10.39 seconds
Started Jun 13 02:34:24 PM PDT 24
Finished Jun 13 02:34:36 PM PDT 24
Peak memory 202032 kb
Host smart-ff8f1ad9-0832-491c-a8bd-7596a640756d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645239769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.645239769
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.1604813475
Short name T699
Test name
Test status
Simulation time 3620654798 ps
CPU time 4.7 seconds
Started Jun 13 02:34:27 PM PDT 24
Finished Jun 13 02:34:32 PM PDT 24
Peak memory 202012 kb
Host smart-90d59090-6c52-4d9e-9a12-562fe691145d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604813475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.1604813475
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.3472233550
Short name T373
Test name
Test status
Simulation time 6143551607 ps
CPU time 15.04 seconds
Started Jun 13 02:34:20 PM PDT 24
Finished Jun 13 02:34:37 PM PDT 24
Peak memory 202056 kb
Host smart-17388a7f-8b2c-4284-99af-934a2ddea24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472233550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.3472233550
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.2965270180
Short name T749
Test name
Test status
Simulation time 333404182581 ps
CPU time 406.93 seconds
Started Jun 13 02:34:25 PM PDT 24
Finished Jun 13 02:41:13 PM PDT 24
Peak memory 202300 kb
Host smart-30577a02-1c94-4fcd-a3ed-8748c6f8f02a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965270180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.2965270180
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.353727244
Short name T152
Test name
Test status
Simulation time 528754980895 ps
CPU time 258.06 seconds
Started Jun 13 02:34:25 PM PDT 24
Finished Jun 13 02:38:45 PM PDT 24
Peak memory 211092 kb
Host smart-b2a0ee89-b9ff-4ab5-9008-f5ca4b310708
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353727244 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.353727244
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.1620347812
Short name T624
Test name
Test status
Simulation time 427032938 ps
CPU time 1.61 seconds
Started Jun 13 02:34:38 PM PDT 24
Finished Jun 13 02:34:41 PM PDT 24
Peak memory 201876 kb
Host smart-4cf50be5-6cc3-4091-aa45-70ff2b87fe06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620347812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.1620347812
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.2825429793
Short name T606
Test name
Test status
Simulation time 166544443986 ps
CPU time 98.99 seconds
Started Jun 13 02:34:38 PM PDT 24
Finished Jun 13 02:36:18 PM PDT 24
Peak memory 202208 kb
Host smart-8fd73230-0066-482e-b574-3575c56aedd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825429793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.2825429793
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.3579134175
Short name T192
Test name
Test status
Simulation time 332774194575 ps
CPU time 135.64 seconds
Started Jun 13 02:34:31 PM PDT 24
Finished Jun 13 02:36:47 PM PDT 24
Peak memory 202208 kb
Host smart-5ae7a283-80a4-4f81-9954-d29fc575106f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579134175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.3579134175
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.972723595
Short name T529
Test name
Test status
Simulation time 491367095548 ps
CPU time 1061.86 seconds
Started Jun 13 02:34:30 PM PDT 24
Finished Jun 13 02:52:13 PM PDT 24
Peak memory 202192 kb
Host smart-13a61ec1-833c-48d9-b8ac-6d7f382d7239
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=972723595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrup
t_fixed.972723595
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.4190664383
Short name T235
Test name
Test status
Simulation time 493532926255 ps
CPU time 599.2 seconds
Started Jun 13 02:34:32 PM PDT 24
Finished Jun 13 02:44:32 PM PDT 24
Peak memory 202248 kb
Host smart-8c90fb82-0f3c-429d-99a9-71b3dd8d68d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190664383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.4190664383
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.2397962911
Short name T392
Test name
Test status
Simulation time 165082143401 ps
CPU time 356.26 seconds
Started Jun 13 02:34:32 PM PDT 24
Finished Jun 13 02:40:29 PM PDT 24
Peak memory 202128 kb
Host smart-6aa7edd7-c82e-4686-b968-5c9d28059591
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397962911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.2397962911
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.1136481578
Short name T315
Test name
Test status
Simulation time 546242966758 ps
CPU time 1209.89 seconds
Started Jun 13 02:34:29 PM PDT 24
Finished Jun 13 02:54:40 PM PDT 24
Peak memory 202264 kb
Host smart-cfd6482f-bbe9-4a7b-8d6d-8bcd8daaeabc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136481578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.1136481578
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.1809258655
Short name T538
Test name
Test status
Simulation time 596162106289 ps
CPU time 652.9 seconds
Started Jun 13 02:34:30 PM PDT 24
Finished Jun 13 02:45:24 PM PDT 24
Peak memory 202192 kb
Host smart-b775ca06-ef55-4e4b-9391-6cbc31a600be
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809258655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.1809258655
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.4085271792
Short name T389
Test name
Test status
Simulation time 26290378113 ps
CPU time 29.24 seconds
Started Jun 13 02:34:36 PM PDT 24
Finished Jun 13 02:35:06 PM PDT 24
Peak memory 201992 kb
Host smart-6f5dd45e-7b9b-4976-8882-2ab041394cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085271792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.4085271792
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.78632194
Short name T419
Test name
Test status
Simulation time 3504224895 ps
CPU time 8.44 seconds
Started Jun 13 02:34:36 PM PDT 24
Finished Jun 13 02:34:46 PM PDT 24
Peak memory 202056 kb
Host smart-ccb4249d-0863-4673-871f-3083bb88380f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78632194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.78632194
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.1418730956
Short name T448
Test name
Test status
Simulation time 5814593031 ps
CPU time 13.17 seconds
Started Jun 13 02:34:30 PM PDT 24
Finished Jun 13 02:34:44 PM PDT 24
Peak memory 202040 kb
Host smart-e0cbe4f0-13c8-4ad4-a8f9-395f5b9e5b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418730956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.1418730956
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.3270395189
Short name T267
Test name
Test status
Simulation time 340279009535 ps
CPU time 1114.19 seconds
Started Jun 13 02:34:36 PM PDT 24
Finished Jun 13 02:53:11 PM PDT 24
Peak memory 202580 kb
Host smart-54f98696-1ca1-4419-a845-38640e64ca11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270395189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.3270395189
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.1071451803
Short name T301
Test name
Test status
Simulation time 52530546511 ps
CPU time 50.91 seconds
Started Jun 13 02:34:37 PM PDT 24
Finished Jun 13 02:35:28 PM PDT 24
Peak memory 210552 kb
Host smart-4f548d05-b76a-40d8-9139-c75ed1412db8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071451803 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.1071451803
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.4222357184
Short name T372
Test name
Test status
Simulation time 383070602 ps
CPU time 1.5 seconds
Started Jun 13 02:34:43 PM PDT 24
Finished Jun 13 02:34:46 PM PDT 24
Peak memory 201908 kb
Host smart-8e9d54f5-b1d4-4578-9a59-062840dd78f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222357184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.4222357184
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.1396670286
Short name T216
Test name
Test status
Simulation time 333288079865 ps
CPU time 206.56 seconds
Started Jun 13 02:34:43 PM PDT 24
Finished Jun 13 02:38:11 PM PDT 24
Peak memory 202212 kb
Host smart-eb54ac63-1326-4b3d-8765-befb6dbc94ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396670286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.1396670286
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.3195413913
Short name T132
Test name
Test status
Simulation time 328952544339 ps
CPU time 383.26 seconds
Started Jun 13 02:34:42 PM PDT 24
Finished Jun 13 02:41:07 PM PDT 24
Peak memory 202236 kb
Host smart-710f048b-4fdf-45eb-8975-ec117c7fc0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195413913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.3195413913
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.1160462190
Short name T457
Test name
Test status
Simulation time 162689133712 ps
CPU time 202.47 seconds
Started Jun 13 02:34:43 PM PDT 24
Finished Jun 13 02:38:07 PM PDT 24
Peak memory 202136 kb
Host smart-ac188bdc-1a7e-4074-9650-912ff997fab1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160462190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.1160462190
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.4281293697
Short name T480
Test name
Test status
Simulation time 332883666912 ps
CPU time 757.67 seconds
Started Jun 13 02:34:37 PM PDT 24
Finished Jun 13 02:47:16 PM PDT 24
Peak memory 202256 kb
Host smart-452079bc-aba3-4ae5-b306-860943ac352b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281293697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.4281293697
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.531790207
Short name T238
Test name
Test status
Simulation time 559417513001 ps
CPU time 1152.76 seconds
Started Jun 13 02:34:45 PM PDT 24
Finished Jun 13 02:53:59 PM PDT 24
Peak memory 202268 kb
Host smart-a89f9b30-3b52-441f-84cc-2fecf41ee935
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531790207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_
wakeup.531790207
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.933122590
Short name T556
Test name
Test status
Simulation time 596006146279 ps
CPU time 847.67 seconds
Started Jun 13 02:34:43 PM PDT 24
Finished Jun 13 02:48:52 PM PDT 24
Peak memory 202280 kb
Host smart-8a0a4af6-99bd-4785-bf2c-2c999fc63096
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933122590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
adc_ctrl_filters_wakeup_fixed.933122590
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.2523420295
Short name T175
Test name
Test status
Simulation time 120580461417 ps
CPU time 504.27 seconds
Started Jun 13 02:34:43 PM PDT 24
Finished Jun 13 02:43:08 PM PDT 24
Peak memory 202592 kb
Host smart-9762cf78-6df5-4b33-864b-ba0b5a9fcfd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523420295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.2523420295
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.360179262
Short name T441
Test name
Test status
Simulation time 36031335436 ps
CPU time 35.47 seconds
Started Jun 13 02:34:43 PM PDT 24
Finished Jun 13 02:35:20 PM PDT 24
Peak memory 202036 kb
Host smart-044dea66-fe2f-4aaf-b3d7-bff31bc8a8ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360179262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.360179262
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.3697117753
Short name T520
Test name
Test status
Simulation time 4705057026 ps
CPU time 11.62 seconds
Started Jun 13 02:34:42 PM PDT 24
Finished Jun 13 02:34:55 PM PDT 24
Peak memory 202020 kb
Host smart-42ae9ce5-8d29-4e2f-9a51-3c09c6895f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697117753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.3697117753
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.778297939
Short name T724
Test name
Test status
Simulation time 5777582616 ps
CPU time 3.79 seconds
Started Jun 13 02:34:38 PM PDT 24
Finished Jun 13 02:34:43 PM PDT 24
Peak memory 202040 kb
Host smart-56178d7b-3389-4f8c-95b4-7f95b5b23a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778297939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.778297939
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.33413932
Short name T719
Test name
Test status
Simulation time 421899969 ps
CPU time 1.12 seconds
Started Jun 13 02:35:01 PM PDT 24
Finished Jun 13 02:35:03 PM PDT 24
Peak memory 201876 kb
Host smart-2cad65af-4733-4775-af94-3387cfebf6a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33413932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.33413932
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.2873349473
Short name T290
Test name
Test status
Simulation time 164993891837 ps
CPU time 388.19 seconds
Started Jun 13 02:34:49 PM PDT 24
Finished Jun 13 02:41:18 PM PDT 24
Peak memory 202212 kb
Host smart-ed936db2-8a70-455c-b3b8-736aefe450f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873349473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.2873349473
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.1046406495
Short name T534
Test name
Test status
Simulation time 166135456197 ps
CPU time 218.3 seconds
Started Jun 13 02:34:47 PM PDT 24
Finished Jun 13 02:38:27 PM PDT 24
Peak memory 202284 kb
Host smart-f6543cda-6c59-4af4-822e-512349c890e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046406495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.1046406495
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.1121641882
Short name T377
Test name
Test status
Simulation time 498591472538 ps
CPU time 834.38 seconds
Started Jun 13 02:34:49 PM PDT 24
Finished Jun 13 02:48:44 PM PDT 24
Peak memory 202244 kb
Host smart-f9117306-2fdc-4709-a587-4a6d6f7c8c1e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121641882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.1121641882
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.2247180565
Short name T446
Test name
Test status
Simulation time 330427941720 ps
CPU time 778.3 seconds
Started Jun 13 02:34:47 PM PDT 24
Finished Jun 13 02:47:47 PM PDT 24
Peak memory 202224 kb
Host smart-1a40ad64-2eb6-466f-bc61-745dac66b128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247180565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.2247180565
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.3903026924
Short name T718
Test name
Test status
Simulation time 328784584044 ps
CPU time 68.03 seconds
Started Jun 13 02:34:47 PM PDT 24
Finished Jun 13 02:35:56 PM PDT 24
Peak memory 202172 kb
Host smart-ce3a3d66-3036-434c-9b22-46aad4c1c042
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903026924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.3903026924
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.1187458701
Short name T592
Test name
Test status
Simulation time 360606217211 ps
CPU time 591.03 seconds
Started Jun 13 02:34:48 PM PDT 24
Finished Jun 13 02:44:40 PM PDT 24
Peak memory 202176 kb
Host smart-fb003344-89bc-4dae-a1ee-a5fbaab89d4b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187458701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.1187458701
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.3061112672
Short name T765
Test name
Test status
Simulation time 210765401210 ps
CPU time 166.28 seconds
Started Jun 13 02:34:48 PM PDT 24
Finished Jun 13 02:37:35 PM PDT 24
Peak memory 202176 kb
Host smart-f42a6d03-f242-48ab-857f-b88f8705e899
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061112672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.3061112672
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.1739282923
Short name T183
Test name
Test status
Simulation time 124158689928 ps
CPU time 519.15 seconds
Started Jun 13 02:34:53 PM PDT 24
Finished Jun 13 02:43:33 PM PDT 24
Peak memory 202592 kb
Host smart-9bedc0fc-1df2-474a-8fea-553be10145b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739282923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.1739282923
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.2751865808
Short name T559
Test name
Test status
Simulation time 27886512978 ps
CPU time 35 seconds
Started Jun 13 02:34:54 PM PDT 24
Finished Jun 13 02:35:29 PM PDT 24
Peak memory 202040 kb
Host smart-f7c262b4-66ad-4bac-8011-ba3cd807e859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751865808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.2751865808
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.4151801762
Short name T524
Test name
Test status
Simulation time 4060479196 ps
CPU time 5.61 seconds
Started Jun 13 02:34:51 PM PDT 24
Finished Jun 13 02:34:57 PM PDT 24
Peak memory 202036 kb
Host smart-01a4ad85-bafa-46aa-9e49-ec6264d55466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151801762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.4151801762
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.3280485983
Short name T622
Test name
Test status
Simulation time 5580886670 ps
CPU time 13.11 seconds
Started Jun 13 02:34:51 PM PDT 24
Finished Jun 13 02:35:04 PM PDT 24
Peak memory 202048 kb
Host smart-97624b72-fa73-457b-a5f6-f629c2c7e33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280485983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.3280485983
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.329337885
Short name T649
Test name
Test status
Simulation time 82568810601 ps
CPU time 235.52 seconds
Started Jun 13 02:35:01 PM PDT 24
Finished Jun 13 02:38:57 PM PDT 24
Peak memory 218204 kb
Host smart-e71de88e-5fc1-484e-afd5-b622b851dc53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329337885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all.
329337885
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.3121212432
Short name T272
Test name
Test status
Simulation time 205355051528 ps
CPU time 138.51 seconds
Started Jun 13 02:34:54 PM PDT 24
Finished Jun 13 02:37:14 PM PDT 24
Peak memory 218488 kb
Host smart-c208f35d-de3b-4c32-ac48-3389e3402df9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121212432 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.3121212432
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.1181691831
Short name T466
Test name
Test status
Simulation time 505073500 ps
CPU time 1.65 seconds
Started Jun 13 02:35:06 PM PDT 24
Finished Jun 13 02:35:08 PM PDT 24
Peak memory 201820 kb
Host smart-bac1d8b8-26f6-4c05-91b5-176cc8386988
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181691831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.1181691831
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.1431109169
Short name T305
Test name
Test status
Simulation time 210048936174 ps
CPU time 218.74 seconds
Started Jun 13 02:35:06 PM PDT 24
Finished Jun 13 02:38:46 PM PDT 24
Peak memory 202236 kb
Host smart-8ee1a5a5-bad5-4f51-8436-013391e80f43
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431109169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.1431109169
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.1041556183
Short name T314
Test name
Test status
Simulation time 319258639093 ps
CPU time 700.71 seconds
Started Jun 13 02:35:02 PM PDT 24
Finished Jun 13 02:46:43 PM PDT 24
Peak memory 202184 kb
Host smart-bb4d6d8c-ee4b-4fcb-b764-240c594aee1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041556183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.1041556183
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.2452896398
Short name T356
Test name
Test status
Simulation time 162570733601 ps
CPU time 191.21 seconds
Started Jun 13 02:35:01 PM PDT 24
Finished Jun 13 02:38:14 PM PDT 24
Peak memory 202240 kb
Host smart-dd13e042-7cb9-4beb-a5a7-b8c510064ea3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452896398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.2452896398
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.924578549
Short name T415
Test name
Test status
Simulation time 159729173801 ps
CPU time 174.42 seconds
Started Jun 13 02:35:01 PM PDT 24
Finished Jun 13 02:37:56 PM PDT 24
Peak memory 202272 kb
Host smart-ba624715-44fb-4211-aa2e-2c4dbd81a3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924578549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.924578549
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.3738940348
Short name T744
Test name
Test status
Simulation time 159372019116 ps
CPU time 86.36 seconds
Started Jun 13 02:35:01 PM PDT 24
Finished Jun 13 02:36:29 PM PDT 24
Peak memory 202140 kb
Host smart-21be9269-d0ff-41d8-92bb-1317ffcfa7b0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738940348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.3738940348
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.226666298
Short name T41
Test name
Test status
Simulation time 172832875226 ps
CPU time 103.77 seconds
Started Jun 13 02:35:01 PM PDT 24
Finished Jun 13 02:36:46 PM PDT 24
Peak memory 202196 kb
Host smart-29f16ff7-d12b-43e1-9d7b-6985bfaf06f8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226666298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_
wakeup.226666298
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.1385473893
Short name T339
Test name
Test status
Simulation time 207774183610 ps
CPU time 120.78 seconds
Started Jun 13 02:35:05 PM PDT 24
Finished Jun 13 02:37:07 PM PDT 24
Peak memory 202164 kb
Host smart-0f6abcf4-e729-48b1-844c-af57cb3d113a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385473893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.1385473893
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.437294276
Short name T789
Test name
Test status
Simulation time 93919083851 ps
CPU time 392.81 seconds
Started Jun 13 02:35:05 PM PDT 24
Finished Jun 13 02:41:39 PM PDT 24
Peak memory 202516 kb
Host smart-bd6da9d7-4839-4c9e-9ff8-389cfe7d753a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437294276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.437294276
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.2579157625
Short name T401
Test name
Test status
Simulation time 43436947549 ps
CPU time 11.01 seconds
Started Jun 13 02:35:05 PM PDT 24
Finished Jun 13 02:35:17 PM PDT 24
Peak memory 202044 kb
Host smart-8d752f39-5eea-4dcf-90fc-dc1373502aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579157625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.2579157625
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.1692493676
Short name T532
Test name
Test status
Simulation time 4199743552 ps
CPU time 2.74 seconds
Started Jun 13 02:35:06 PM PDT 24
Finished Jun 13 02:35:10 PM PDT 24
Peak memory 202052 kb
Host smart-427f7847-5ab0-42d7-84b4-37be852b6c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692493676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.1692493676
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.626494134
Short name T375
Test name
Test status
Simulation time 5679718032 ps
CPU time 6.89 seconds
Started Jun 13 02:35:01 PM PDT 24
Finished Jun 13 02:35:09 PM PDT 24
Peak memory 202044 kb
Host smart-3cd4f8d7-7196-488c-81ab-1cf1545764d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626494134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.626494134
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.4176140208
Short name T685
Test name
Test status
Simulation time 164879828382 ps
CPU time 105 seconds
Started Jun 13 02:35:06 PM PDT 24
Finished Jun 13 02:36:52 PM PDT 24
Peak memory 202272 kb
Host smart-2711ad2e-bd4b-4e12-9860-4c7a9c264e1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176140208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.4176140208
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.1435963598
Short name T39
Test name
Test status
Simulation time 42061712042 ps
CPU time 81.66 seconds
Started Jun 13 02:35:05 PM PDT 24
Finished Jun 13 02:36:27 PM PDT 24
Peak memory 202328 kb
Host smart-873ce29b-5d5d-43de-8920-be59e7422792
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435963598 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.1435963598
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.3326717878
Short name T333
Test name
Test status
Simulation time 513968740 ps
CPU time 1.76 seconds
Started Jun 13 02:35:20 PM PDT 24
Finished Jun 13 02:35:23 PM PDT 24
Peak memory 201908 kb
Host smart-91286fe7-e0bb-44fb-8935-171b7dd38df8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326717878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.3326717878
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.1924652696
Short name T632
Test name
Test status
Simulation time 514030558658 ps
CPU time 1127.43 seconds
Started Jun 13 02:35:13 PM PDT 24
Finished Jun 13 02:54:01 PM PDT 24
Peak memory 202208 kb
Host smart-a4cba150-b58a-4876-b4c5-5abeac80e2c9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924652696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.1924652696
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.4010569245
Short name T127
Test name
Test status
Simulation time 335029449355 ps
CPU time 280.39 seconds
Started Jun 13 02:35:13 PM PDT 24
Finished Jun 13 02:39:55 PM PDT 24
Peak memory 202216 kb
Host smart-ec9398d9-1ff8-48f0-93bc-651b6656d746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010569245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.4010569245
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.685208956
Short name T312
Test name
Test status
Simulation time 161116080050 ps
CPU time 344.84 seconds
Started Jun 13 02:35:11 PM PDT 24
Finished Jun 13 02:40:57 PM PDT 24
Peak memory 202268 kb
Host smart-47dddd1e-8800-45d2-bde9-8dc550feb17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685208956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.685208956
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.3096040598
Short name T652
Test name
Test status
Simulation time 168616256267 ps
CPU time 407.82 seconds
Started Jun 13 02:35:13 PM PDT 24
Finished Jun 13 02:42:02 PM PDT 24
Peak memory 202232 kb
Host smart-423a0f9d-f947-4119-b1da-509d035a92bf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096040598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.3096040598
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.2851038100
Short name T485
Test name
Test status
Simulation time 164402638933 ps
CPU time 360.89 seconds
Started Jun 13 02:35:12 PM PDT 24
Finished Jun 13 02:41:14 PM PDT 24
Peak memory 202228 kb
Host smart-9899250f-e19f-4c53-9152-8d48c8a05957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851038100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.2851038100
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.1486025533
Short name T445
Test name
Test status
Simulation time 165712030058 ps
CPU time 363.34 seconds
Started Jun 13 02:35:15 PM PDT 24
Finished Jun 13 02:41:19 PM PDT 24
Peak memory 202208 kb
Host smart-3ed1bb69-e3ee-4569-b3e6-8a6c166633dc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486025533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.1486025533
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.3468778308
Short name T703
Test name
Test status
Simulation time 169869590581 ps
CPU time 99.46 seconds
Started Jun 13 02:35:13 PM PDT 24
Finished Jun 13 02:36:53 PM PDT 24
Peak memory 202160 kb
Host smart-881675ac-1b5f-46d1-92b8-9ec943ee9129
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468778308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.3468778308
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.3919602212
Short name T436
Test name
Test status
Simulation time 608820560017 ps
CPU time 681.2 seconds
Started Jun 13 02:35:12 PM PDT 24
Finished Jun 13 02:46:34 PM PDT 24
Peak memory 202224 kb
Host smart-e81beaaf-7768-423a-af86-baa4b479b88c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919602212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.3919602212
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.3308793493
Short name T185
Test name
Test status
Simulation time 102430902977 ps
CPU time 601.24 seconds
Started Jun 13 02:35:17 PM PDT 24
Finished Jun 13 02:45:20 PM PDT 24
Peak memory 202548 kb
Host smart-82fc7d05-502c-440b-88ce-8e7c1eb68651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308793493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.3308793493
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.125765975
Short name T613
Test name
Test status
Simulation time 30800436918 ps
CPU time 67.38 seconds
Started Jun 13 02:35:11 PM PDT 24
Finished Jun 13 02:36:20 PM PDT 24
Peak memory 202012 kb
Host smart-fc84e2d7-a962-49ce-a47f-6e20ef9894ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125765975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.125765975
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.1528999451
Short name T460
Test name
Test status
Simulation time 4541249880 ps
CPU time 10.54 seconds
Started Jun 13 02:35:13 PM PDT 24
Finished Jun 13 02:35:25 PM PDT 24
Peak memory 202044 kb
Host smart-65f0079e-5964-4112-bb96-eb55ff853036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528999451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.1528999451
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.3075818315
Short name T662
Test name
Test status
Simulation time 5857399111 ps
CPU time 7.01 seconds
Started Jun 13 02:35:13 PM PDT 24
Finished Jun 13 02:35:21 PM PDT 24
Peak memory 202056 kb
Host smart-e2d8917b-b1fa-4242-af7a-9634372fd830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075818315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.3075818315
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.1396191706
Short name T570
Test name
Test status
Simulation time 11004635429 ps
CPU time 25.95 seconds
Started Jun 13 02:35:20 PM PDT 24
Finished Jun 13 02:35:47 PM PDT 24
Peak memory 202064 kb
Host smart-72b566cf-c727-4d60-9235-ee6569408f95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396191706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.1396191706
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.1290992917
Short name T19
Test name
Test status
Simulation time 100837616778 ps
CPU time 57.84 seconds
Started Jun 13 02:35:18 PM PDT 24
Finished Jun 13 02:36:17 PM PDT 24
Peak memory 202328 kb
Host smart-a410bebc-6611-4b7b-a784-d40a0b2c4a55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290992917 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.1290992917
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.3052062112
Short name T700
Test name
Test status
Simulation time 419164651 ps
CPU time 0.84 seconds
Started Jun 13 02:35:25 PM PDT 24
Finished Jun 13 02:35:28 PM PDT 24
Peak memory 201944 kb
Host smart-65d6ad7b-83ee-4289-9b9e-85fb67cc4487
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052062112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.3052062112
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.1106080744
Short name T224
Test name
Test status
Simulation time 533161575242 ps
CPU time 1176.13 seconds
Started Jun 13 02:35:24 PM PDT 24
Finished Jun 13 02:55:02 PM PDT 24
Peak memory 202196 kb
Host smart-93fa53b4-a1cf-4c73-8ba7-4a2fa7c53cfc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106080744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.1106080744
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.1801476627
Short name T322
Test name
Test status
Simulation time 184750616678 ps
CPU time 404.3 seconds
Started Jun 13 02:35:26 PM PDT 24
Finished Jun 13 02:42:12 PM PDT 24
Peak memory 202220 kb
Host smart-c7f1d4a2-ff46-40f6-a0b6-af23621c831e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801476627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.1801476627
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.126504066
Short name T268
Test name
Test status
Simulation time 159423514607 ps
CPU time 96.35 seconds
Started Jun 13 02:35:25 PM PDT 24
Finished Jun 13 02:37:02 PM PDT 24
Peak memory 202328 kb
Host smart-d3c1c471-372f-492f-a82f-ff019ba1c9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126504066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.126504066
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.121460334
Short name T501
Test name
Test status
Simulation time 321858242413 ps
CPU time 727.36 seconds
Started Jun 13 02:35:26 PM PDT 24
Finished Jun 13 02:47:35 PM PDT 24
Peak memory 202240 kb
Host smart-9f4c16c5-6ef0-4877-87ee-45a7e4762437
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=121460334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrup
t_fixed.121460334
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.74041323
Short name T659
Test name
Test status
Simulation time 318938533608 ps
CPU time 264.31 seconds
Started Jun 13 02:35:20 PM PDT 24
Finished Jun 13 02:39:45 PM PDT 24
Peak memory 202292 kb
Host smart-ac5c9981-41f0-4848-8ede-9855589b8f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74041323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.74041323
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.4268443546
Short name T410
Test name
Test status
Simulation time 160967964997 ps
CPU time 348.14 seconds
Started Jun 13 02:35:20 PM PDT 24
Finished Jun 13 02:41:09 PM PDT 24
Peak memory 202196 kb
Host smart-db7508e2-df1d-4405-b5e9-8b65dd736802
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268443546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.4268443546
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.2141350207
Short name T576
Test name
Test status
Simulation time 197104682646 ps
CPU time 382.07 seconds
Started Jun 13 02:35:26 PM PDT 24
Finished Jun 13 02:41:50 PM PDT 24
Peak memory 202312 kb
Host smart-c98088cb-1372-47f8-a0ea-08dd0f26d464
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141350207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.2141350207
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.2763801358
Short name T527
Test name
Test status
Simulation time 397986139513 ps
CPU time 226.22 seconds
Started Jun 13 02:35:20 PM PDT 24
Finished Jun 13 02:39:07 PM PDT 24
Peak memory 202252 kb
Host smart-510f12d3-a1f2-49a3-88d2-0180329e3e7d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763801358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.2763801358
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.3455678953
Short name T541
Test name
Test status
Simulation time 99195784580 ps
CPU time 575.72 seconds
Started Jun 13 02:35:25 PM PDT 24
Finished Jun 13 02:45:02 PM PDT 24
Peak memory 202600 kb
Host smart-9074757b-a45b-4b55-829b-8c12d74f41d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455678953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.3455678953
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.3867593436
Short name T693
Test name
Test status
Simulation time 29685065660 ps
CPU time 31.41 seconds
Started Jun 13 02:35:25 PM PDT 24
Finished Jun 13 02:35:57 PM PDT 24
Peak memory 202008 kb
Host smart-15ec4872-a00e-449e-88f5-75f5a62f7dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867593436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.3867593436
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.2700099651
Short name T651
Test name
Test status
Simulation time 4413892118 ps
CPU time 10.73 seconds
Started Jun 13 02:40:19 PM PDT 24
Finished Jun 13 02:40:34 PM PDT 24
Peak memory 202040 kb
Host smart-cc8985e5-df04-48c2-8990-f92f6172f464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700099651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.2700099651
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.3208149377
Short name T31
Test name
Test status
Simulation time 5633561985 ps
CPU time 4.16 seconds
Started Jun 13 02:35:19 PM PDT 24
Finished Jun 13 02:35:25 PM PDT 24
Peak memory 202020 kb
Host smart-0e20ff8a-703a-410d-94c6-09a28f10058a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208149377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.3208149377
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.2255725609
Short name T721
Test name
Test status
Simulation time 259185154453 ps
CPU time 41.26 seconds
Started Jun 13 02:35:27 PM PDT 24
Finished Jun 13 02:36:10 PM PDT 24
Peak memory 211640 kb
Host smart-4a0303ae-6f92-4cdd-ac15-572b4f4c5039
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255725609 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.2255725609
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.3446993673
Short name T597
Test name
Test status
Simulation time 529725305 ps
CPU time 1.13 seconds
Started Jun 13 02:35:36 PM PDT 24
Finished Jun 13 02:35:38 PM PDT 24
Peak memory 201928 kb
Host smart-4e15143d-047e-496b-860b-8648768bc5c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446993673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.3446993673
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.541601339
Short name T133
Test name
Test status
Simulation time 519204022798 ps
CPU time 132.88 seconds
Started Jun 13 02:35:30 PM PDT 24
Finished Jun 13 02:37:44 PM PDT 24
Peak memory 202196 kb
Host smart-20d5f9c9-cb81-41be-87c3-c289b7fcadeb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541601339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gati
ng.541601339
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.1940731741
Short name T494
Test name
Test status
Simulation time 529495364426 ps
CPU time 335.36 seconds
Started Jun 13 02:35:30 PM PDT 24
Finished Jun 13 02:41:07 PM PDT 24
Peak memory 202264 kb
Host smart-f88ac26a-6154-4b05-9137-9f5bdce8f991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940731741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.1940731741
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.1084502161
Short name T638
Test name
Test status
Simulation time 320564648072 ps
CPU time 361.65 seconds
Started Jun 13 02:35:26 PM PDT 24
Finished Jun 13 02:41:30 PM PDT 24
Peak memory 202244 kb
Host smart-d379a101-efc7-4d10-92c9-0dac13509875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084502161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.1084502161
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.3015868391
Short name T432
Test name
Test status
Simulation time 164933785432 ps
CPU time 349.82 seconds
Started Jun 13 02:35:26 PM PDT 24
Finished Jun 13 02:41:18 PM PDT 24
Peak memory 202172 kb
Host smart-06a10fe3-23df-4a0b-8abf-1abf3d23d81e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015868391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.3015868391
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.2237050580
Short name T116
Test name
Test status
Simulation time 488226881069 ps
CPU time 599.58 seconds
Started Jun 13 02:35:28 PM PDT 24
Finished Jun 13 02:45:29 PM PDT 24
Peak memory 202264 kb
Host smart-5eda778e-2c11-4ee7-ad26-27aae1a108b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237050580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.2237050580
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.2058546562
Short name T109
Test name
Test status
Simulation time 500959481010 ps
CPU time 77.84 seconds
Started Jun 13 02:35:29 PM PDT 24
Finished Jun 13 02:36:48 PM PDT 24
Peak memory 202236 kb
Host smart-e2a24fdf-0c28-438d-a2f6-54f9e3df988b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058546562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.2058546562
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.3013299353
Short name T755
Test name
Test status
Simulation time 409182402838 ps
CPU time 442.52 seconds
Started Jun 13 02:35:29 PM PDT 24
Finished Jun 13 02:42:53 PM PDT 24
Peak memory 202212 kb
Host smart-618ff34d-761c-4155-9709-44106e34910d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013299353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.3013299353
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.2081980085
Short name T580
Test name
Test status
Simulation time 130841659562 ps
CPU time 690.72 seconds
Started Jun 13 02:35:36 PM PDT 24
Finished Jun 13 02:47:08 PM PDT 24
Peak memory 202600 kb
Host smart-2fbd67c8-de45-4887-adca-898ba5b0fa7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081980085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.2081980085
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.4169633918
Short name T337
Test name
Test status
Simulation time 41748720404 ps
CPU time 15.79 seconds
Started Jun 13 02:35:30 PM PDT 24
Finished Jun 13 02:35:47 PM PDT 24
Peak memory 202036 kb
Host smart-1874798c-9a4e-4a9a-b8c4-0ee4180c0735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169633918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.4169633918
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.1493560804
Short name T430
Test name
Test status
Simulation time 3489722632 ps
CPU time 8.84 seconds
Started Jun 13 02:35:31 PM PDT 24
Finished Jun 13 02:35:41 PM PDT 24
Peak memory 202028 kb
Host smart-b674c4a7-cb1d-4137-a5a1-24219f1f6d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493560804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.1493560804
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.1729086239
Short name T591
Test name
Test status
Simulation time 6013279156 ps
CPU time 4.52 seconds
Started Jun 13 02:35:24 PM PDT 24
Finished Jun 13 02:35:30 PM PDT 24
Peak memory 202044 kb
Host smart-b7350dd8-8bcc-4380-901a-fd0c74e8f15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729086239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.1729086239
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.542251679
Short name T25
Test name
Test status
Simulation time 25044110382 ps
CPU time 42.59 seconds
Started Jun 13 02:35:35 PM PDT 24
Finished Jun 13 02:36:19 PM PDT 24
Peak memory 210600 kb
Host smart-f3099f8c-505b-4c77-828c-62dfe8cff33f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542251679 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.542251679
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.2480994861
Short name T400
Test name
Test status
Simulation time 323672908 ps
CPU time 1.31 seconds
Started Jun 13 02:31:53 PM PDT 24
Finished Jun 13 02:31:59 PM PDT 24
Peak memory 201936 kb
Host smart-00fdfd42-29a6-4619-b3a5-632881c5fa47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480994861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.2480994861
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.3617895264
Short name T562
Test name
Test status
Simulation time 161858137350 ps
CPU time 115.84 seconds
Started Jun 13 02:31:31 PM PDT 24
Finished Jun 13 02:33:33 PM PDT 24
Peak memory 202184 kb
Host smart-5a1b3fbd-9c31-47cf-aa8f-cb044dcf16f1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617895264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.3617895264
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.3367054013
Short name T508
Test name
Test status
Simulation time 489466610899 ps
CPU time 791.99 seconds
Started Jun 13 02:31:31 PM PDT 24
Finished Jun 13 02:44:49 PM PDT 24
Peak memory 202256 kb
Host smart-2167edf5-7497-4cfe-9069-6982c40f3389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367054013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.3367054013
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.1148159679
Short name T517
Test name
Test status
Simulation time 490291287715 ps
CPU time 561.56 seconds
Started Jun 13 02:31:46 PM PDT 24
Finished Jun 13 02:41:11 PM PDT 24
Peak memory 202212 kb
Host smart-fbedd039-3bf5-4fd2-b5f3-a280d7463ec4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148159679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.1148159679
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.3105847994
Short name T148
Test name
Test status
Simulation time 489054917362 ps
CPU time 83.41 seconds
Started Jun 13 02:31:31 PM PDT 24
Finished Jun 13 02:33:01 PM PDT 24
Peak memory 202248 kb
Host smart-44e65475-f3df-4e4e-99b0-b37dcd3c566a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105847994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.3105847994
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.1057886633
Short name T435
Test name
Test status
Simulation time 497073524553 ps
CPU time 587.93 seconds
Started Jun 13 02:31:31 PM PDT 24
Finished Jun 13 02:41:25 PM PDT 24
Peak memory 202160 kb
Host smart-3cb94e62-450e-4122-a123-9532d1cab326
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057886633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.1057886633
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.4135086369
Short name T263
Test name
Test status
Simulation time 184710315306 ps
CPU time 422.69 seconds
Started Jun 13 02:31:30 PM PDT 24
Finished Jun 13 02:38:39 PM PDT 24
Peak memory 202204 kb
Host smart-3cc70938-2054-4782-8057-a772abfad92c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135086369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.4135086369
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.2438634762
Short name T782
Test name
Test status
Simulation time 196629486514 ps
CPU time 46.55 seconds
Started Jun 13 02:31:36 PM PDT 24
Finished Jun 13 02:32:28 PM PDT 24
Peak memory 202152 kb
Host smart-65091630-9404-4746-acb4-10c06b85ed61
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438634762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.2438634762
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.626121315
Short name T495
Test name
Test status
Simulation time 124428770730 ps
CPU time 366.18 seconds
Started Jun 13 02:31:38 PM PDT 24
Finished Jun 13 02:37:49 PM PDT 24
Peak memory 202532 kb
Host smart-ff5adfa3-9960-4cbb-a1b7-6e8e2cb10e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626121315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.626121315
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.2766265799
Short name T336
Test name
Test status
Simulation time 28369905167 ps
CPU time 18.17 seconds
Started Jun 13 02:31:28 PM PDT 24
Finished Jun 13 02:31:52 PM PDT 24
Peak memory 202048 kb
Host smart-d28873f6-51b1-4be3-936a-f7be09b3878d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766265799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.2766265799
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.972696512
Short name T423
Test name
Test status
Simulation time 3458731273 ps
CPU time 4.47 seconds
Started Jun 13 02:31:33 PM PDT 24
Finished Jun 13 02:31:43 PM PDT 24
Peak memory 202052 kb
Host smart-889cb276-7b9e-48ae-a8c2-3e81d4f881b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972696512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.972696512
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.3000614102
Short name T358
Test name
Test status
Simulation time 5713738717 ps
CPU time 3.5 seconds
Started Jun 13 02:31:39 PM PDT 24
Finished Jun 13 02:31:47 PM PDT 24
Peak memory 202056 kb
Host smart-051c1441-b2c2-48a0-810d-52c95ea96149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000614102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.3000614102
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.1965104513
Short name T730
Test name
Test status
Simulation time 274791707536 ps
CPU time 502.65 seconds
Started Jun 13 02:31:37 PM PDT 24
Finished Jun 13 02:40:05 PM PDT 24
Peak memory 210748 kb
Host smart-aa74bf8f-b13a-49eb-b448-19ffb33d51ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965104513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
1965104513
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.878513555
Short name T22
Test name
Test status
Simulation time 82002309395 ps
CPU time 285.7 seconds
Started Jun 13 02:31:28 PM PDT 24
Finished Jun 13 02:36:19 PM PDT 24
Peak memory 210924 kb
Host smart-c5d411a5-b077-49e9-b505-f0d319e5d37e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878513555 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.878513555
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.907021683
Short name T767
Test name
Test status
Simulation time 314575022 ps
CPU time 1.41 seconds
Started Jun 13 02:31:48 PM PDT 24
Finished Jun 13 02:31:52 PM PDT 24
Peak memory 201900 kb
Host smart-11d53a87-a14a-4790-a5bc-269c022d4341
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907021683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.907021683
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.2861355005
Short name T147
Test name
Test status
Simulation time 498275150722 ps
CPU time 129.04 seconds
Started Jun 13 02:31:43 PM PDT 24
Finished Jun 13 02:33:57 PM PDT 24
Peak memory 202212 kb
Host smart-70f88999-954a-495b-9c4c-751f117a7b26
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861355005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.2861355005
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.1662436759
Short name T244
Test name
Test status
Simulation time 585198097013 ps
CPU time 465.04 seconds
Started Jun 13 02:31:37 PM PDT 24
Finished Jun 13 02:39:27 PM PDT 24
Peak memory 202292 kb
Host smart-1ef9ba2a-d135-41cf-b60a-7492066831d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662436759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.1662436759
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.1684785560
Short name T574
Test name
Test status
Simulation time 329019783838 ps
CPU time 354.77 seconds
Started Jun 13 02:31:48 PM PDT 24
Finished Jun 13 02:37:46 PM PDT 24
Peak memory 202216 kb
Host smart-bf52a93a-4ec2-4fb2-9b62-53caad8a2f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684785560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.1684785560
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.779216623
Short name T350
Test name
Test status
Simulation time 490062259430 ps
CPU time 295.41 seconds
Started Jun 13 02:31:39 PM PDT 24
Finished Jun 13 02:36:39 PM PDT 24
Peak memory 202248 kb
Host smart-98f99014-3a51-4ddf-bca5-8e4ad64acef6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=779216623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt
_fixed.779216623
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.1232723249
Short name T648
Test name
Test status
Simulation time 497313277555 ps
CPU time 1120.46 seconds
Started Jun 13 02:31:37 PM PDT 24
Finished Jun 13 02:50:23 PM PDT 24
Peak memory 202260 kb
Host smart-d8ade46b-ea9c-41ae-805f-8bb6d08e2b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232723249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.1232723249
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.467175058
Short name T614
Test name
Test status
Simulation time 497830990018 ps
CPU time 1082.39 seconds
Started Jun 13 02:31:50 PM PDT 24
Finished Jun 13 02:49:56 PM PDT 24
Peak memory 202416 kb
Host smart-b1d9c416-4ea2-4364-98fa-97f59a5369bc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=467175058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixed
.467175058
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.1424235289
Short name T166
Test name
Test status
Simulation time 363329810903 ps
CPU time 60.8 seconds
Started Jun 13 02:31:46 PM PDT 24
Finished Jun 13 02:32:50 PM PDT 24
Peak memory 202268 kb
Host smart-18775b28-a081-4b30-a4a7-adfd4bcd99f6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424235289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.1424235289
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.3934906136
Short name T482
Test name
Test status
Simulation time 202054487879 ps
CPU time 228.63 seconds
Started Jun 13 02:31:45 PM PDT 24
Finished Jun 13 02:35:37 PM PDT 24
Peak memory 202212 kb
Host smart-9dc25556-39d0-416e-97b7-c8435157ff18
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934906136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.3934906136
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.2898621836
Short name T514
Test name
Test status
Simulation time 82350490057 ps
CPU time 437.96 seconds
Started Jun 13 02:31:54 PM PDT 24
Finished Jun 13 02:39:16 PM PDT 24
Peak memory 202528 kb
Host smart-12f5ac91-fd39-4752-9ffc-af95ae4aa8e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898621836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.2898621836
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.2145455217
Short name T555
Test name
Test status
Simulation time 24484848534 ps
CPU time 28.56 seconds
Started Jun 13 02:31:46 PM PDT 24
Finished Jun 13 02:32:18 PM PDT 24
Peak memory 202028 kb
Host smart-271f7ca2-5d4a-4b8d-94ab-ab20745c39e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145455217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.2145455217
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.3333955455
Short name T594
Test name
Test status
Simulation time 3983991431 ps
CPU time 9.91 seconds
Started Jun 13 02:31:38 PM PDT 24
Finished Jun 13 02:31:53 PM PDT 24
Peak memory 202064 kb
Host smart-6cabce1a-842b-49d1-9688-7c001b9d6b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333955455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.3333955455
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.4103312499
Short name T732
Test name
Test status
Simulation time 5527276418 ps
CPU time 7.19 seconds
Started Jun 13 02:31:34 PM PDT 24
Finished Jun 13 02:31:47 PM PDT 24
Peak memory 202068 kb
Host smart-8ecb822e-b981-449f-b93d-840f6cdf60b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103312499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.4103312499
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.533992636
Short name T682
Test name
Test status
Simulation time 420346648343 ps
CPU time 1305.88 seconds
Started Jun 13 02:31:51 PM PDT 24
Finished Jun 13 02:53:41 PM PDT 24
Peak memory 202592 kb
Host smart-5308e29c-f169-4c8f-afec-2f64761c2e47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533992636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.533992636
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.802007236
Short name T393
Test name
Test status
Simulation time 500122960 ps
CPU time 1.2 seconds
Started Jun 13 02:31:43 PM PDT 24
Finished Jun 13 02:31:49 PM PDT 24
Peak memory 201904 kb
Host smart-d8b0ff4b-17b4-45e6-bab9-d2611b1ee56a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802007236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.802007236
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.3939703661
Short name T105
Test name
Test status
Simulation time 328187250123 ps
CPU time 97.71 seconds
Started Jun 13 02:31:35 PM PDT 24
Finished Jun 13 02:33:18 PM PDT 24
Peak memory 202180 kb
Host smart-5ef900eb-968e-454f-ae7f-ae3f2fb34c73
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939703661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.3939703661
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.1705231183
Short name T549
Test name
Test status
Simulation time 340699599405 ps
CPU time 265.29 seconds
Started Jun 13 02:32:16 PM PDT 24
Finished Jun 13 02:36:49 PM PDT 24
Peak memory 202096 kb
Host smart-6d112429-7611-43e6-aeb0-e214b65b0638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705231183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.1705231183
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.1534931528
Short name T711
Test name
Test status
Simulation time 496118275932 ps
CPU time 1091.28 seconds
Started Jun 13 02:31:45 PM PDT 24
Finished Jun 13 02:50:00 PM PDT 24
Peak memory 202228 kb
Host smart-e491209f-e3c3-40ea-a9d1-96890cab81ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534931528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.1534931528
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.679541889
Short name T656
Test name
Test status
Simulation time 168088328378 ps
CPU time 360.03 seconds
Started Jun 13 02:31:52 PM PDT 24
Finished Jun 13 02:37:57 PM PDT 24
Peak memory 202112 kb
Host smart-48ee7028-8536-403f-9f4e-2cdaa785e507
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=679541889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt
_fixed.679541889
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.1367826036
Short name T160
Test name
Test status
Simulation time 495804752759 ps
CPU time 303.92 seconds
Started Jun 13 02:31:46 PM PDT 24
Finished Jun 13 02:36:54 PM PDT 24
Peak memory 202228 kb
Host smart-c45c5594-d018-4990-8f5c-db9e0ed4bce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367826036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.1367826036
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.3756956343
Short name T83
Test name
Test status
Simulation time 167580628817 ps
CPU time 211.89 seconds
Started Jun 13 02:31:43 PM PDT 24
Finished Jun 13 02:35:20 PM PDT 24
Peak memory 202172 kb
Host smart-5a233c0e-0327-48dc-b245-2d546b8d15c5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756956343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.3756956343
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.2606921413
Short name T226
Test name
Test status
Simulation time 357837720325 ps
CPU time 831.67 seconds
Started Jun 13 02:31:37 PM PDT 24
Finished Jun 13 02:45:34 PM PDT 24
Peak memory 202232 kb
Host smart-ad79191d-0c28-42d7-aa5f-0bc589b66364
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606921413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.2606921413
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.3063990126
Short name T345
Test name
Test status
Simulation time 603691844213 ps
CPU time 393.08 seconds
Started Jun 13 02:31:47 PM PDT 24
Finished Jun 13 02:38:23 PM PDT 24
Peak memory 202192 kb
Host smart-ad1a1088-838c-48f8-933b-b3ff4b1a0ab9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063990126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.3063990126
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.336857874
Short name T741
Test name
Test status
Simulation time 115866569641 ps
CPU time 418.79 seconds
Started Jun 13 02:31:31 PM PDT 24
Finished Jun 13 02:38:36 PM PDT 24
Peak memory 202500 kb
Host smart-524cd2d3-4da0-4bbb-8384-8749175bf3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336857874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.336857874
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.1559745718
Short name T331
Test name
Test status
Simulation time 41424033826 ps
CPU time 89.5 seconds
Started Jun 13 02:31:41 PM PDT 24
Finished Jun 13 02:33:15 PM PDT 24
Peak memory 202032 kb
Host smart-d601abe0-43a5-419b-8a41-346a9de458bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559745718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.1559745718
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.2761971652
Short name T30
Test name
Test status
Simulation time 4803459294 ps
CPU time 12.42 seconds
Started Jun 13 02:31:40 PM PDT 24
Finished Jun 13 02:31:57 PM PDT 24
Peak memory 202016 kb
Host smart-ddb57a70-87cc-4fc4-a2cc-2fc05dd992d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761971652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.2761971652
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.3101400815
Short name T365
Test name
Test status
Simulation time 5533998504 ps
CPU time 3.95 seconds
Started Jun 13 02:31:36 PM PDT 24
Finished Jun 13 02:31:46 PM PDT 24
Peak memory 202068 kb
Host smart-1ab6c305-6f0c-451c-a465-f3dfe5d87574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101400815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.3101400815
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.1384010812
Short name T758
Test name
Test status
Simulation time 324318327566 ps
CPU time 723.19 seconds
Started Jun 13 02:31:38 PM PDT 24
Finished Jun 13 02:43:46 PM PDT 24
Peak memory 213332 kb
Host smart-3fb48f5f-5a0a-45a7-addd-b854ffd02194
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384010812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
1384010812
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.4137542070
Short name T214
Test name
Test status
Simulation time 92255162015 ps
CPU time 104.63 seconds
Started Jun 13 02:31:38 PM PDT 24
Finished Jun 13 02:33:27 PM PDT 24
Peak memory 210876 kb
Host smart-ffe632c1-3d69-4036-a478-e26747ba2b7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137542070 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.4137542070
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.3038375516
Short name T739
Test name
Test status
Simulation time 414832788 ps
CPU time 0.94 seconds
Started Jun 13 02:31:50 PM PDT 24
Finished Jun 13 02:31:55 PM PDT 24
Peak memory 201864 kb
Host smart-a8b75485-560b-4509-a995-14ccb2cab478
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038375516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.3038375516
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.3323442683
Short name T215
Test name
Test status
Simulation time 203673266934 ps
CPU time 50.96 seconds
Started Jun 13 02:31:38 PM PDT 24
Finished Jun 13 02:32:34 PM PDT 24
Peak memory 202220 kb
Host smart-94f17dff-e05c-4b87-b976-981da29338d5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323442683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.3323442683
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.1850043560
Short name T293
Test name
Test status
Simulation time 163427757039 ps
CPU time 192.44 seconds
Started Jun 13 02:31:39 PM PDT 24
Finished Jun 13 02:34:56 PM PDT 24
Peak memory 202228 kb
Host smart-b99b75d6-5388-41c3-b3b1-e57ba5ca0f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850043560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.1850043560
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.1468304557
Short name T666
Test name
Test status
Simulation time 166423705576 ps
CPU time 392.33 seconds
Started Jun 13 02:31:44 PM PDT 24
Finished Jun 13 02:38:21 PM PDT 24
Peak memory 202188 kb
Host smart-7c41106f-5dc0-4e96-bb1c-d36e3fd8be50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468304557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.1468304557
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.3416225735
Short name T644
Test name
Test status
Simulation time 163553304296 ps
CPU time 369.36 seconds
Started Jun 13 02:31:38 PM PDT 24
Finished Jun 13 02:37:52 PM PDT 24
Peak memory 202240 kb
Host smart-b135cd5c-afde-4bcc-8fab-84c660760da3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416225735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.3416225735
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.3086096111
Short name T433
Test name
Test status
Simulation time 328985065129 ps
CPU time 502.15 seconds
Started Jun 13 02:31:50 PM PDT 24
Finished Jun 13 02:40:16 PM PDT 24
Peak memory 202168 kb
Host smart-d3ccaa04-4436-4eaf-9292-380dce28aee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086096111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.3086096111
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.3035174251
Short name T745
Test name
Test status
Simulation time 508276516076 ps
CPU time 1166.5 seconds
Started Jun 13 02:31:33 PM PDT 24
Finished Jun 13 02:51:05 PM PDT 24
Peak memory 202356 kb
Host smart-8368500f-a266-4768-a549-51abb7fb34a7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035174251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.3035174251
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.1755544087
Short name T674
Test name
Test status
Simulation time 291776271072 ps
CPU time 358.28 seconds
Started Jun 13 02:31:46 PM PDT 24
Finished Jun 13 02:37:47 PM PDT 24
Peak memory 202268 kb
Host smart-c30a3294-641d-4dad-8b29-e2ed07022489
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755544087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.1755544087
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.2978334691
Short name T409
Test name
Test status
Simulation time 415644952924 ps
CPU time 226.73 seconds
Started Jun 13 02:31:40 PM PDT 24
Finished Jun 13 02:35:31 PM PDT 24
Peak memory 202176 kb
Host smart-e4ada673-ea29-4a1a-aba8-8a426ee2459a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978334691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.2978334691
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.3627488474
Short name T775
Test name
Test status
Simulation time 86230518330 ps
CPU time 422.7 seconds
Started Jun 13 02:31:50 PM PDT 24
Finished Jun 13 02:38:56 PM PDT 24
Peak memory 202592 kb
Host smart-548e8a6d-9724-41b1-8738-8b9239e043d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627488474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.3627488474
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.1428956132
Short name T434
Test name
Test status
Simulation time 38858640529 ps
CPU time 22.49 seconds
Started Jun 13 02:31:53 PM PDT 24
Finished Jun 13 02:32:20 PM PDT 24
Peak memory 202064 kb
Host smart-3d1b413e-64c9-44f2-bcaa-31536a6c3dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428956132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.1428956132
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.2948336532
Short name T769
Test name
Test status
Simulation time 5004960584 ps
CPU time 6.78 seconds
Started Jun 13 02:31:37 PM PDT 24
Finished Jun 13 02:31:49 PM PDT 24
Peak memory 202052 kb
Host smart-5a31cf8e-ee00-406e-8d67-2e729e2d2bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948336532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.2948336532
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.2416123928
Short name T461
Test name
Test status
Simulation time 5805436866 ps
CPU time 13.84 seconds
Started Jun 13 02:31:44 PM PDT 24
Finished Jun 13 02:32:02 PM PDT 24
Peak memory 202040 kb
Host smart-d54c7abd-005d-4891-ab03-0789cf9b97ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416123928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.2416123928
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.3906888242
Short name T321
Test name
Test status
Simulation time 494364424405 ps
CPU time 676.84 seconds
Started Jun 13 02:31:45 PM PDT 24
Finished Jun 13 02:43:06 PM PDT 24
Peak memory 210712 kb
Host smart-7e332333-9bd4-4ed0-bf2a-58dbcabc8987
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906888242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
3906888242
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.2184961308
Short name T76
Test name
Test status
Simulation time 84616430529 ps
CPU time 106.05 seconds
Started Jun 13 02:31:46 PM PDT 24
Finished Jun 13 02:33:35 PM PDT 24
Peak memory 210832 kb
Host smart-f9d922fb-064a-4881-8f17-73ae10e9cf4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184961308 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.2184961308
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.3988146580
Short name T573
Test name
Test status
Simulation time 484475658 ps
CPU time 1.12 seconds
Started Jun 13 02:31:55 PM PDT 24
Finished Jun 13 02:32:01 PM PDT 24
Peak memory 202084 kb
Host smart-6b347a9b-05c7-4b87-b894-9274cd82d437
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988146580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.3988146580
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.473037358
Short name T256
Test name
Test status
Simulation time 360206624488 ps
CPU time 686.4 seconds
Started Jun 13 02:31:50 PM PDT 24
Finished Jun 13 02:43:21 PM PDT 24
Peak memory 202272 kb
Host smart-c55e16b3-c542-4b5f-873a-088c35a682f6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473037358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gatin
g.473037358
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.3160872645
Short name T537
Test name
Test status
Simulation time 164697549004 ps
CPU time 385.55 seconds
Started Jun 13 02:31:46 PM PDT 24
Finished Jun 13 02:38:15 PM PDT 24
Peak memory 202292 kb
Host smart-b1d4bc6d-8e89-4007-be91-212a8dafe1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160872645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.3160872645
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.2012444340
Short name T569
Test name
Test status
Simulation time 168985060147 ps
CPU time 192.69 seconds
Started Jun 13 02:32:01 PM PDT 24
Finished Jun 13 02:35:19 PM PDT 24
Peak memory 202116 kb
Host smart-73cb0b61-f2c4-4371-b082-621d7e88ad43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012444340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.2012444340
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.1168742539
Short name T346
Test name
Test status
Simulation time 164818682884 ps
CPU time 313.24 seconds
Started Jun 13 02:31:43 PM PDT 24
Finished Jun 13 02:37:01 PM PDT 24
Peak memory 202272 kb
Host smart-523e4188-0ae1-4e34-869f-30332300ff12
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168742539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.1168742539
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.3359298926
Short name T777
Test name
Test status
Simulation time 332415966069 ps
CPU time 219.59 seconds
Started Jun 13 02:31:50 PM PDT 24
Finished Jun 13 02:35:34 PM PDT 24
Peak memory 202228 kb
Host smart-2ad0c42d-5885-491b-9be8-240fa91a2411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359298926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.3359298926
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.4014585999
Short name T475
Test name
Test status
Simulation time 500678919095 ps
CPU time 525.51 seconds
Started Jun 13 02:31:52 PM PDT 24
Finished Jun 13 02:40:42 PM PDT 24
Peak memory 202112 kb
Host smart-38286175-94f9-47e8-a1b4-ab2686b9538f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014585999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.4014585999
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.2741651471
Short name T566
Test name
Test status
Simulation time 384884639800 ps
CPU time 217.27 seconds
Started Jun 13 02:31:50 PM PDT 24
Finished Jun 13 02:35:31 PM PDT 24
Peak memory 202164 kb
Host smart-86beac2f-8e9e-4671-84bf-ff485ffd579d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741651471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.2741651471
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.2427427333
Short name T615
Test name
Test status
Simulation time 204864698978 ps
CPU time 454.25 seconds
Started Jun 13 02:31:50 PM PDT 24
Finished Jun 13 02:39:28 PM PDT 24
Peak memory 202188 kb
Host smart-f34ed9a9-5763-4ab8-b464-18c00f52a41b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427427333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.2427427333
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.3984683534
Short name T619
Test name
Test status
Simulation time 106208908990 ps
CPU time 473.3 seconds
Started Jun 13 02:31:58 PM PDT 24
Finished Jun 13 02:39:56 PM PDT 24
Peak memory 202512 kb
Host smart-f5b48604-2e2a-4661-a014-09ce500412bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984683534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.3984683534
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.3952906423
Short name T329
Test name
Test status
Simulation time 28621400384 ps
CPU time 68.39 seconds
Started Jun 13 02:31:51 PM PDT 24
Finished Jun 13 02:33:03 PM PDT 24
Peak memory 201988 kb
Host smart-3d7ece31-98ae-41de-90b4-87c4397b0296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952906423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.3952906423
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.1304757973
Short name T706
Test name
Test status
Simulation time 5326012692 ps
CPU time 13.92 seconds
Started Jun 13 02:31:53 PM PDT 24
Finished Jun 13 02:32:11 PM PDT 24
Peak memory 202016 kb
Host smart-24a2870d-6b0c-43b5-8b19-585ba324c537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304757973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.1304757973
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.182532412
Short name T509
Test name
Test status
Simulation time 5868234962 ps
CPU time 4.21 seconds
Started Jun 13 02:31:48 PM PDT 24
Finished Jun 13 02:31:55 PM PDT 24
Peak memory 202052 kb
Host smart-5fdc4219-dc89-4e27-bb2c-aa6d269d1907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182532412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.182532412
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.4192805501
Short name T129
Test name
Test status
Simulation time 347552869381 ps
CPU time 87.25 seconds
Started Jun 13 02:31:55 PM PDT 24
Finished Jun 13 02:33:27 PM PDT 24
Peak memory 202224 kb
Host smart-328ef301-f0ca-4931-b0fa-898d8c63f69f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192805501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
4192805501
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.584568520
Short name T277
Test name
Test status
Simulation time 51693394156 ps
CPU time 252.54 seconds
Started Jun 13 02:31:53 PM PDT 24
Finished Jun 13 02:36:10 PM PDT 24
Peak memory 218120 kb
Host smart-c10ad42e-ab9f-49ef-b1df-7b5fc35a408e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584568520 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.584568520
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%