Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7304	1			T2	68		T3	3		T8	6
testmodes[AdcCtrlTestmodeNormal]	5646	1			T1	2		T2	17		T3	8
testmodes[AdcCtrlTestmodeLowpower]	5719	1			T2	38		T12	1		T45	1
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3946	1			T2	59		T8	2		T37	74
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1868	1			T2	4		T3	3		T8	3
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1360	1			T2	5		T37	10		T49	13
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1827	1			T2	5		T3	3		T8	4
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2099	1			T1	1		T2	8		T3	4
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1390	1			T2	3		T37	10		T49	18
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1408	1			T2	3		T37	10		T49	14
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1338	1			T2	5		T37	10		T49	17
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2736	1			T2	30		T53	9		T37	29