Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26533

1

T1

2

T2

157

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23274

1

T1

2

T2

157

T3

11

auto[ADC_CTRL_FILTER_COND_OUT]

3259

1

T5

12

T7

5

T10

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20633

1

T2

122

T3

11

T5

29

auto[1]

5900

1

T1

2

T2

35

T4

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22426

1

T1

2

T2

140

T3

11

auto[1]

4107

1

T2

17

T4

7

T5

32

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	7	1			T214	6		T215	1		-	-
values[0]	11	1			T155	1		T191	10		-	-
values[1]	651	1			T12	1		T38	7		T126	2
values[2]	2737	1			T1	2		T4	8		T10	1
values[3]	673	1			T10	1		T48	26		T116	14
values[4]	738	1			T5	18		T11	7		T127	3
values[5]	767	1			T2	33		T5	12		T114	1
values[6]	627	1			T7	8		T11	16		T37	4
values[7]	637	1			T5	27		T6	13		T10	1
values[8]	691	1			T2	2		T11	6		T37	2
values[9]	1208	1			T5	1		T7	5		T9	1
minimum	17786	1			T2	122		T3	11		T5	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	918	1			T38	7		T155	1		T126	2
values[1]	2724	1			T1	2		T4	8		T10	1
values[2]	626	1			T10	1		T11	7		T116	14
values[3]	781	1			T5	30		T114	1		T161	11
values[4]	719	1			T2	33		T37	4		T47	11
values[5]	560	1			T7	8		T11	16		T161	9
values[6]	667	1			T5	27		T6	13		T10	1
values[7]	642	1			T2	2		T5	1		T7	5
values[8]	917	1			T45	24		T114	1		T47	9
values[9]	187	1			T114	1		T26	24		T216	1
minimum	17792	1			T2	122		T3	11		T5	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22776

1

T1

2

T2

140

T3

11

auto[1]

3757

1

T2

17

T5

24

T6

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T155	1		T127	10		T117	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T38	4		T126	2		T124	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1378	1			T1	2		T4	1		T10	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T48	13		T13	7		T147	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T11	1		T122	18		T41	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T10	1		T116	1		T147	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T5	6		T114	1		T161	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T5	6		T127	3		T121	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T2	21		T37	3		T47	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T38	3		T120	1		T28	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T7	1		T116	1		T123	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T11	1		T161	1		T121	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T5	15		T6	11		T10	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T37	1		T189	14		T217	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T2	1		T5	1		T9	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T7	1		T151	8		T191	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T39	6		T115	1		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T45	16		T114	1		T47	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T114	1		T14	3		T218	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T26	12		T216	1		T219	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17629	1			T2	118		T3	11		T8	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T220	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T123	4		T130	1		T134	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T38	3		T124	22		T217	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1034	1			T4	7		T221	14		T23	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T48	15		T13	4		T147	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T11	6		T122	14		T41	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T116	13		T147	11		T222	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T5	12		T161	10		T116	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T5	6		T125	28		T223	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T2	12		T37	1		T125	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T38	1		T120	12		T28	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T7	7		T123	14		T15	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T11	15		T161	8		T224	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T5	12		T6	2		T37	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T217	7		T119	11		T17	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T2	1		T11	5		T46	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T7	4		T151	9		T225	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T39	2		T115	11		T137	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T45	8		T39	1		T151	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T14	1		T218	7		T183	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T26	12		T219	10		T226	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T2	4		T5	2		T37	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T220	1		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T214	1		T215	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T155	1		T191	10		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T12	1		T127	10		T117	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T38	4		T126	2		T124	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1369	1			T1	2		T4	1		T10	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T48	1		T13	7		T147	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T122	18		T41	9		T124	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T10	1		T48	12		T116	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T5	6		T11	1		T193	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T127	3		T121	1		T125	32
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T2	21		T114	1		T161	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T5	6		T38	3		T120	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T7	1		T37	3		T116	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T11	1		T137	1		T121	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T5	15		T6	11		T10	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T37	1		T161	1		T217	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T2	1		T11	1		T37	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T151	8		T191	12		T227	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T5	1		T9	1		T114	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	332	1			T7	1		T45	16		T114	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17628	1			T2	118		T3	11		T8	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T214	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T123	4		T130	1		T134	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T38	3		T124	22		T217	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1037	1			T4	7		T221	14		T23	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T48	1		T13	4		T147	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T122	14		T41	3		T124	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T48	14		T116	13		T147	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T5	12		T11	6		T193	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T125	28		T86	11		T90	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T2	12		T161	10		T116	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T5	6		T38	1		T120	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T7	7		T37	1		T123	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T11	15		T137	10		T119	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T5	12		T6	2		T26	23
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T161	8		T217	7		T119	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T2	1		T11	5		T37	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T151	9		T17	3		T63	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T39	2		T115	11		T137	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T7	4		T45	8		T39	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T2	4		T5	2		T37	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T155	1		T127	1		T117	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T38	5		T126	2		T124	23
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1371	1			T1	2		T4	8		T10	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T48	17		T13	8		T147	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T11	7		T122	15		T41	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T10	1		T116	14		T147	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T5	13		T114	1		T161	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T5	7		T127	1		T121	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T2	16		T37	2		T47	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T38	4		T120	13		T28	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T7	8		T116	1		T123	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T11	16		T161	9		T121	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T5	13		T6	3		T10	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T37	1		T189	1		T217	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T2	2		T5	1		T9	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T7	5		T151	10		T191	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T39	6		T115	12		T137	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T45	9		T114	1		T47	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T114	1		T14	3		T218	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T26	13		T216	1		T219	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17787	1			T2	122		T3	11		T5	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T220	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T127	9		T117	1		T123	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T38	2		T124	13		T217	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1041	1			T29	14		T228	15		T188	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T48	11		T13	3		T147	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T122	17		T41	6		T124	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T147	10		T141	18		T229	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T5	5		T230	10		T231	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T5	5		T127	2		T125	30
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T2	17		T37	2		T47	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T28	6		T158	13		T35	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T123	9		T15	3		T232	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T128	5		T224	12		T138	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	14		T6	10		T26	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T189	13		T217	6		T140	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T46	1		T28	11		T233	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T151	7		T191	11		T128	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T39	2		T130	11		T149	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T45	15		T47	8		T151	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T14	1		T181	13		T234	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T26	11		T235	7		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T220	1		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	8	40	83.33	8

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T214	6		T215	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T155	1		T191	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T12	1		T127	1		T117	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T38	5		T126	2		T124	23
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1374	1			T1	2		T4	8		T10	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T48	2		T13	8		T147	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T122	15		T41	6		T124	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T10	1		T48	15		T116	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T5	13		T11	7		T193	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T127	1		T121	1		T125	30
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T2	16		T114	1		T161	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T5	7		T38	4		T120	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T7	8		T37	2		T116	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T11	16		T137	11		T121	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T5	13		T6	3		T10	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T37	1		T161	9		T217	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T2	2		T11	6		T37	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T151	10		T191	1		T227	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	359	1			T5	1		T9	1		T114	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	358	1			T7	5		T45	9		T114	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17786	1			T2	122		T3	11		T5	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T191	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T127	9		T117	1		T123	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T38	2		T124	13		T217	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1032	1			T29	14		T228	15		T188	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T13	3		T147	7		T224	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T122	17		T41	6		T124	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T48	11		T147	10		T236	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T5	5		T140	8		T231	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T127	2		T125	30		T86	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T2	17		T47	10		T125	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T5	5		T28	6		T223	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T37	2		T123	9		T15	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T189	13		T138	2		T175	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T5	14		T6	10		T26	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T217	6		T128	14		T224	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T46	1		T28	11		T127	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T151	7		T191	11		T227	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T39	2		T130	11		T149	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T45	15		T47	8		T26	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22776

1

T1

2

T2

140

T3

11

auto[1]

auto[0]

3757

1

T2

17

T5

24

T6

10

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26533

1

T1

2

T2

157

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23026

1

T1

2

T2

157

T3

11

auto[ADC_CTRL_FILTER_COND_OUT]

3507

1

T5

28

T7

8

T9

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20714

1

T2

155

T3

11

T5

15

auto[1]

5819

1

T1

2

T2

2

T4

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22426

1

T1

2

T2

140

T3

11

auto[1]

4107

1

T2

17

T4

7

T5

32

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	10	1			T121	1		T237	9		-	-
values[0]	79	1			T222	15		T18	9		T238	9
values[1]	497	1			T2	2		T12	1		T37	2
values[2]	786	1			T5	27		T10	1		T114	1
values[3]	381	1			T11	7		T137	7		T117	2
values[4]	741	1			T2	33		T5	18		T10	1
values[5]	790	1			T116	12		T127	3		T41	12
values[6]	620	1			T7	8		T47	9		T48	2
values[7]	714	1			T5	12		T11	16		T47	11
values[8]	2838	1			T1	2		T4	8		T5	1
values[9]	1291	1			T6	13		T7	5		T9	1
minimum	17786	1			T2	122		T3	11		T5	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	818	1			T2	2		T10	1		T12	1
values[1]	702	1			T5	27		T114	1		T155	1
values[2]	391	1			T10	1		T11	7		T37	4
values[3]	837	1			T2	33		T5	18		T37	1
values[4]	668	1			T7	8		T28	22		T116	12
values[5]	642	1			T5	12		T47	20		T48	4
values[6]	2729	1			T1	2		T4	8		T11	16
values[7]	781	1			T5	1		T6	13		T11	6
values[8]	951	1			T7	5		T9	1		T10	1
values[9]	200	1			T127	10		T121	2		T149	27
minimum	17814	1			T2	122		T3	11		T5	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22776

1

T1

2

T2

140

T3

11

auto[1]

3757

1

T2

17

T5

24

T6

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T2	1		T12	1		T37	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T10	1		T114	1		T161	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T126	1		T137	1		T239	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T5	15		T114	1		T155	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T11	1		T39	6		T13	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T10	1		T37	3		T116	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T2	21		T5	6		T39	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T37	1		T38	3		T122	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T28	7		T125	19		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T7	1		T116	1		T127	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T5	6		T47	9		T48	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T47	11		T120	1		T41	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1394	1			T1	2		T4	1		T11	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T123	3		T130	1		T124	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T6	11		T11	1		T26	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T5	1		T45	16		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T7	1		T26	12		T151	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T9	1		T10	1		T46	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T127	10		T121	1		T149	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T121	1		T237	1		T240	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17628	1			T2	118		T3	11		T8	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T193	1		T241	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T2	1		T37	1		T147	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T161	8		T48	14		T119	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T137	3		T239	2		T134	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T5	12		T151	13		T156	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T11	6		T39	2		T13	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T37	1		T116	13		T137	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T2	12		T5	12		T39	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T38	1		T122	1		T147	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T28	15		T125	13		T242	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T7	7		T116	11		T217	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T5	6		T48	2		T27	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T120	12		T41	3		T130	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1027	1			T4	7		T11	15		T221	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T123	4		T130	1		T124	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T6	2		T11	5		T26	23
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T45	8		T137	10		T125	28
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T7	4		T26	12		T151	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T46	1		T161	10		T38	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T149	13		T220	1		T93	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T237	8		T243	20		T244	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T2	4		T5	2		T37	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T193	12		T241	7		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T121	1		T237	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T222	1		T18	6		T238	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T2	1		T12	1		T37	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T114	1		T161	1		T48	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T126	1		T217	7		T149	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T5	15		T10	1		T114	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T11	1		T137	1		T129	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T137	1		T117	2		T151	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T2	21		T5	6		T39	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T10	1		T37	4		T38	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T43	1		T242	1		T222	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T116	1		T127	3		T41	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T47	9		T48	1		T28	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T7	1		T120	1		T245	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T5	6		T11	1		T48	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T47	11		T130	12		T124	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1450	1			T1	2		T4	1		T11	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T5	1		T123	3		T130	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	363	1			T6	11		T7	1		T26	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	364	1			T9	1		T10	1		T45	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17628	1			T2	118		T3	11		T8	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T237	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T222	14		T18	3		T246	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T2	1		T37	1		T147	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T161	8		T48	14		T119	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T217	7		T149	6		T193	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T5	12		T134	2		T156	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T11	6		T137	3		T239	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T137	2		T151	13		T180	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T2	12		T5	12		T39	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T37	1		T38	1		T116	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T242	4		T222	15		T179	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T116	11		T41	3		T217	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T48	1		T28	15		T115	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T7	7		T120	12		T158	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T5	6		T11	15		T48	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T130	17		T124	5		T247	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1087	1			T4	7		T11	5		T221	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T123	4		T130	1		T125	28
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T6	2		T7	4		T26	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T45	8		T46	1		T161	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T2	4		T5	2		T37	3