Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26533

1

T1

2

T2

157

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23126

1

T1

2

T2

157

T3

11

auto[ADC_CTRL_FILTER_COND_OUT]

3407

1

T5

28

T7

8

T9

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20736

1

T2

155

T3

11

T5

15

auto[1]

5797

1

T1

2

T2

2

T4

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22426

1

T1

2

T2

140

T3

11

auto[1]

4107

1

T2

17

T4

7

T5

32

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	396	1			T7	5		T9	1		T46	3
values[0]	46	1			T222	15		T18	9		T246	22
values[1]	607	1			T2	2		T12	1		T37	2
values[2]	741	1			T5	27		T10	1		T114	1
values[3]	395	1			T11	7		T13	11		T116	14
values[4]	797	1			T2	33		T5	18		T10	1
values[5]	713	1			T116	12		T127	3		T41	12
values[6]	558	1			T7	8		T47	9		T48	2
values[7]	683	1			T5	12		T11	16		T47	11
values[8]	2922	1			T1	2		T4	8		T5	1
values[9]	889	1			T6	13		T10	1		T38	7
minimum	17786	1			T2	122		T3	11		T5	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	637	1			T2	2		T10	1		T12	1
values[1]	647	1			T5	27		T114	1		T155	1
values[2]	425	1			T10	1		T11	7		T39	8
values[3]	855	1			T2	33		T5	18		T37	5
values[4]	651	1			T28	22		T116	12		T127	3
values[5]	648	1			T5	12		T7	8		T47	20
values[6]	2713	1			T1	2		T4	8		T11	16
values[7]	746	1			T5	1		T6	13		T11	6
values[8]	1090	1			T7	5		T9	1		T10	1
values[9]	86	1			T46	3		T127	10		T121	1
minimum	18035	1			T2	122		T3	11		T5	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22776

1

T1

2

T2

140

T3

11

auto[1]

3757

1

T2

17

T5

24

T6

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T2	1		T12	1		T37	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T10	1		T114	1		T48	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T126	1		T137	1		T151	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T5	15		T114	1		T155	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T39	6		T13	7		T119	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T10	1		T11	1		T116	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T2	21		T5	6		T39	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T37	4		T38	3		T122	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T28	7		T125	19		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T116	1		T127	3		T41	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T5	6		T47	9		T48	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T7	1		T47	11		T120	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1384	1			T1	2		T4	1		T11	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T48	1		T130	1		T124	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T6	11		T11	1		T26	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T5	1		T45	16		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T7	1		T26	12		T151	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T9	1		T10	1		T161	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T127	10		T121	1		T310	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T46	2		T300	5		T249	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17682	1			T2	118		T3	11		T8	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T161	1		T216	1		T84	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T2	1		T37	1		T217	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T48	14		T119	11		T225	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T137	3		T151	13		T239	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T5	12		T285	16		T229	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T39	2		T13	4		T119	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T11	6		T116	13		T137	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T2	12		T5	12		T39	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T37	1		T38	1		T122	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T28	15		T125	13		T242	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T116	11		T41	3		T217	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T5	6		T48	1		T27	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T7	7		T120	12		T130	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1047	1			T4	7		T11	15		T221	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T48	1		T130	1		T124	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T6	2		T11	5		T26	23
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T45	8		T137	10		T123	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T7	4		T26	12		T151	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T161	10		T38	3		T44	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T93	4		T244	9		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T46	1		T300	7		T249	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T2	4		T5	2		T37	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T161	8		T84	1		T292	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T7	1		T26	12		T127	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T9	1		T46	2		T161	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T222	1		T18	6		T246	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T2	1		T12	1		T37	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T114	1		T161	1		T48	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T126	1		T217	7		T129	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T5	15		T10	1		T114	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T13	7		T137	1		T151	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T11	1		T116	1		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T2	21		T5	6		T39	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T10	1		T37	4		T38	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T242	1		T222	1		T254	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T116	1		T127	3		T41	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T47	9		T48	1		T28	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T7	1		T120	1		T245	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T5	6		T11	1		T27	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T47	11		T48	1		T130	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1471	1			T1	2		T4	1		T11	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T5	1		T45	16		T123	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T6	11		T121	1		T151	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T10	1		T38	4		T137	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17628	1			T2	118		T3	11		T8	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T7	4		T26	12		T253	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T46	1		T161	10		T44	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T222	14		T18	3		T246	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T2	1		T37	1		T147	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T161	8		T48	14		T119	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T217	7		T134	11		T193	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T5	12		T156	12		T285	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T13	4		T137	3		T151	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T11	6		T116	13		T137	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T2	12		T5	12		T39	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T37	1		T38	1		T122	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T242	4		T222	15		T252	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T116	11		T41	3		T217	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T48	1		T28	15		T125	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T7	7		T120	12		T232	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T5	6		T11	15		T27	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T48	1		T130	17		T124	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1121	1			T4	7		T11	5		T221	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T45	8		T123	4		T130	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T6	2		T151	9		T33	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T38	3		T137	10		T225	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T2	4		T5	2		T37	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T2	2		T12	1		T37	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T10	1		T114	1		T48	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T126	1		T137	4		T151	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T5	13		T114	1		T155	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T39	6		T13	8		T119	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T10	1		T11	7		T116	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T2	16		T5	13		T39	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T37	3		T38	4		T122	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T28	16		T125	14		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T116	12		T127	1		T41	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T5	7		T47	1		T48	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T7	8		T47	1		T120	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1374	1			T1	2		T4	8		T11	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T48	2		T130	2		T124	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T6	3		T11	6		T26	24
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T5	1		T45	9		T137	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T7	5		T26	13		T151	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T9	1		T10	1		T161	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T127	1		T121	1		T310	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T46	2		T300	8		T249	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17873	1			T2	122		T3	11		T5	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T161	9		T216	1		T84	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T217	6		T149	7		T177	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T48	11		T88	10		T14	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T151	14		T134	15		T170	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T5	14		T285	21		T229	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T39	2		T13	3		T34	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T117	1		T251	12		T274	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T2	17		T5	5		T225	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T37	2		T147	7		T223	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T28	6		T125	18		T245	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T127	2		T41	6		T217	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T5	5		T47	8		T122	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T47	10		T130	11		T263	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1057	1			T29	14		T228	15		T188	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T124	7		T247	14		T138	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T6	10		T26	15		T28	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T45	15		T123	2		T125	28
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T26	11		T151	7		T33	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T38	2		T233	1		T191	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T127	9		T181	13		T93	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T46	1		T300	4		T249	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T147	10		T123	9		T18	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T84	7		T229	12		T311	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T7	5		T26	13		T127	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T9	1		T46	2		T161	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T222	15		T18	5		T246	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T2	2		T12	1		T37	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T114	1		T161	9		T48	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T126	1		T217	8		T129	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T5	13		T10	1		T114	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T13	8		T137	4		T151	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T11	7		T116	14		T137	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T2	16		T5	13		T39	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T10	1		T37	3		T38	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T242	5		T222	16		T254	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T116	12		T127	1		T41	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T47	1		T48	2		T28	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T7	8		T120	13		T245	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T5	7		T11	16		T27	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T47	1		T48	2		T130	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1466	1			T1	2		T4	8		T11	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T5	1		T45	9		T123	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T6	3		T121	1		T151	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T10	1		T38	5		T137	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17786	1			T2	122		T3	11		T5	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T26	11		T127	9		T140	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T46	1		T233	1		T44	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T18	4		T246	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T147	10		T123	9		T149	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T48	11		T84	7		T88	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T217	6		T134	15		T177	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T5	14		T156	10		T285	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T13	3		T151	14		T34	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T117	1		T251	12		T141	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T2	17		T5	5		T39	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T37	2		T147	7		T223	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T252	10		T196	12		T253	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T127	2		T41	6		T217	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T47	8		T28	6		T125	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T245	1		T232	8		T158	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T5	5		T122	17		T223	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T47	10		T130	11		T124	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1126	1			T26	15		T28	11		T29	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T45	15		T123	2		T125	28
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T6	10		T151	7		T33	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T38	2		T191	9		T225	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22776

1

T1

2

T2

140

T3

11

auto[1]

auto[0]

3757

1

T2

17

T5

24

T6

10