Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26533

1

T1

2

T2

157

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23288

1

T1

2

T2

122

T3

11

auto[ADC_CTRL_FILTER_COND_OUT]

3245

1

T2

35

T5

1

T7

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20843

1

T2

124

T3

11

T5

2

auto[1]

5690

1

T1

2

T2

33

T4

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22426

1

T1

2

T2

140

T3

11

auto[1]

4107

1

T2

17

T4

7

T5

32

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	157	1			T10	1		T137	4		T127	7
values[0]	28	1			T151	28		-	-		-	-
values[1]	630	1			T6	13		T11	6		T37	4
values[2]	759	1			T2	33		T9	1		T47	11
values[3]	651	1			T5	27		T12	1		T46	3
values[4]	665	1			T7	5		T120	13		T121	1
values[5]	2788	1			T1	2		T4	8		T5	18
values[6]	619	1			T10	1		T37	2		T114	1
values[7]	717	1			T2	2		T5	12		T37	1
values[8]	722	1			T10	1		T48	2		T38	7
values[9]	1011	1			T5	1		T7	8		T11	16
minimum	17786	1			T2	122		T3	11		T5	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	746	1			T2	33		T47	9		T39	2
values[1]	575	1			T9	1		T11	6		T47	11
values[2]	643	1			T5	27		T7	5		T12	1
values[3]	2777	1			T1	2		T4	8		T267	2
values[4]	746	1			T5	18		T11	7		T37	2
values[5]	532	1			T10	1		T114	1		T13	11
values[6]	830	1			T2	2		T5	12		T10	1
values[7]	607	1			T5	1		T38	7		T116	26
values[8]	1002	1			T7	8		T11	16		T45	24
values[9]	68	1			T10	1		T127	7		T150	1
minimum	18007	1			T2	122		T3	11		T5	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22776

1

T1

2

T2

140

T3

11

auto[1]

3757

1

T2

17

T5

24

T6

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T27	1		T127	10		T123	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T2	21		T47	9		T39	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T9	1		T11	1		T121	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T47	11		T41	9		T245	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T5	15		T48	12		T26	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T7	1		T12	1		T46	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1464	1			T1	2		T4	1		T267	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T115	1		T147	8		T191	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T5	6		T37	1		T28	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T11	1		T126	1		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T179	1		T297	10		T274	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T10	1		T114	1		T13	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T5	6		T10	1		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T2	1		T37	1		T161	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T38	4		T127	3		T122	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T5	1		T116	2		T147	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T11	1		T45	16		T161	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T7	1		T114	1		T39	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T10	1		T127	7		T237	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T150	1		T129	1		T293	21
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17702	1			T2	118		T3	11		T6	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T37	3		T151	15		T33	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T27	10		T123	14		T44	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T2	12		T39	1		T296	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T11	5		T149	6		T223	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T41	3		T292	1		T252	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T5	12		T48	14		T26	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T7	4		T46	1		T90	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1053	1			T4	7		T38	1		T120	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T115	11		T147	6		T225	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T5	12		T37	1		T28	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T11	6		T130	1		T124	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T179	11		T274	5		T213	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T13	4		T122	1		T149	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T5	6		T48	1		T26	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T2	1		T161	10		T48	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T38	3		T122	14		T224	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T116	24		T147	11		T134	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T11	15		T45	8		T161	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T7	7		T39	2		T130	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T237	4		T312	5		T313	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T293	13		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T2	4		T5	2		T6	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T37	1		T151	13		T33	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T10	1		T137	1		T127	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T150	1		T128	1		T227	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T151	15		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T6	11		T11	1		T114	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T37	3		T47	9		T39	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T9	1		T121	1		T191	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T2	21		T47	11		T126	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T5	15		T48	12		T26	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T12	1		T46	2		T41	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T120	1		T121	1		T151	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T7	1		T147	8		T86	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1416	1			T1	2		T4	1		T5	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T11	1		T126	1		T115	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T37	1		T115	1		T125	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T10	1		T114	1		T155	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T5	6		T116	1		T125	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T2	1		T37	1		T161	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T10	1		T48	1		T38	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T116	1		T147	11		T217	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T11	1		T45	16		T161	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T5	1		T7	1		T114	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17628	1			T2	118		T3	11		T8	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T137	3		T272	8		T194	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T314	2		T290	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T151	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T6	2		T11	5		T27	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T37	1		T39	1		T33	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T149	6		T223	3		T44	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T2	12		T292	1		T252	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T5	12		T48	14		T26	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T46	1		T41	3		T90	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T120	12		T151	9		T124	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T7	4		T147	6		T138	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1060	1			T4	7		T5	12		T38	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T11	6		T115	11		T130	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T37	1		T115	2		T125	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T122	1		T124	22		T149	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T5	6		T125	13		T119	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T2	1		T161	10		T48	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T48	1		T38	3		T26	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T116	13		T147	11		T217	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T11	15		T45	8		T161	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T7	7		T39	2		T116	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T2	4		T5	2		T37	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T27	11		T127	1		T123	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T2	16		T47	1		T39	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T9	1		T11	6		T121	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T47	1		T41	6		T245	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T5	13		T48	15		T26	24
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T7	5		T12	1		T46	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1409	1			T1	2		T4	8		T267	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T115	12		T147	7		T191	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T5	13		T37	2		T28	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T11	7		T126	1		T130	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T179	12		T297	1		T274	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T10	1		T114	1		T13	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T5	7		T10	1		T48	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T2	2		T37	1		T161	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T38	5		T127	1		T122	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T5	1		T116	26		T147	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T11	16		T45	9		T161	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T7	8		T114	1		T39	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T10	1		T127	1		T237	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T150	1		T129	1		T293	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17854	1			T2	122		T3	11		T5	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T37	2		T151	14		T33	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T127	9		T123	9		T44	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T2	17		T47	8		T140	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T191	11		T149	7		T223	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T47	10		T41	6		T245	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T5	14		T48	11		T26	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T46	1		T90	6		T286	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1108	1			T29	14		T228	15		T151	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T147	7		T191	9		T225	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T5	5		T28	6		T233	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T124	13		T15	3		T170	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T297	9		T274	7		T213	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T13	3		T149	13		T88	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T5	5		T26	11		T125	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T217	23		T156	10		T177	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T38	2		T127	2		T122	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T147	10		T134	3		T34	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T45	15		T28	11		T123	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T39	2		T130	11		T189	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T127	6		T312	5		T313	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T293	20		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T6	10		T125	12		T253	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T37	2		T151	14		T33	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T10	1		T137	4		T127	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T150	1		T128	1		T227	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T151	14		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T6	3		T11	6		T114	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T37	2		T47	1		T39	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T9	1		T121	1		T191	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T2	16		T47	1		T126	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T5	13		T48	15		T26	24
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T12	1		T46	2		T41	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T120	13		T121	1		T151	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T7	5		T147	7		T86	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1401	1			T1	2		T4	8		T5	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T11	7		T126	1		T115	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T37	2		T115	3		T125	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T10	1		T114	1		T155	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T5	7		T116	1		T125	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T2	2		T37	1		T161	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T10	1		T48	2		T38	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T116	14		T147	12		T217	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T11	16		T45	9		T161	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	332	1			T5	1		T7	8		T114	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17786	1			T2	122		T3	11		T5	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T127	6		T163	9		T312	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T227	11		T315	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T151	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T6	10		T127	9		T123	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T37	2		T47	8		T33	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T191	11		T149	7		T223	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T2	17		T47	10		T245	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T5	14		T48	11		T26	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T46	1		T41	6		T90	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T151	7		T124	7		T128	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T147	7		T138	13		T162	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1075	1			T5	5		T28	6		T29	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T191	9		T225	11		T15	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T125	16		T297	9		T213	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T124	13		T149	13		T88	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T5	5		T125	18		T263	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T13	3		T217	7		T156	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T38	2		T26	11		T28	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T147	10		T217	16		T34	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T45	15		T123	2		T247	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T39	2		T130	11		T189	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22776

1

T1

2

T2

140

T3

11

auto[1]

auto[0]

3757

1

T2

17

T5

24

T6

10