Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26533

1

T1

2

T2

157

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23257

1

T1

2

T2

157

T3

11

auto[ADC_CTRL_FILTER_COND_OUT]

3276

1

T5

12

T7

5

T10

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20698

1

T2

122

T3

11

T5

29

auto[1]

5835

1

T1

2

T2

35

T4

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22426

1

T1

2

T2

140

T3

11

auto[1]

4107

1

T2

17

T4

7

T5

32

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	331	1			T114	1		T47	9		T33	20
values[0]	19	1			T191	10		T316	9		-	-
values[1]	689	1			T12	1		T38	7		T155	1
values[2]	2723	1			T1	2		T4	8		T10	1
values[3]	643	1			T10	1		T48	26		T116	14
values[4]	790	1			T5	18		T11	7		T161	11
values[5]	762	1			T2	33		T5	12		T114	1
values[6]	508	1			T7	8		T11	16		T37	4
values[7]	711	1			T5	27		T6	13		T10	1
values[8]	718	1			T2	2		T11	6		T37	2
values[9]	853	1			T5	1		T7	5		T9	1
minimum	17786	1			T2	122		T3	11		T5	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	749	1			T12	1		T126	2		T127	10
values[1]	2772	1			T1	2		T4	8		T10	1
values[2]	618	1			T10	1		T11	7		T116	14
values[3]	819	1			T2	33		T5	30		T114	1
values[4]	646	1			T37	4		T47	11		T38	4
values[5]	572	1			T7	8		T11	16		T161	9
values[6]	725	1			T5	27		T6	13		T10	1
values[7]	694	1			T2	2		T5	1		T7	5
values[8]	871	1			T9	1		T45	24		T114	1
values[9]	146	1			T114	1		T26	24		T14	4
minimum	17921	1			T2	122		T3	11		T5	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22776

1

T1

2

T2

140

T3

11

auto[1]

3757

1

T2

17

T5

24

T6

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T12	1		T127	10		T117	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T126	2		T124	14		T217	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1394	1			T1	2		T4	1		T10	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T48	13		T13	7		T147	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T11	1		T122	18		T41	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T10	1		T116	1		T147	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T2	21		T5	6		T114	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T5	6		T127	3		T121	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T37	3		T47	11		T125	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T38	3		T120	1		T28	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T7	1		T116	1		T123	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T11	1		T161	1		T121	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T5	15		T6	11		T10	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T37	1		T189	14		T217	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T2	1		T5	1		T11	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T7	1		T151	8		T191	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T9	1		T39	6		T115	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T45	16		T114	1		T47	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T114	1		T14	3		T218	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T26	12		T219	1		T140	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17661	1			T2	118		T3	11		T8	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T38	4		T34	1		T296	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T123	4		T134	12		T222	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T124	22		T217	12		T225	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1032	1			T4	7		T221	14		T23	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T48	15		T13	4		T147	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T11	6		T122	14		T41	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T116	13		T147	11		T222	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T2	12		T5	12		T161	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T5	6		T125	28		T223	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T37	1		T125	13		T225	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T38	1		T120	12		T28	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T7	7		T123	14		T15	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T11	15		T161	8		T119	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T5	12		T6	2		T26	23
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T217	7		T119	11		T239	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T2	1		T11	5		T37	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T7	4		T151	9		T247	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T39	2		T115	11		T137	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T45	8		T39	1		T151	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T14	1		T218	7		T183	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T26	12		T219	10		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T2	4		T5	2		T37	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T38	3		T34	1		T296	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T114	1		T14	3		T218	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T47	9		T33	10		T217	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T191	10		T316	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T12	1		T155	1		T127	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T38	4		T126	2		T124	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1386	1			T1	2		T4	1		T10	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T48	1		T13	7		T147	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T122	18		T41	9		T124	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T10	1		T48	12		T116	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T5	6		T11	1		T161	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T127	3		T121	1		T125	32
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T2	21		T114	1		T47	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T5	6		T38	3		T120	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T7	1		T37	3		T116	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T11	1		T121	1		T119	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T5	15		T6	11		T10	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T37	1		T161	1		T189	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T2	1		T11	1		T37	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T151	8		T191	12		T128	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T5	1		T9	1		T39	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T7	1		T45	16		T114	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17628	1			T2	118		T3	11		T8	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T14	1		T218	7		T295	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T33	10		T217	14		T219	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T316	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T123	4		T130	1		T134	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T38	3		T124	22		T217	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1030	1			T4	7		T221	14		T23	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T48	1		T13	4		T147	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T122	14		T41	3		T124	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T48	14		T116	13		T147	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T5	12		T11	6		T161	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T125	28		T223	13		T86	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T2	12		T116	11		T125	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T5	6		T38	1		T120	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T7	7		T37	1		T123	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T11	15		T119	7		T138	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T5	12		T6	2		T26	23
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T161	8		T217	7		T119	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T2	1		T11	5		T37	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T151	9		T17	3		T63	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T39	2		T115	11		T137	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T7	4		T45	8		T39	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T2	4		T5	2		T37	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T12	1		T127	1		T117	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T126	2		T124	23		T217	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1370	1			T1	2		T4	8		T10	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T48	17		T13	8		T147	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T11	7		T122	15		T41	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T10	1		T116	14		T147	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T2	16		T5	13		T114	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T5	7		T127	1		T121	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T37	2		T47	1		T125	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T38	4		T120	13		T28	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T7	8		T116	1		T123	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T11	16		T161	9		T121	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T5	13		T6	3		T10	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T37	1		T189	1		T217	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T2	2		T5	1		T11	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T7	5		T151	10		T191	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T9	1		T39	6		T115	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T45	9		T114	1		T47	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T114	1		T14	3		T218	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T26	13		T219	11		T140	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17832	1			T2	122		T3	11		T5	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T38	5		T34	2		T296	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T127	9		T117	1		T123	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T124	13		T217	7		T225	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1056	1			T29	14		T228	15		T124	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T48	11		T13	3		T147	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T122	17		T41	6		T149	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T147	10		T141	18		T229	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T2	17		T5	5		T230	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T5	5		T127	2		T125	30
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T37	2		T47	10		T125	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T28	6		T274	10		T158	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T123	9		T15	3		T175	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T224	12		T138	15		T175	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T5	14		T6	10		T26	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T189	13		T217	6		T128	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T46	1		T28	11		T233	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T151	7		T191	11		T247	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T39	2		T130	11		T149	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T45	15		T47	8		T151	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T14	1		T181	13		T234	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T26	11		T297	9		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T191	9		T317	4		T318	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T38	2		T306	6		T220	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T114	1		T14	3		T218	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T47	1		T33	11		T217	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T191	1		T316	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T12	1		T155	1		T127	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T38	5		T126	2		T124	23
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1367	1			T1	2		T4	8		T10	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T48	2		T13	8		T147	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T122	15		T41	6		T124	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T10	1		T48	15		T116	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T5	13		T11	7		T161	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T127	1		T121	1		T125	30
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T2	16		T114	1		T47	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T5	7		T38	4		T120	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T7	8		T37	2		T116	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T11	16		T121	1		T119	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T5	13		T6	3		T10	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T37	1		T161	9		T189	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T2	2		T11	6		T37	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T151	10		T191	1		T128	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T5	1		T9	1		T39	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T7	5		T45	9		T114	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17786	1			T2	122		T3	11		T5	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T14	1		T181	13		T184	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T47	8		T33	9		T217	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T191	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T127	9		T117	1		T123	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T38	2		T124	13		T217	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1049	1			T29	14		T228	15		T188	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T13	3		T147	7		T224	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T122	17		T41	6		T124	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T48	11		T147	10		T236	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T5	5		T230	10		T231	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T127	2		T125	30		T223	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T2	17		T47	10		T125	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T5	5		T28	6		T156	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T37	2		T123	9		T15	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T138	2		T175	3		T232	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T5	14		T6	10		T26	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T189	13		T217	6		T128	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T46	1		T28	11		T127	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T151	7		T191	11		T128	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T39	2		T130	11		T149	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T45	15		T26	11		T151	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22776

1

T1

2

T2

140

T3

11

auto[1]

auto[0]

3757

1

T2

17

T5

24

T6

10