Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26533

1

T1

2

T2

157

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21107

1

T2

122

T3

11

T5

42

auto[ADC_CTRL_FILTER_COND_OUT]

5426

1

T1

2

T2

35

T4

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20610

1

T2

157

T3

11

T5

47

auto[1]

5923

1

T1

2

T4

8

T5

13

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22426

1

T1

2

T2

140

T3

11

auto[1]

4107

1

T2

17

T4

7

T5

32

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	230	1			T121	1		T150	1		T239	3
values[0]	31	1			T231	17		T301	1		T273	11
values[1]	579	1			T28	22		T126	1		T137	11
values[2]	811	1			T2	2		T5	1		T9	1
values[3]	642	1			T5	12		T7	5		T11	7
values[4]	555	1			T37	5		T48	26		T38	4
values[5]	886	1			T10	1		T12	1		T45	24
values[6]	625	1			T2	33		T11	22		T161	9
values[7]	638	1			T5	18		T10	1		T47	9
values[8]	560	1			T37	2		T114	2		T47	11
values[9]	3190	1			T1	2		T4	8		T5	27
minimum	17786	1			T2	122		T3	11		T5	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	742	1			T9	1		T126	1		T115	3
values[1]	2764	1			T1	2		T2	2		T4	8
values[2]	651	1			T5	12		T7	5		T11	7
values[3]	489	1			T37	5		T161	11		T48	26
values[4]	903	1			T10	1		T12	1		T45	24
values[5]	640	1			T2	33		T5	18		T11	22
values[6]	605	1			T10	1		T47	20		T121	1
values[7]	814	1			T6	13		T7	8		T37	2
values[8]	756	1			T5	27		T10	1		T48	2
values[9]	155	1			T46	3		T227	12		T236	8
minimum	18014	1			T2	122		T3	11		T5	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22776

1

T1

2

T2

140

T3

11

auto[1]

3757

1

T2

17

T5

24

T6

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T9	1		T115	1		T122	18
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T126	1		T217	7		T162	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T5	1		T114	1		T39	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1438	1			T1	2		T2	1		T4	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T5	6		T7	1		T11	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T39	1		T233	2		T43	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T37	3		T38	3		T27	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T37	1		T161	1		T48	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T10	1		T12	1		T45	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T38	4		T127	10		T147	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T11	2		T161	1		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T2	21		T5	6		T121	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T47	20		T121	1		T119	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T10	1		T216	1		T223	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T7	1		T37	1		T114	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T6	11		T114	1		T120	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T5	15		T116	1		T118	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T10	1		T48	1		T13	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T46	2		T227	12		T307	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T236	8		T226	1		T182	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17689	1			T2	118		T3	11		T8	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T28	12		T137	1		T41	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T115	2		T122	14		T292	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T217	7		T274	9		T17	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T39	2		T28	15		T33	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1084	1			T2	1		T4	7		T48	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T5	6		T7	4		T11	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T39	1		T138	2		T194	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T37	1		T38	1		T27	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T161	10		T48	14		T151	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T45	8		T26	23		T125	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T38	3		T147	6		T125	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T11	20		T161	8		T137	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T2	12		T5	12		T147	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T119	7		T138	15		T239	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T223	13		T134	9		T222	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T7	7		T37	1		T116	24
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T6	2		T120	12		T122	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T5	12		T84	1		T239	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T48	1		T13	4		T137	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T46	1		T290	10		T154	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T226	16		T182	10		T282	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T2	4		T5	2		T37	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T28	10		T137	10		T41	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T239	1		T14	3		T219	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T121	1		T150	1		T236	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T231	3		T301	1		T273	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T122	18		T292	1		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T28	12		T126	1		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T5	1		T9	1		T114	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T2	1		T39	1		T123	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T5	6		T7	1		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T48	1		T233	2		T128	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T37	3		T38	3		T26	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T37	1		T48	12		T155	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T10	1		T12	1		T45	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T161	1		T38	4		T127	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T11	2		T161	1		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T2	21		T121	1		T147	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T47	9		T121	1		T191	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T5	6		T10	1		T223	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T37	1		T114	1		T47	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T114	1		T120	1		T216	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T5	15		T7	1		T46	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1586	1			T1	2		T4	1		T6	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17628	1			T2	118		T3	11		T8	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T239	2		T14	1		T219	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T230	11		T282	15		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T231	14		T273	9		T305	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T122	14		T292	1		T252	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T28	10		T137	10		T41	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T39	2		T28	15		T115	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T2	1		T39	1		T123	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T5	6		T7	4		T11	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T48	1		T272	8		T224	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T37	1		T38	1		T26	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T48	14		T151	9		T217	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T45	8		T26	23		T125	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T161	10		T38	3		T147	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T11	20		T161	8		T137	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T2	12		T147	11		T130	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T138	15		T239	4		T15	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T5	12		T223	13		T134	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T37	1		T116	13		T151	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T120	12		T90	7		T239	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T5	12		T7	7		T46	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1144	1			T4	7		T6	2		T48	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T2	4		T5	2		T37	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T9	1		T115	3		T122	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T126	1		T217	8		T162	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T5	1		T114	1		T39	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1425	1			T1	2		T2	2		T4	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T5	7		T7	5		T11	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T39	2		T233	1		T43	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T37	2		T38	4		T27	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T37	1		T161	11		T48	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T10	1		T12	1		T45	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T38	5		T127	1		T147	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T11	22		T161	9		T137	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T2	16		T5	13		T121	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T47	2		T121	1		T119	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T10	1		T216	1		T223	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T7	8		T37	2		T114	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T6	3		T114	1		T120	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T5	13		T116	1		T118	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T10	1		T48	2		T13	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T46	2		T227	1		T307	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T236	1		T226	17		T182	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17866	1			T2	122		T3	11		T5	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T28	11		T137	11		T41	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T122	17		T191	11		T140	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T217	6		T162	12		T274	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T39	2		T28	6		T127	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1097	1			T29	14		T228	15		T123	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T5	5		T26	11		T123	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T233	1		T128	9		T138	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T37	2		T117	1		T223	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T48	11		T151	7		T217	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T45	15		T26	15		T125	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T38	2		T127	9		T147	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T191	9		T306	6		T230	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T2	17		T5	5		T147	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T47	18		T138	13		T15	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T223	13		T134	12		T245	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T127	2		T151	14		T124	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T6	10		T189	13		T224	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T5	14		T84	7		T14	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T13	3		T247	14		T134	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T46	1		T227	11		T307	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T236	7		T282	19		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T252	10		T231	2		T286	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T28	11		T41	6		T140	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T239	3		T14	3		T219	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T121	1		T150	1		T236	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T231	15		T301	1		T273	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T122	15		T292	2		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T28	11		T126	1		T137	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T5	1		T9	1		T114	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T2	2		T39	2		T123	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T5	7		T7	5		T11	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T48	2		T233	1		T128	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T37	2		T38	4		T26	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T37	1		T48	15		T155	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T10	1		T12	1		T45	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T161	11		T38	5		T127	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T11	22		T161	9		T137	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T2	16		T121	1		T147	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T47	1		T121	1		T191	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T5	13		T10	1		T223	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T37	2		T114	1		T47	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T114	1		T120	13		T216	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T5	13		T7	8		T46	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1501	1			T1	2		T4	8		T6	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17786	1			T2	122		T3	11		T5	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T14	1		T213	2		T307	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T236	7		T319	2		T282	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T231	2		T273	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T122	17		T140	7		T252	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T28	11		T41	6		T140	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T39	2		T28	6		T127	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T123	9		T130	11		T217	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T5	5		T33	9		T123	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T233	1		T128	9		T224	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T37	2		T26	11		T86	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T48	11		T151	7		T217	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T45	15		T26	15		T117	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T38	2		T127	9		T147	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T230	10		T262	10		T64	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T2	17		T147	10		T125	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T47	8		T191	9		T138	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T5	5		T223	13		T134	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T47	10		T127	2		T151	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T90	6		T245	18		T274	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T5	14		T46	1		T84	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1229	1			T6	10		T13	3		T29	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22776

1

T1

2

T2

140

T3

11

auto[1]

auto[0]

3757

1

T2

17

T5

24

T6

10