Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26533

1

T1

2

T2

157

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23173

1

T1

2

T2

124

T3

11

auto[ADC_CTRL_FILTER_COND_OUT]

3360

1

T2

33

T5

18

T7

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21218

1

T2

122

T3

11

T5

29

auto[1]

5315

1

T1

2

T2

35

T4

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22426

1

T1

2

T2

140

T3

11

auto[1]

4107

1

T2

17

T4

7

T5

32

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	23	1			T218	11		T320	9		T168	1
values[0]	84	1			T161	11		T33	20		T159	1
values[1]	578	1			T2	33		T5	27		T7	8
values[2]	842	1			T48	2		T38	4		T155	1
values[3]	644	1			T2	2		T5	12		T11	6
values[4]	720	1			T48	2		T27	11		T126	1
values[5]	2834	1			T1	2		T4	8		T5	1
values[6]	563	1			T45	24		T114	1		T39	2
values[7]	540	1			T9	1		T127	17		T41	12
values[8]	637	1			T7	5		T37	4		T116	26
values[9]	1282	1			T5	18		T10	2		T114	2
minimum	17786	1			T2	122		T3	11		T5	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	743	1			T2	33		T5	27		T7	8
values[1]	889	1			T5	12		T38	4		T126	1
values[2]	614	1			T11	6		T37	3		T39	8
values[3]	2962	1			T1	2		T2	2		T4	8
values[4]	584	1			T5	1		T11	7		T12	1
values[5]	571	1			T45	24		T114	1		T39	2
values[6]	606	1			T9	1		T37	4		T116	14
values[7]	691	1			T7	5		T116	12		T127	7
values[8]	848	1			T5	18		T10	2		T114	2
values[9]	193	1			T119	12		T43	1		T224	25
minimum	17832	1			T2	122		T3	11		T5	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22776

1

T1

2

T2

140

T3

11

auto[1]

3757

1

T2

17

T5

24

T6

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T5	15		T10	1		T11	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T2	21		T7	1		T161	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T5	6		T125	17		T217	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T38	3		T126	1		T125	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T37	2		T27	1		T115	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T11	1		T39	6		T28	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1508	1			T1	2		T2	1		T4	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T122	1		T134	10		T17	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T5	1		T11	1		T13	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T12	1		T48	1		T126	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T137	1		T125	13		T134	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T45	16		T114	1		T39	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T37	3		T116	1		T121	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T9	1		T127	10		T233	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T7	1		T127	7		T122	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T116	1		T149	8		T225	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T10	1		T114	1		T47	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T5	6		T10	1		T114	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T43	1		T224	13		T232	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T119	1		T193	1		T240	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17628	1			T2	118		T3	11		T8	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T149	14		T35	10		T215	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T5	12		T11	15		T46	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T2	12		T7	7		T161	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T5	6		T125	13		T217	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T38	1		T125	13		T217	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T37	1		T27	10		T115	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T11	5		T39	2		T28	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1077	1			T2	1		T4	7		T6	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T122	1		T134	10		T285	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T11	6		T13	4		T115	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T48	1		T137	3		T151	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T137	10		T125	15		T134	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T45	8		T39	1		T124	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T37	1		T116	13		T124	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T41	3		T130	17		T34	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T7	4		T122	14		T119	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T116	11		T149	6		T225	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T48	14		T38	3		T28	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T5	12		T151	13		T138	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T224	12		T232	9		T274	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T119	11		T193	2		T240	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T2	4		T5	2		T37	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T149	13		T35	8		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T218	1		T168	1		T321	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T320	9		T265	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T159	1		T169	1		T322	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T161	1		T33	10		T323	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T5	15		T10	1		T11	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T2	21		T7	1		T47	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T48	1		T155	1		T116	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T38	3		T118	1		T191	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T2	1		T5	6		T37	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T11	1		T39	6		T28	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T27	1		T126	1		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T48	1		T225	1		T134	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1486	1			T1	2		T4	1		T5	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T12	1		T126	1		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T115	1		T137	1		T125	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T45	16		T114	1		T39	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T127	7		T124	8		T217	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T9	1		T127	10		T41	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T7	1		T37	3		T116	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T116	1		T225	3		T34	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	386	1			T10	1		T114	1		T47	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	361	1			T5	6		T10	1		T114	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17628	1			T2	118		T3	11		T8	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T218	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T169	8		T322	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T161	10		T33	10		T323	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T5	12		T11	15		T46	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T2	12		T7	7		T120	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T48	1		T147	6		T125	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T38	1		T217	12		T223	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T2	1		T5	6		T37	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T11	5		T39	2		T28	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T27	10		T223	13		T86	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T48	1		T225	10		T134	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1084	1			T4	7		T6	2		T11	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T137	3		T122	1		T151	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T115	2		T137	10		T125	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T45	8		T39	1		T124	22
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T124	5		T217	14		T222	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T41	3		T130	17		T274	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T7	4		T37	1		T116	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T116	11		T225	6		T34	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T48	14		T38	3		T28	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T5	12		T151	13		T119	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T2	4		T5	2		T37	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T5	13		T10	1		T11	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T2	16		T7	8		T161	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T5	7		T125	14		T217	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T38	4		T126	1		T125	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T37	3		T27	11		T115	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T11	6		T39	6		T28	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1419	1			T1	2		T2	2		T4	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T122	2		T134	11		T17	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T5	1		T11	7		T13	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T12	1		T48	2		T126	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T137	11		T125	16		T134	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T45	9		T114	1		T39	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T37	2		T116	14		T121	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T9	1		T127	1		T233	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T7	5		T127	1		T122	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T116	12		T149	7		T225	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T10	1		T114	1		T47	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T5	13		T10	1		T114	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T43	1		T224	13		T232	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T119	12		T193	3		T240	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17786	1			T2	122		T3	11		T5	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T149	14		T35	9		T215	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T5	14		T46	1		T26	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T2	17		T47	10		T33	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T5	5		T125	16		T217	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T125	18		T191	9		T217	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T128	5		T223	13		T162	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T39	2		T28	11		T225	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1166	1			T6	10		T26	11		T29	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T134	9		T285	21		T158	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T13	3		T86	11		T306	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T127	2		T151	7		T263	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T125	12		T134	3		T288	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T45	15		T117	1		T124	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T37	2		T124	7		T217	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T127	9		T233	1		T41	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T127	6		T122	17		T84	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T149	7		T225	2		T251	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T47	8		T48	11		T38	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T5	5		T151	14		T138	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T224	12		T232	8		T274	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T240	1		T324	24		T282	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T149	13		T35	9		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T218	11		T168	1		T321	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T320	1		T265	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T159	1		T169	9		T322	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T161	11		T33	11		T323	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T5	13		T10	1		T11	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T2	16		T7	8		T47	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T48	2		T155	1		T116	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T38	4		T118	1		T191	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T2	2		T5	7		T37	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T11	6		T39	6		T28	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T27	11		T126	1		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T48	2		T225	11		T134	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1425	1			T1	2		T4	8		T5	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T12	1		T126	1		T137	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T115	3		T137	11		T125	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T45	9		T114	1		T39	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T127	1		T124	6		T217	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T9	1		T127	1		T41	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T7	5		T37	2		T116	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T116	12		T225	7		T34	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	339	1			T10	1		T114	1		T47	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T5	13		T10	1		T114	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17786	1			T2	122		T3	11		T5	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T320	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T33	9		T323	13		T181	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T5	14		T46	1		T26	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T2	17		T47	10		T125	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T147	7		T125	16		T217	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T191	9		T217	7		T223	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T5	5		T189	13		T128	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T39	2		T28	11		T225	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T223	13		T86	11		T88	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T134	9		T285	21		T262	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1145	1			T6	10		T13	3		T26	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T127	2		T151	7		T170	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T125	12		T134	3		T306	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T45	15		T117	1		T233	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T127	6		T124	7		T217	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T127	9		T41	6		T130	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T37	2		T122	17		T90	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T225	2		T34	7		T251	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	324	1			T47	8		T48	11		T38	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T5	5		T151	14		T149	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22776

1

T1

2

T2

140

T3

11

auto[1]

auto[0]

3757

1

T2

17

T5

24

T6

10