Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26533

1

T1

2

T2

157

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22994

1

T1

2

T2

124

T3

11

auto[ADC_CTRL_FILTER_COND_OUT]

3539

1

T2

33

T5

18

T7

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21182

1

T2

122

T3

11

T5

41

auto[1]

5351

1

T1

2

T2

35

T4

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22426

1

T1

2

T2

140

T3

11

auto[1]

4107

1

T2

17

T4

7

T5

32

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	295	1			T5	18		T38	7		T121	1
values[0]	35	1			T161	11		T33	20		T159	1
values[1]	635	1			T2	33		T5	27		T7	8
values[2]	868	1			T48	2		T38	4		T116	1
values[3]	596	1			T5	12		T11	6		T37	3
values[4]	726	1			T2	2		T48	2		T27	11
values[5]	2846	1			T1	2		T4	8		T5	1
values[6]	575	1			T45	24		T114	1		T39	2
values[7]	508	1			T9	1		T116	14		T137	11
values[8]	707	1			T7	5		T37	4		T116	12
values[9]	956	1			T10	2		T114	2		T47	9
minimum	17786	1			T2	122		T3	11		T5	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	548	1			T2	33		T10	1		T11	16
values[1]	881	1			T5	12		T38	4		T121	1
values[2]	613	1			T11	6		T37	3		T39	8
values[3]	2901	1			T1	2		T2	2		T4	8
values[4]	649	1			T5	1		T6	13		T11	7
values[5]	543	1			T45	24		T114	1		T39	2
values[6]	629	1			T9	1		T37	4		T116	14
values[7]	681	1			T7	5		T47	9		T116	12
values[8]	893	1			T5	18		T10	2		T114	2
values[9]	159	1			T224	25		T193	3		T274	13
minimum	18036	1			T2	122		T3	11		T5	29

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22776

1

T1

2

T2

140

T3

11

auto[1]

3757

1

T2

17

T5

24

T6

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T10	1		T11	1		T48	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T2	21		T161	2		T126	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T5	6		T121	1		T125	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T38	3		T125	19		T191	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T37	2		T39	6		T115	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T11	1		T27	1		T28	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1447	1			T1	2		T2	1		T4	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T48	1		T122	1		T86	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T5	1		T6	11		T11	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T12	1		T137	1		T127	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T114	1		T137	1		T125	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T45	16		T39	1		T117	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T37	3		T116	1		T233	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T9	1		T127	17		T41	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T7	1		T47	9		T121	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T116	1		T149	8		T225	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T10	1		T114	1		T48	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T5	6		T10	1		T114	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T193	1		T274	11		T153	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T224	13		T240	3		T302	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17671	1			T2	118		T3	11		T5	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T7	1		T47	11		T120	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T11	15		T48	1		T137	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T2	12		T161	18		T223	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T5	6		T125	13		T44	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T38	1		T125	13		T217	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T37	1		T39	2		T115	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T11	5		T27	10		T28	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1072	1			T2	1		T4	7		T221	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T48	1		T122	1		T86	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T6	2		T11	6		T13	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T137	3		T151	9		T219	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T137	10		T125	15		T134	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T45	8		T39	1		T124	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T37	1		T116	13		T124	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T41	3		T130	17		T34	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T7	4		T122	14		T119	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T116	11		T149	6		T225	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T48	14		T38	3		T28	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T5	12		T151	13		T119	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T193	2		T274	2		T153	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T224	12		T240	1		T302	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T2	4		T5	14		T37	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T7	7		T120	12		T26	23

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T38	4		T247	15		T43	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T5	6		T121	1		T224	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T159	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T161	1		T33	10		T255	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T5	15		T10	1		T11	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T2	21		T7	1		T161	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T48	1		T116	1		T147	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T38	3		T118	1		T191	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T5	6		T37	2		T39	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T11	1		T28	12		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T2	1		T126	1		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T48	1		T27	1		T225	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1485	1			T1	2		T4	1		T5	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T12	1		T137	1		T127	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T114	1		T115	1		T125	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T45	16		T39	1		T117	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T116	1		T137	1		T233	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T9	1		T127	7		T41	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T7	1		T37	3		T121	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T116	1		T127	10		T225	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	316	1			T10	1		T114	1		T47	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T10	1		T114	1		T151	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17628	1			T2	118		T3	11		T8	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T38	3		T247	9		T15	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T5	12		T224	12		T138	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T161	10		T33	10		T257	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T5	12		T11	15		T46	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T2	12		T7	7		T161	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T48	1		T147	6		T125	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T38	1		T217	19		T223	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T5	6		T37	1		T39	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T11	5		T28	10		T130	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T2	1		T223	13		T88	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T48	1		T27	10		T225	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1095	1			T4	7		T6	2		T11	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T137	3		T122	1		T151	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T115	2		T125	15		T134	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T45	8		T39	1		T124	22
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T116	13		T137	10		T124	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T41	3		T130	17		T213	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T7	4		T37	1		T119	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T116	11		T225	6		T239	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T48	14		T28	15		T122	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T151	13		T119	11		T149	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T2	4		T5	2		T37	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T10	1		T11	16		T48	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T2	16		T161	20		T126	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T5	7		T121	1		T125	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T38	4		T125	14		T191	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T37	3		T39	6		T115	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T11	6		T27	11		T28	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1406	1			T1	2		T2	2		T4	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T48	2		T122	2		T86	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T5	1		T6	3		T11	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T12	1		T137	4		T127	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T114	1		T137	11		T125	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T45	9		T39	2		T117	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T37	2		T116	14		T233	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T9	1		T127	2		T41	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T7	5		T47	1		T121	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T116	12		T149	7		T225	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T10	1		T114	1		T48	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T5	13		T10	1		T114	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T193	3		T274	3		T153	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T224	13		T240	3		T302	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17813	1			T2	122		T3	11		T5	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T7	8		T47	1		T120	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T147	17		T123	2		T138	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T2	17		T223	6		T177	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T5	5		T125	16		T44	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T125	18		T191	9		T217	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T39	2		T189	13		T128	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T28	11		T225	11		T162	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1113	1			T26	11		T29	14		T228	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T86	11		T274	10		T285	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T6	10		T13	3		T134	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T127	2		T151	7		T263	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T125	12		T134	3		T288	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T45	15		T117	1		T124	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T37	2		T233	1		T124	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T127	15		T41	6		T130	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T47	8		T122	17		T90	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T149	7		T225	2		T84	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T48	11		T38	2		T28	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T5	5		T151	14		T138	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T274	10		T325	5		T326	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T224	12		T240	1		T324	24
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T5	14		T46	1		T213	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T47	10		T26	15		T33	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T38	5		T247	10		T43	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T5	13		T121	1		T224	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T159	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T161	11		T33	11		T255	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T5	13		T10	1		T11	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T2	16		T7	8		T161	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T48	2		T116	1		T147	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T38	4		T118	1		T191	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T5	7		T37	3		T39	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T11	6		T28	11		T130	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T2	2		T126	1		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T48	2		T27	11		T225	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1437	1			T1	2		T4	8		T5	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T12	1		T137	4		T127	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T114	1		T115	3		T125	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T45	9		T39	2		T117	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T116	14		T137	11		T233	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T9	1		T127	1		T41	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T7	5		T37	2		T121	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T116	12		T127	1		T225	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	312	1			T10	1		T114	1		T47	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T10	1		T114	1		T151	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17786	1			T2	122		T3	11		T5	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T38	2		T247	14		T15	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T5	5		T224	12		T138	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T33	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T5	14		T46	1		T147	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T2	17		T47	10		T26	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T147	7		T125	16		T44	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T191	9		T217	13		T223	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T5	5		T39	2		T189	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T28	11		T225	11		T170	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T223	13		T88	10		T139	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T86	11		T274	10		T285	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1143	1			T6	10		T13	3		T26	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T127	2		T151	7		T263	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T125	12		T134	3		T306	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T45	15		T117	1		T124	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T233	1		T124	7		T217	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T127	6		T41	6		T130	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T37	2		T90	6		T229	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T127	9		T225	2		T34	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T47	8		T48	11		T28	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T151	14		T149	7		T84	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22776

1

T1

2

T2

140

T3

11

auto[1]

auto[0]

3757

1

T2

17

T5

24

T6

10