Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26533

1

T1

2

T2

157

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23127

1

T1

2

T2

122

T3

11

auto[ADC_CTRL_FILTER_COND_OUT]

3406

1

T2

35

T5

57

T6

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20357

1

T2

154

T3

11

T5

14

auto[1]

6176

1

T1

2

T2

3

T4

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22426

1

T1

2

T2

140

T3

11

auto[1]

4107

1

T2

17

T4

7

T5

32

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	604	1			T2	1		T37	3		T49	1
values[0]	54	1			T147	14		T163	14		T327	21
values[1]	803	1			T37	1		T48	2		T39	8
values[2]	2659	1			T1	2		T4	8		T11	6
values[3]	819	1			T2	33		T10	1		T26	24
values[4]	521	1			T5	30		T161	9		T127	7
values[5]	536	1			T5	27		T11	16		T12	1
values[6]	585	1			T7	5		T9	1		T10	1
values[7]	835	1			T6	13		T45	24		T48	28
values[8]	545	1			T2	2		T10	1		T37	2
values[9]	1190	1			T5	1		T7	8		T114	1
minimum	17382	1			T2	121		T3	11		T5	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	798	1			T11	6		T37	1		T114	1
values[1]	2714	1			T1	2		T4	8		T161	11
values[2]	769	1			T2	33		T10	1		T121	1
values[3]	599	1			T5	57		T11	16		T12	1
values[4]	492	1			T46	3		T13	11		T115	3
values[5]	667	1			T7	5		T9	1		T10	1
values[6]	739	1			T6	13		T45	24		T27	11
values[7]	696	1			T2	2		T7	8		T10	1
values[8]	1008	1			T114	1		T47	9		T120	13
values[9]	96	1			T5	1		T147	22		T224	26
minimum	17955	1			T2	122		T3	11		T5	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22776

1

T1

2

T2

140

T3

11

auto[1]

3757

1

T2

17

T5

24

T6

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T11	1		T37	1		T48	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T114	1		T39	6		T121	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1402	1			T1	2		T4	1		T47	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T161	1		T28	12		T117	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T119	1		T43	1		T128	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T2	21		T10	1		T121	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T37	3		T137	1		T127	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T5	27		T11	1		T12	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T46	2		T115	1		T118	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T13	7		T116	1		T43	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T11	1		T39	1		T115	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T7	1		T9	1		T10	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T45	16		T126	1		T116	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T6	11		T27	1		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T38	4		T28	7		T123	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T2	1		T7	1		T10	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T114	1		T26	16		T126	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T47	9		T120	1		T125	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T5	1		T147	11		T224	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T181	14		T283	1		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17677	1			T2	118		T3	11		T8	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T246	1		T328	1		T327	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T11	5		T48	1		T217	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T39	2		T225	10		T193	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1001	1			T4	7		T38	1		T221	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T161	10		T28	10		T124	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T119	7		T272	8		T138	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T2	12		T41	3		T125	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T37	1		T137	3		T84	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T5	30		T11	15		T161	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T46	1		T115	2		T151	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T13	4		T116	11		T90	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T11	6		T39	1		T115	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T7	4		T48	15		T137	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T45	8		T116	13		T217	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T6	2		T27	10		T137	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T38	3		T28	15		T123	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T2	1		T7	7		T37	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T26	23		T151	9		T86	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T120	12		T125	13		T224	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T147	11		T224	11		T252	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T283	6		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T2	4		T5	2		T37	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T246	3		T327	11		T303	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	461	1			T2	1		T37	3		T49	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T181	14		T329	16		T328	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T147	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T163	3		T327	10		T289	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T37	1		T48	1		T217	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T39	6		T124	8		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1383	1			T1	2		T4	1		T11	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T114	1		T161	1		T28	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T26	12		T119	1		T43	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T2	21		T10	1		T121	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T127	7		T272	1		T129	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T5	12		T161	1		T266	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T37	3		T46	2		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T5	15		T11	1		T12	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T11	1		T39	1		T115	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T7	1		T9	1		T10	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T45	16		T126	1		T217	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T6	11		T48	13		T27	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T38	4		T28	7		T116	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T2	1		T10	1		T37	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T5	1		T114	1		T26	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	351	1			T7	1		T47	9		T120	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17224	1			T2	117		T3	11		T8	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T224	11		T138	2		T330	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T329	15		T331	10		T327	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T147	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T163	11		T327	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T48	1		T217	7		T223	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T39	2		T124	5		T225	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	995	1			T4	7		T11	5		T38	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T161	10		T28	10		T14	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T26	12		T119	7		T138	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T2	12		T41	3		T125	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T272	8		T156	12		T222	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T5	18		T161	8		T134	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T37	1		T46	1		T137	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T5	12		T11	15		T116	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T11	6		T39	1		T115	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T7	4		T13	4		T137	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T45	8		T217	12		T119	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T6	2		T48	15		T27	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T38	3		T28	15		T116	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T2	1		T37	1		T125	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T26	23		T147	11		T151	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T7	7		T120	12		T33	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T2	4		T5	2		T37	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T11	6		T37	1		T48	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T114	1		T39	6		T121	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1332	1			T1	2		T4	8		T47	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T161	11		T28	11		T117	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T119	8		T43	1		T128	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T2	16		T10	1		T121	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T37	2		T137	4		T127	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T5	33		T11	16		T12	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T46	2		T115	3		T118	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T13	8		T116	12		T43	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T11	7		T39	2		T115	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T7	5		T9	1		T10	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T45	9		T126	1		T116	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T6	3		T27	11		T137	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T38	5		T28	16		T123	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T2	2		T7	8		T10	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T114	1		T26	24		T126	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T47	1		T120	13		T125	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T5	1		T147	12		T224	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T181	1		T283	7		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17877	1			T2	122		T3	11		T5	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T246	4		T328	1		T327	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T217	6		T223	13		T44	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T39	2		T128	5		T274	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1071	1			T47	10		T26	11		T29	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T28	11		T117	1		T124	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T128	9		T138	13		T134	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T2	17		T41	6		T125	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T37	2		T127	6		T84	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T5	24		T127	9		T139	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T46	1		T151	14		T123	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T13	3		T90	6		T251	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T233	1		T217	16		T263	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T48	11		T127	2		T122	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T45	15		T217	7		T225	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T6	10		T247	14		T162	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T38	2		T28	6		T123	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T33	9		T130	11		T125	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T26	15		T151	7		T191	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T47	8		T125	18		T224	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T147	10		T224	14		T318	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T181	13		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T147	7		T248	15		T252	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T327	9		T289	4		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	457	1			T2	1		T37	3		T49	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T181	1		T329	16		T328	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T147	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T163	12		T327	12		T289	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T37	1		T48	2		T217	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T39	6		T124	6		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1323	1			T1	2		T4	8		T11	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T114	1		T161	11		T28	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T26	13		T119	8		T43	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T2	16		T10	1		T121	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T127	1		T272	9		T129	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T5	20		T161	9		T266	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T37	2		T46	2		T137	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T5	13		T11	16		T12	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T11	7		T39	2		T115	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T7	5		T9	1		T10	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T45	9		T126	1		T217	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T6	3		T48	17		T27	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T38	5		T28	16		T116	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T2	2		T10	1		T37	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	319	1			T5	1		T114	1		T26	24
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	332	1			T7	8		T47	1		T120	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17382	1			T2	121		T3	11		T5	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T224	14		T138	2		T330	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T181	13		T329	15		T331	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T147	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T163	2		T327	9		T289	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T217	6		T223	13		T44	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T39	2		T124	7		T128	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1055	1			T47	10		T29	14		T228	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T28	11		T117	1		T189	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T26	11		T128	9		T138	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T2	17		T41	6		T125	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T127	6		T156	10		T213	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T5	10		T134	3		T34	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T37	2		T46	1		T123	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T5	14		T127	9		T90	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T233	1		T151	14		T217	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T13	3		T127	2		T223	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T45	15		T217	7		T149	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T6	10		T48	11		T122	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T38	2		T28	6		T225	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T125	12		T191	9		T227	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T26	15		T147	10		T151	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T47	8		T33	9		T130	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22776

1

T1

2

T2

140

T3

11

auto[1]

auto[0]

3757

1

T2

17

T5

24

T6

10