Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T2	2		T12	1		T37	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T10	1		T114	1		T161	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T126	1		T137	4		T239	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T5	13		T114	1		T155	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T11	7		T39	6		T13	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T10	1		T37	2		T116	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T2	16		T5	13		T39	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T37	1		T38	4		T122	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T28	16		T125	14		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T7	8		T116	12		T127	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T5	7		T47	1		T48	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T47	1		T120	13		T41	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1355	1			T1	2		T4	8		T11	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T123	5		T130	2		T124	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T6	3		T11	6		T26	24
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T5	1		T45	9		T137	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T7	5		T26	13		T151	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T9	1		T10	1		T46	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T127	1		T121	1		T149	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T121	1		T237	9		T240	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17786	1			T2	122		T3	11		T5	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T193	13		T241	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T147	10		T123	9		T217	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T48	11		T84	7		T88	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T134	12		T170	12		T248	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T5	14		T151	14		T156	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T39	2		T13	3		T34	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T37	2		T117	1		T15	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T2	17		T5	5		T225	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T147	7		T223	13		T224	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T28	6		T125	18		T245	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T127	2		T217	7		T128	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T5	5		T47	8		T191	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T47	10		T41	6		T130	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1066	1			T29	14		T228	15		T122	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T123	2		T124	7		T247	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T6	10		T26	15		T28	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T45	15		T125	28		T225	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T26	11		T151	7		T33	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T46	1		T38	2		T233	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T127	9		T149	13		T181	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T240	1		T243	17		T249	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T241	7		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	8	40	83.33	8

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T121	1		T237	9		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T222	15		T18	5		T238	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T2	2		T12	1		T37	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T114	1		T161	9		T48	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T126	1		T217	8		T149	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T5	13		T10	1		T114	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T11	7		T137	4		T129	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T137	3		T117	1		T151	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T2	16		T5	13		T39	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T10	1		T37	3		T38	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T43	1		T242	5		T222	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T116	12		T127	1		T41	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T47	1		T48	2		T28	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T7	8		T120	13		T245	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T5	7		T11	16		T48	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T47	1		T130	18		T124	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1430	1			T1	2		T4	8		T11	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T5	1		T123	5		T130	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	342	1			T6	3		T7	5		T26	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	365	1			T9	1		T10	1		T45	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17786	1			T2	122		T3	11		T5	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T18	4		T238	8		T246	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T147	10		T123	9		T250	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T48	11		T84	7		T88	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T217	6		T149	7		T177	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T5	14		T134	3		T156	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T134	12		T34	7		T170	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T117	1		T151	14		T251	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T2	17		T5	5		T39	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T37	2		T147	7		T223	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T252	10		T196	12		T253	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T127	2		T41	6		T217	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T47	8		T28	6		T125	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T245	1		T158	13		T202	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T5	5		T122	17		T124	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T47	10		T130	11		T124	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1107	1			T26	15		T28	11		T29	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T123	2		T125	28		T134	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T6	10		T26	11		T127	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T45	15		T46	1		T38	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22776

1

T1

2

T2

140

T3

11

auto[1]

auto[0]

3757

1

T2

17

T5

24

T6

10