Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26533

1

T1

2

T2

157

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23207

1

T1

2

T2

124

T3

11

auto[ADC_CTRL_FILTER_COND_OUT]

3326

1

T2

33

T5

57

T10

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20760

1

T2

122

T3

11

T5

2

auto[1]

5773

1

T1

2

T2

35

T4

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22426

1

T1

2

T2

140

T3

11

auto[1]

4107

1

T2

17

T4

7

T5

32

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
values[0]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	192	1			T11	16		T114	1		T121	1
values[1]	857	1			T2	33		T5	12		T7	5
values[2]	709	1			T114	1		T115	3		T122	2
values[3]	565	1			T11	7		T12	1		T46	3
values[4]	2960	1			T1	2		T4	8		T45	24
values[5]	744	1			T37	3		T114	1		T13	11
values[6]	682	1			T5	19		T9	1		T48	2
values[7]	626	1			T7	8		T161	9		T48	26
values[8]	594	1			T10	1		T47	9		T39	2
values[9]	818	1			T2	2		T5	27		T6	13
minimum	17786	1			T2	122		T3	11		T5	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	799	1			T2	33		T5	12		T7	5
values[1]	752	1			T114	1		T115	3		T116	14
values[2]	569	1			T11	7		T12	1		T46	3
values[3]	3002	1			T1	2		T4	8		T45	24
values[4]	725	1			T37	2		T114	1		T27	11
values[5]	676	1			T5	19		T9	1		T48	28
values[6]	511	1			T7	8		T161	9		T38	4
values[7]	657	1			T10	1		T11	6		T47	9
values[8]	745	1			T2	2		T5	27		T11	16
values[9]	92	1			T6	13		T10	1		T191	10
minimum	18005	1			T2	122		T3	11		T5	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22776

1

T1

2

T2

140

T3

11

auto[1]

3757

1

T2

17

T5

24

T6

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T7	1		T137	1		T151	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T2	21		T5	6		T10	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T127	10		T147	8		T129	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T114	1		T115	1		T116	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T46	2		T48	1		T126	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T11	1		T12	1		T138	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1503	1			T1	2		T4	1		T45	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T26	16		T137	1		T121	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T37	1		T28	12		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T114	1		T27	1		T126	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T5	1		T9	1		T48	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T5	6		T28	7		T225	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T7	1		T124	8		T216	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T161	1		T38	3		T39	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T11	1		T47	9		T122	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T10	1		T39	1		T120	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T2	1		T37	3		T114	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T5	15		T11	1		T121	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T6	11		T254	1		T255	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T10	1		T191	10		T256	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17685	1			T2	118		T3	11		T8	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T193	1		T170	13		T159	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T7	4		T137	3		T151	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T2	12		T5	6		T161	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T147	6		T177	10		T237	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T115	2		T116	13		T122	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T46	1		T48	1		T116	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T11	6		T138	15		T239	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1131	1			T4	7		T45	8		T221	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T26	23		T137	2		T217	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T37	1		T28	10		T137	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T27	10		T134	9		T170	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T48	15		T38	3		T123	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T5	12		T28	15		T225	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T7	7		T124	5		T222	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T161	8		T38	1		T39	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T11	5		T122	14		T147	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T39	1		T120	12		T41	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T2	1		T37	1		T115	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T5	12		T11	15		T223	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T6	2		T257	14		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T258	1		T259	13		T260	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T2	4		T5	2		T37	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T193	12		T170	10		T261	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T114	1		T225	12		T175	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T11	1		T121	1		T256	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T7	1		T47	11		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T2	21		T5	6		T10	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T147	8		T129	1		T223	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T114	1		T115	1		T122	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T46	2		T48	1		T126	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T11	1		T12	1		T116	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1503	1			T1	2		T4	1		T45	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T137	1		T217	24		T119	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T37	2		T13	7		T26	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T114	1		T26	16		T126	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T5	1		T9	1		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T5	6		T27	1		T43	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T7	1		T48	12		T123	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T161	1		T38	3		T39	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T47	9		T122	18		T147	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T10	1		T39	1		T120	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T2	1		T6	11		T11	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T5	15		T10	1		T191	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17628	1			T2	118		T3	11		T8	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T225	13		T175	2		T218	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T11	15		T250	15		T153	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T7	4		T137	3		T151	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T2	12		T5	6		T161	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T147	6		T223	3		T177	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T115	2		T122	1		T217	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T46	1		T48	1		T116	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T11	6		T116	13		T151	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1155	1			T4	7		T45	8		T221	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T137	2		T217	21		T119	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T37	1		T13	4		T26	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T26	23		T119	11		T170	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T48	1		T38	3		T125	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T5	12		T27	10		T224	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T7	7		T48	14		T123	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T161	8		T38	1		T39	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T122	14		T147	11		T225	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T39	1		T120	12		T41	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T2	1		T6	2		T11	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T5	12		T223	13		T138	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T2	4		T5	2		T37	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T7	5		T137	4		T151	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T2	16		T5	7		T10	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T127	1		T147	7		T129	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T114	1		T115	3		T116	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T46	2		T48	2		T126	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T11	7		T12	1		T138	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1478	1			T1	2		T4	8		T45	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T26	24		T137	3		T121	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T37	2		T28	11		T137	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T114	1		T27	11		T126	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T5	1		T9	1		T48	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T5	13		T28	16		T225	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T7	8		T124	6		T216	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T161	9		T38	4		T39	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T11	6		T47	1		T122	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T10	1		T39	2		T120	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T2	2		T37	2		T114	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T5	13		T11	16		T121	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T6	3		T254	1		T255	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T10	1		T191	1		T256	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17835	1			T2	122		T3	11		T5	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T193	13		T170	11		T159	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T151	14		T125	34		T223	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T2	17		T5	5		T130	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T127	9		T147	7		T177	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T151	7		T217	7		T128	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T46	1		T88	10		T17	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T138	13		T232	8		T262	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1156	1			T45	15		T13	3		T26	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T26	15		T217	22		T90	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T28	11		T127	2		T123	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T117	1		T134	12		T236	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T48	11		T38	2		T233	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T5	5		T28	6		T224	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T124	7		T245	1		T251	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T39	2		T33	9		T252	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T47	8		T122	17		T147	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T41	6		T134	9		T156	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T37	2		T225	11		T44	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T5	14		T191	11		T263	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T6	10		T257	12		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T191	9		T162	10		T259	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T47	10		T34	7		T264	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T170	12		T261	1		T181	3

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	*	--	--	2
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T114	1		T225	14		T175	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T11	16		T121	1		T256	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T7	5		T47	1		T137	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T2	16		T5	7		T10	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T147	7		T129	1		T223	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T114	1		T115	3		T122	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T46	2		T48	2		T126	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T11	7		T12	1		T116	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1500	1			T1	2		T4	8		T45	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T137	3		T217	23		T119	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T37	3		T13	8		T26	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T114	1		T26	24		T126	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T5	1		T9	1		T48	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T5	13		T27	11		T43	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T7	8		T48	15		T123	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T161	9		T38	4		T39	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T47	1		T122	15		T147	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T10	1		T39	2		T120	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T2	2		T6	3		T11	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T5	13		T10	1		T191	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17786	1			T2	122		T3	11		T5	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T225	11		T175	1		T257	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T162	10		T250	4		T153	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T47	10		T151	14		T125	34
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T2	17		T5	5		T130	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T147	7		T223	6		T177	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T217	7		T149	13		T175	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T46	1		T127	9		T88	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T151	7		T128	9		T138	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1158	1			T45	15		T29	14		T127	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T217	22		T90	6		T196	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T13	3		T26	11		T28	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T26	15		T117	1		T236	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T38	2		T233	1		T125	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T5	5		T224	12		T134	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T48	11		T123	9		T124	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T39	2		T28	6		T33	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T47	8		T122	17		T147	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T41	6		T134	9		T156	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T6	10		T37	2		T124	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T5	14		T191	20		T263	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22776

1

T1

2

T2

140

T3

11

auto[1]

auto[0]

3757

1

T2

17

T5

24

T6

10