Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26533

1

T1

2

T2

157

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23254

1

T1

2

T2

124

T3

11

auto[ADC_CTRL_FILTER_COND_OUT]

3279

1

T2

33

T5

57

T10

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20768

1

T2

122

T3

11

T5

2

auto[1]

5765

1

T1

2

T2

35

T4

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22426

1

T1

2

T2

140

T3

11

auto[1]

4107

1

T2

17

T4

7

T5

32

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	6	1			T175	6		-	-		-	-
values[0]	32	1			T47	11		T275	10		T276	3
values[1]	839	1			T2	33		T5	12		T7	5
values[2]	686	1			T114	1		T122	2		T147	14
values[3]	607	1			T11	7		T12	1		T48	2
values[4]	2898	1			T1	2		T4	8		T45	24
values[5]	776	1			T37	3		T114	1		T13	11
values[6]	646	1			T5	19		T9	1		T48	2
values[7]	667	1			T7	8		T161	9		T48	26
values[8]	559	1			T10	1		T47	9		T39	2
values[9]	1031	1			T2	2		T5	27		T6	13
minimum	17786	1			T2	122		T3	11		T5	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	956	1			T2	33		T5	12		T7	5
values[1]	811	1			T114	1		T115	3		T116	14
values[2]	616	1			T11	7		T12	1		T45	24
values[3]	2964	1			T1	2		T4	8		T37	1
values[4]	677	1			T37	2		T114	1		T27	11
values[5]	705	1			T5	19		T9	1		T48	28
values[6]	530	1			T7	8		T161	9		T38	4
values[7]	614	1			T10	1		T11	6		T47	9
values[8]	735	1			T2	2		T5	27		T11	16
values[9]	131	1			T6	13		T10	1		T121	1
minimum	17794	1			T2	122		T3	11		T5	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22776

1

T1

2

T2

140

T3

11

auto[1]

3757

1

T2

17

T5

24

T6

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T7	1		T47	11		T137	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T2	21		T5	6		T10	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T127	10		T147	8		T129	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T114	1		T115	1		T116	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T45	16		T46	2		T48	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T11	1		T12	1		T138	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1489	1			T1	2		T4	1		T37	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T26	16		T137	1		T121	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T37	1		T28	12		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T114	1		T27	1		T126	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T5	1		T9	1		T48	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T5	6		T28	7		T33	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T7	1		T124	8		T216	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T161	1		T38	3		T39	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T11	1		T47	9		T122	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T10	1		T120	1		T263	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T2	1		T37	3		T114	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T5	15		T11	1		T39	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T6	11		T277	1		T254	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T10	1		T121	1		T191	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17628	1			T2	118		T3	11		T8	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T278	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T7	4		T137	3		T151	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T2	12		T5	6		T161	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T147	6		T177	10		T237	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T115	2		T116	13		T122	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T45	8		T46	1		T48	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T11	6		T138	15		T239	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1125	1			T4	7		T221	14		T13	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T26	23		T137	2		T217	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T37	1		T28	10		T137	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T27	10		T134	9		T170	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T48	15		T38	3		T123	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T5	12		T28	15		T33	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T7	7		T124	5		T239	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T161	8		T38	1		T39	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T11	5		T122	14		T147	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T120	12		T138	2		T134	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T2	1		T37	1		T115	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T5	12		T11	15		T39	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T6	2		T257	14		T279	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T179	4		T280	1		T259	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T2	4		T5	2		T37	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T175	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T47	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T275	1		T276	1		T278	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T7	1		T137	1		T151	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T2	21		T5	6		T10	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T147	8		T129	1		T223	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T114	1		T122	1		T217	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T48	1		T126	1		T116	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T11	1		T12	1		T116	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1463	1			T1	2		T4	1		T45	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T217	24		T43	2		T90	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T37	2		T13	7		T26	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T114	1		T26	16		T126	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T5	1		T9	1		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T5	6		T27	1		T43	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T7	1		T48	12		T122	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T161	1		T38	3		T39	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T47	9		T147	11		T216	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T10	1		T39	1		T120	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T2	1		T6	11		T11	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T5	15		T10	1		T11	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17628	1			T2	118		T3	11		T8	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T175	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T275	9		T276	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T7	4		T137	3		T151	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T2	12		T5	6		T161	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T147	6		T223	3		T177	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T122	1		T217	12		T149	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T48	1		T116	11		T88	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T11	6		T116	13		T137	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1120	1			T4	7		T45	8		T46	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T217	21		T90	7		T237	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T37	1		T13	4		T26	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T26	23		T119	14		T34	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T48	1		T38	3		T137	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T5	12		T27	10		T224	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T7	7		T48	14		T122	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T161	8		T38	1		T39	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T147	11		T225	6		T239	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T39	1		T120	12		T41	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T2	1		T6	2		T11	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T5	12		T11	15		T223	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T2	4		T5	2		T37	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T7	5		T47	1		T137	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T2	16		T5	7		T10	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T127	1		T147	7		T129	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T114	1		T115	3		T116	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T45	9		T46	2		T48	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T11	7		T12	1		T138	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1468	1			T1	2		T4	8		T37	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T26	24		T137	3		T121	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T37	2		T28	11		T137	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T114	1		T27	11		T126	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T5	1		T9	1		T48	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T5	13		T28	16		T33	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T7	8		T124	6		T216	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T161	9		T38	4		T39	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T11	6		T47	1		T122	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T10	1		T120	13		T263	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T2	2		T37	2		T114	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T5	13		T11	16		T39	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T6	3		T277	1		T254	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T10	1		T121	1		T191	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17786	1			T2	122		T3	11		T5	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T278	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T47	10		T151	14		T125	34
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T2	17		T5	5		T149	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T127	9		T147	7		T177	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T151	7		T130	11		T217	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T45	15		T46	1		T88	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T138	13		T232	8		T262	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1146	1			T13	3		T26	11		T29	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T26	15		T217	22		T90	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T28	11		T123	2		T149	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T117	1		T134	12		T236	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T48	11		T38	2		T233	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T5	5		T28	6		T33	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T124	7		T245	1		T251	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T39	2		T252	20		T35	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T47	8		T122	17		T147	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T263	7		T138	2		T134	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T37	2		T225	11		T44	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T5	14		T41	6		T191	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T6	10		T257	12		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T191	9		T162	10		T181	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T278	7		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T175	5		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T47	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T275	10		T276	3		T278	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T7	5		T137	4		T151	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T2	16		T5	7		T10	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T147	7		T129	1		T223	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T114	1		T122	2		T217	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T48	2		T126	1		T116	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T11	7		T12	1		T116	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1458	1			T1	2		T4	8		T45	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T217	23		T43	2		T90	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T37	3		T13	8		T26	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T114	1		T26	24		T126	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T5	1		T9	1		T48	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T5	13		T27	11		T43	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T7	8		T48	15		T122	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T161	9		T38	4		T39	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T47	1		T147	12		T216	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T10	1		T39	2		T120	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T2	2		T6	3		T11	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	347	1			T5	13		T10	1		T11	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17786	1			T2	122		T3	11		T5	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T175	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T47	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T278	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T151	14		T125	34		T84	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T2	17		T5	5		T130	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T147	7		T223	6		T177	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T217	7		T149	13		T175	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T127	9		T88	10		T281	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T151	7		T128	9		T138	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1125	1			T45	15		T46	1		T29	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T217	22		T90	6		T196	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T13	3		T26	11		T28	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T26	15		T117	1		T236	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T38	2		T233	1		T125	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T5	5		T224	12		T134	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T48	11		T122	17		T123	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T39	2		T28	6		T33	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T47	8		T147	10		T225	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T41	6		T134	9		T156	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T6	10		T37	2		T124	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T5	14		T191	20		T263	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22776

1

T1

2

T2

140

T3

11

auto[1]

auto[0]

3757

1

T2

17

T5

24

T6

10