Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26533

1

T1

2

T2

157

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23078

1

T1

2

T2

124

T3

11

auto[ADC_CTRL_FILTER_COND_OUT]

3455

1

T2

33

T5

58

T6

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20626

1

T2

121

T3

11

T5

59

auto[1]

5907

1

T1

2

T2

36

T4

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22426

1

T1

2

T2

140

T3

11

auto[1]

4107

1

T2

17

T4

7

T5

32

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	417	1			T2	1		T37	3		T49	1
values[0]	96	1			T48	2		T147	14		T128	6
values[1]	711	1			T37	1		T39	8		T124	13
values[2]	2816	1			T1	2		T2	33		T4	8
values[3]	711	1			T10	1		T26	24		T121	1
values[4]	469	1			T5	12		T161	9		T266	1
values[5]	593	1			T5	45		T11	16		T12	1
values[6]	599	1			T7	5		T9	1		T10	1
values[7]	789	1			T45	24		T48	28		T27	11
values[8]	645	1			T2	2		T6	13		T10	1
values[9]	1305	1			T5	1		T7	8		T114	1
minimum	17382	1			T2	121		T3	11		T5	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	966	1			T11	6		T37	1		T114	1
values[1]	2735	1			T1	2		T4	8		T161	11
values[2]	728	1			T2	33		T10	1		T121	1
values[3]	537	1			T5	57		T11	16		T12	1
values[4]	512	1			T46	3		T13	11		T115	3
values[5]	702	1			T7	5		T9	1		T10	1
values[6]	723	1			T6	13		T45	24		T27	11
values[7]	764	1			T2	2		T7	8		T37	2
values[8]	830	1			T10	1		T114	1		T47	9
values[9]	215	1			T5	1		T126	1		T147	22
minimum	17821	1			T2	122		T3	11		T5	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22776

1

T1

2

T2

140

T3

11

auto[1]

3757

1

T2

17

T5

24

T6

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T11	1		T37	1		T47	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T114	1		T48	1		T39	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1430	1			T1	2		T4	1		T267	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T161	1		T28	12		T124	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T10	1		T121	1		T43	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T2	21		T41	9		T125	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T37	3		T116	1		T127	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T5	27		T11	1		T12	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T115	1		T151	15		T222	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T46	2		T13	7		T116	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T11	1		T39	1		T126	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T7	1		T9	1		T10	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T45	16		T225	12		T88	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T6	11		T27	1		T116	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T2	1		T7	1		T37	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T114	1		T28	7		T33	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T10	1		T114	1		T120	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T47	9		T125	19		T128	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T126	1		T147	11		T191	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T5	1		T224	15		T239	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17628	1			T2	118		T3	11		T8	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T282	20		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T11	5		T147	6		T217	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T48	1		T39	2		T225	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1040	1			T4	7		T38	1		T221	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T161	10		T28	10		T124	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T272	8		T138	15		T15	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T2	12		T41	3		T125	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T37	1		T84	1		T242	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T5	30		T11	15		T161	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T115	2		T151	13		T222	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T46	1		T13	4		T116	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T11	6		T39	1		T115	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T7	4		T48	15		T137	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T45	8		T225	13		T88	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T6	2		T27	10		T116	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T2	1		T7	7		T37	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T28	15		T33	10		T123	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T120	12		T26	23		T151	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T125	13		T224	12		T193	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T147	11		T138	2		T252	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T224	11		T239	4		T283	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T2	4		T5	2		T37	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T282	15		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	407	1			T2	1		T37	3		T49	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T147	8		T179	1		T231	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T48	1		T128	6		T163	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T37	1		T217	7		T216	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T39	6		T124	8		T225	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1420	1			T1	2		T4	1		T11	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T2	21		T114	1		T161	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T10	1		T26	12		T121	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T41	9		T125	17		T134	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T272	1		T129	1		T156	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T5	6		T161	1		T266	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T37	3		T116	1		T127	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T5	21		T11	1		T12	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T11	1		T39	1		T115	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T7	1		T9	1		T10	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T45	16		T126	1		T122	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T48	13		T27	1		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T2	1		T10	1		T37	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T6	11		T114	1		T28	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	348	1			T7	1		T114	1		T120	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	384	1			T5	1		T47	9		T33	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17224	1			T2	117		T3	11		T8	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T219	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T147	6		T179	4		T231	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T48	1		T163	11		T284	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T217	7		T44	2		T226	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T39	2		T124	5		T225	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1016	1			T4	7		T11	5		T38	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T2	12		T161	10		T28	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T26	12		T119	7		T138	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T41	3		T125	13		T134	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T272	8		T156	12		T262	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T5	6		T161	8		T134	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T37	1		T84	1		T242	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T5	24		T11	15		T46	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T11	6		T39	1		T115	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T7	4		T13	4		T137	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T45	8		T122	14		T217	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T48	15		T27	10		T137	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T2	1		T37	1		T38	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T6	2		T28	15		T116	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	336	1			T7	7		T120	12		T26	23
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T33	10		T123	14		T130	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T2	4		T5	2		T37	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T11	6		T37	1		T47	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T114	1		T48	2		T39	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1382	1			T1	2		T4	8		T267	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T161	11		T28	11		T124	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T10	1		T121	1		T43	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T2	16		T41	6		T125	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T37	2		T116	1		T127	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T5	33		T11	16		T12	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T115	3		T151	14		T222	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T46	2		T13	8		T116	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T11	7		T39	2		T126	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T7	5		T9	1		T10	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T45	9		T225	14		T88	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T6	3		T27	11		T116	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T2	2		T7	8		T37	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T114	1		T28	16		T33	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T10	1		T114	1		T120	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T47	1		T125	14		T128	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T126	1		T147	12		T191	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T5	1		T224	12		T239	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17786	1			T2	122		T3	11		T5	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T282	16		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T47	10		T147	7		T217	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T39	2		T128	5		T223	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1088	1			T26	11		T29	14		T117	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T28	11		T124	7		T189	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T138	13		T15	3		T262	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T2	17		T41	6		T125	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T37	2		T127	6		T84	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T5	24		T127	9		T134	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T151	14		T285	21		T286	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T46	1		T13	3		T123	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T233	1		T122	17		T217	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T48	11		T127	2		T263	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T45	15		T225	11		T88	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T6	10		T217	7		T17	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T38	2		T124	13		T134	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T28	6		T33	9		T123	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T26	15		T151	7		T86	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T47	8		T125	18		T224	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T147	10		T191	11		T138	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T224	14		T287	17		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T282	19		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	417	1			T2	1		T37	3		T49	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T147	7		T179	5		T231	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T48	2		T128	1		T163	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T37	1		T217	8		T216	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T39	6		T124	6		T225	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1354	1			T1	2		T4	8		T11	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T2	16		T114	1		T161	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T10	1		T26	13		T121	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T41	6		T125	14		T134	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T272	9		T129	1		T156	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T5	7		T161	9		T266	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T37	2		T116	1		T127	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T5	26		T11	16		T12	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T11	7		T39	2		T115	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T7	5		T9	1		T10	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T45	9		T126	1		T122	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T48	17		T27	11		T137	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T2	2		T10	1		T37	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T6	3		T114	1		T28	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	407	1			T7	8		T114	1		T120	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T5	1		T47	1		T33	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17382	1			T2	121		T3	11		T5	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T147	7		T231	2		T288	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T128	5		T163	2		T289	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T217	6		T44	2		T248	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T39	2		T124	7		T223	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1082	1			T47	10		T29	14		T117	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T2	17		T28	11		T189	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T26	11		T138	13		T15	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T41	6		T125	16		T134	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T156	10		T262	7		T141	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T5	5		T128	9		T134	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T37	2		T127	6		T84	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T5	19		T46	1		T127	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T233	1		T151	14		T232	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T13	3		T127	2		T263	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T45	15		T122	17		T217	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T48	11		T217	7		T227	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T38	2		T124	13		T88	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T6	10		T28	6		T125	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T26	15		T147	10		T151	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T47	8		T33	9		T123	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22776

1

T1

2

T2

140

T3

11

auto[1]

auto[0]

3757

1

T2

17

T5

24

T6

10