Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26533

1

T1

2

T2

157

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23333

1

T1

2

T2

122

T3

11

auto[ADC_CTRL_FILTER_COND_OUT]

3200

1

T2

35

T5

1

T7

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20762

1

T2

124

T3

11

T5

2

auto[1]

5771

1

T1

2

T2

33

T4

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22426

1

T1

2

T2

140

T3

11

auto[1]

4107

1

T2

17

T4

7

T5

32

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	24	1			T227	12		T290	10		T243	1
values[0]	74	1			T37	4		T127	10		T291	3
values[1]	616	1			T6	13		T11	6		T114	1
values[2]	726	1			T2	33		T9	1		T47	11
values[3]	656	1			T5	27		T12	1		T46	3
values[4]	657	1			T7	5		T120	13		T121	1
values[5]	2697	1			T1	2		T4	8		T5	18
values[6]	691	1			T10	1		T37	2		T114	1
values[7]	736	1			T2	2		T5	12		T10	1
values[8]	653	1			T7	8		T48	4		T38	7
values[9]	1217	1			T5	1		T10	1		T11	16
minimum	17786	1			T2	122		T3	11		T5	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	971	1			T2	33		T6	13		T37	4
values[1]	610	1			T5	27		T9	1		T11	6
values[2]	605	1			T7	5		T12	1		T46	3
values[3]	2774	1			T1	2		T4	8		T267	2
values[4]	710	1			T5	18		T11	7		T37	2
values[5]	640	1			T10	1		T114	1		T13	11
values[6]	724	1			T2	2		T5	12		T10	1
values[7]	645	1			T5	1		T116	26		T127	3
values[8]	916	1			T7	8		T11	16		T45	24
values[9]	136	1			T10	1		T127	7		T150	1
minimum	17802	1			T2	122		T3	11		T5	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22776

1

T1

2

T2

140

T3

11

auto[1]

3757

1

T2

17

T5

24

T6

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T6	11		T114	1		T27	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T2	21		T37	3		T47	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T5	15		T9	1		T11	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T47	11		T41	9		T245	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T48	12		T26	16		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T7	1		T12	1		T46	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1437	1			T1	2		T4	1		T267	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T115	1		T147	8		T191	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T5	6		T37	1		T28	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T11	1		T126	1		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T125	19		T119	1		T179	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T10	1		T114	1		T13	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T5	6		T10	1		T48	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T2	1		T37	1		T161	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T127	3		T42	1		T129	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T5	1		T116	2		T147	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T11	1		T45	16		T161	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T7	1		T114	1		T39	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T10	1		T127	7		T239	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T150	1		T129	1		T239	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17636	1			T2	118		T3	11		T8	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T6	2		T27	10		T123	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T2	12		T37	1		T39	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T5	12		T11	5		T149	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T41	3		T292	1		T252	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T48	14		T26	23		T137	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T7	4		T46	1		T90	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1034	1			T4	7		T38	1		T120	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T115	11		T147	6		T225	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T5	12		T37	1		T28	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T11	6		T130	1		T124	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T125	13		T119	3		T179	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T13	4		T122	1		T149	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T5	6		T48	1		T38	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T2	1		T161	10		T48	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T224	12		T239	2		T218	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T116	24		T147	11		T130	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T11	15		T45	8		T161	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T7	7		T39	2		T119	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T239	4		T237	4		T252	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T239	12		T293	13		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T2	4		T5	2		T37	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T294	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T227	12		T290	1		T243	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T127	10		T291	1		T295	26
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T37	3		T166	1		T169	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T6	11		T11	1		T114	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T47	9		T39	1		T126	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T9	1		T121	1		T191	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T2	21		T47	11		T126	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T5	15		T48	12		T26	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T12	1		T46	2		T41	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T120	1		T121	1		T151	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T7	1		T147	8		T86	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1381	1			T1	2		T4	1		T5	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T11	1		T126	1		T115	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T37	1		T28	7		T115	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T10	1		T114	1		T155	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T5	6		T10	1		T116	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T2	1		T37	1		T161	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T48	1		T38	4		T26	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T7	1		T48	1		T147	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	351	1			T10	1		T11	1		T45	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T5	1		T114	1		T39	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17628	1			T2	118		T3	11		T8	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T290	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T291	2		T295	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T37	1		T166	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T6	2		T11	5		T27	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T39	1		T151	13		T33	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T223	3		T44	2		T134	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T2	12		T252	14		T296	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T5	12		T48	14		T26	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T46	1		T41	3		T90	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T120	12		T151	9		T124	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T7	4		T147	6		T219	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1004	1			T4	7		T5	12		T38	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T11	6		T115	11		T130	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T37	1		T28	15		T115	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T122	1		T124	22		T149	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T5	6		T125	13		T175	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T2	1		T161	10		T13	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T48	1		T38	3		T26	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T7	7		T48	1		T147	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T11	15		T45	8		T161	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T39	2		T116	24		T130	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T2	4		T5	2		T37	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T6	3		T114	1		T27	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T2	16		T37	2		T47	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T5	13		T9	1		T11	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T47	1		T41	6		T245	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T48	15		T26	24		T137	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T7	5		T12	1		T46	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1386	1			T1	2		T4	8		T267	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T115	12		T147	7		T191	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T5	13		T37	2		T28	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T11	7		T126	1		T130	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T125	14		T119	4		T179	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T10	1		T114	1		T13	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T5	7		T10	1		T48	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T2	2		T37	1		T161	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T127	1		T42	1		T129	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T5	1		T116	26		T147	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T11	16		T45	9		T161	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T7	8		T114	1		T39	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T10	1		T127	1		T239	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T150	1		T129	1		T239	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17795	1			T2	122		T3	11		T5	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T6	10		T127	9		T123	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T2	17		T37	2		T47	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T5	14		T191	11		T149	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T47	10		T41	6		T245	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T48	11		T26	15		T117	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T46	1		T90	6		T286	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1085	1			T29	14		T228	15		T151	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T147	7		T191	9		T225	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T5	5		T28	6		T233	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T124	13		T15	3		T170	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T125	18		T297	9		T274	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T13	3		T149	13		T88	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T5	5		T38	2		T26	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T217	23		T156	10		T177	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T127	2		T224	12		T286	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T147	10		T130	11		T134	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T45	15		T28	11		T122	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T39	2		T189	13		T227	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T127	6		T252	10		T163	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T293	20		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T298	7		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T294	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T227	1		T290	10		T243	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T127	1		T291	3		T295	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T37	2		T166	7		T169	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T6	3		T11	6		T114	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T47	1		T39	2		T126	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T9	1		T121	1		T191	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T2	16		T47	1		T126	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T5	13		T48	15		T26	24
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T12	1		T46	2		T41	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T120	13		T121	1		T151	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T7	5		T147	7		T86	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1346	1			T1	2		T4	8		T5	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T11	7		T126	1		T115	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T37	2		T28	16		T115	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T10	1		T114	1		T155	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T5	7		T10	1		T116	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T2	2		T37	1		T161	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T48	2		T38	5		T26	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T7	8		T48	2		T147	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	375	1			T10	1		T11	16		T45	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	356	1			T5	1		T114	1		T39	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17786	1			T2	122		T3	11		T5	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T227	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T127	9		T295	25		T299	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T37	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T6	10		T123	9		T125	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T47	8		T151	14		T33	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T191	11		T223	6		T44	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T2	17		T47	10		T245	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T5	14		T48	11		T26	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T46	1		T41	6		T90	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T151	7		T124	7		T128	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T147	7		T162	10		T230	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1039	1			T5	5		T29	14		T228	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T191	9		T225	11		T138	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T28	6		T125	16		T285	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T124	13		T149	13		T88	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T5	5		T125	18		T175	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T13	3		T217	7		T156	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T38	2		T26	11		T28	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T147	10		T217	16		T34	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T45	15		T127	6		T122	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T39	2		T130	11		T189	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22776

1

T1

2

T2

140

T3

11

auto[1]

auto[0]

3757

1

T2

17

T5

24

T6

10