Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26533

1

T1

2

T2

157

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21078

1

T2

122

T3

11

T5

42

auto[ADC_CTRL_FILTER_COND_OUT]

5455

1

T1

2

T2

35

T4

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20590

1

T2

157

T3

11

T5

47

auto[1]

5943

1

T1

2

T4

8

T5

13

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22426

1

T1

2

T2

140

T3

11

auto[1]

4107

1

T2

17

T4

7

T5

32

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	26	1			T137	4		T300	22		-	-
values[0]	44	1			T41	12		T301	1		T302	17
values[1]	529	1			T28	22		T126	1		T137	11
values[2]	836	1			T2	2		T9	1		T114	1
values[3]	613	1			T5	13		T7	5		T11	7
values[4]	681	1			T37	4		T48	26		T38	4
values[5]	741	1			T10	1		T12	1		T45	24
values[6]	680	1			T2	33		T11	6		T161	9
values[7]	646	1			T5	18		T10	1		T11	16
values[8]	528	1			T37	2		T114	2		T47	11
values[9]	3423	1			T1	2		T4	8		T5	27
minimum	17786	1			T2	122		T3	11		T5	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	975	1			T9	1		T28	22		T126	1
values[1]	2754	1			T1	2		T2	2		T4	8
values[2]	673	1			T5	12		T7	5		T11	7
values[3]	469	1			T37	5		T161	11		T48	26
values[4]	896	1			T10	1		T11	6		T12	1
values[5]	609	1			T2	33		T5	18		T11	16
values[6]	610	1			T10	1		T47	20		T121	1
values[7]	722	1			T6	13		T7	8		T37	2
values[8]	802	1			T5	27		T48	2		T13	11
values[9]	226	1			T10	1		T46	3		T137	4
minimum	17797	1			T2	122		T3	11		T5	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22776

1

T1

2

T2

140

T3

11

auto[1]

3757

1

T2

17

T5

24

T6

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T9	1		T115	1		T122	18
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T28	12		T126	1		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T5	1		T114	1		T39	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1463	1			T1	2		T2	1		T4	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T5	6		T7	1		T11	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T39	1		T233	2		T151	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T37	3		T38	3		T27	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T37	1		T161	1		T48	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T10	1		T11	1		T12	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T38	4		T127	10		T147	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T11	1		T161	1		T191	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T2	21		T5	6		T121	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T47	20		T121	1		T119	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T10	1		T216	1		T223	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T7	1		T37	1		T114	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T6	11		T114	1		T120	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T5	15		T116	1		T118	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T48	1		T13	7		T126	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T46	2		T227	12		T219	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T10	1		T137	1		T236	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17628	1			T2	118		T3	11		T8	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T303	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T115	2		T122	14		T292	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T28	10		T137	10		T41	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T39	2		T28	15		T33	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1099	1			T2	1		T4	7		T48	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T5	6		T7	4		T11	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T39	1		T151	9		T138	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T37	1		T38	1		T27	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T161	10		T48	14		T217	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T11	5		T45	8		T26	23
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T38	3		T147	6		T125	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T11	15		T161	8		T193	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T2	12		T5	12		T147	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T119	7		T138	15		T239	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T223	13		T134	9		T222	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T7	7		T37	1		T116	24
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T6	2		T120	12		T122	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T5	12		T84	1		T239	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T48	1		T13	4		T247	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T46	1		T219	10		T290	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T137	3		T226	16		T18	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T2	4		T5	2		T37	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T303	10		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T137	1		T300	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T301	1		T302	1		T273	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T41	9		T304	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T127	7		T292	1		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T28	12		T126	1		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T9	1		T114	1		T39	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T2	1		T39	1		T123	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T5	7		T7	1		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T48	1		T233	2		T128	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T37	3		T38	3		T26	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T48	12		T155	1		T126	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T10	1		T12	1		T45	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T37	1		T161	1		T38	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T11	1		T161	1		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T2	21		T121	1		T147	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T11	1		T47	9		T121	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T5	6		T10	1		T223	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T37	1		T114	1		T47	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T114	1		T216	1		T129	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	328	1			T5	15		T7	1		T46	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1591	1			T1	2		T4	1		T6	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17628	1			T2	118		T3	11		T8	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T137	3		T300	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T302	16		T273	9		T305	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T41	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T292	1		T252	2		T296	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T28	10		T137	10		T274	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T39	2		T28	15		T115	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T2	1		T39	1		T123	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T5	6		T7	4		T11	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T48	1		T224	12		T88	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T37	1		T38	1		T26	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T48	14		T151	9		T217	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T45	8		T26	23		T27	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T161	10		T38	3		T147	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T11	5		T161	8		T137	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T2	12		T147	11		T130	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T11	15		T138	15		T239	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T5	12		T223	13		T134	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T37	1		T151	13		T124	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T239	12		T274	5		T252	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T5	12		T7	7		T46	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1202	1			T4	7		T6	2		T48	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T2	4		T5	2		T37	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T9	1		T115	3		T122	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T28	11		T126	1		T137	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T5	1		T114	1		T39	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1440	1			T1	2		T2	2		T4	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T5	7		T7	5		T11	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T39	2		T233	1		T151	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T37	2		T38	4		T27	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T37	1		T161	11		T48	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T10	1		T11	6		T12	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T38	5		T127	1		T147	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T11	16		T161	9		T191	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T2	16		T5	13		T121	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T47	2		T121	1		T119	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T10	1		T216	1		T223	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T7	8		T37	2		T114	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T6	3		T114	1		T120	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T5	13		T116	1		T118	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T48	2		T13	8		T126	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T46	2		T227	1		T219	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T10	1		T137	4		T236	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17786	1			T2	122		T3	11		T5	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T303	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T122	17		T191	11		T140	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T28	11		T41	6		T217	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T39	2		T28	6		T127	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1122	1			T29	14		T228	15		T123	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T5	5		T26	11		T123	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T233	1		T151	7		T128	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T37	2		T117	1		T223	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T48	11		T217	7		T34	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T45	15		T26	15		T125	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T38	2		T127	9		T147	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T191	9		T263	7		T306	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T2	17		T5	5		T147	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T47	18		T138	13		T15	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T223	13		T134	12		T245	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T127	2		T151	14		T124	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T6	10		T189	13		T224	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T5	14		T84	7		T14	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T13	3		T247	14		T134	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T46	1		T227	11		T307	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T236	7		T18	1		T308	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T137	4		T300	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T301	1		T302	17		T273	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T41	6		T304	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T127	1		T292	2		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T28	11		T126	1		T137	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T9	1		T114	1		T39	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T2	2		T39	2		T123	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T5	8		T7	5		T11	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T48	2		T233	1		T128	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T37	2		T38	4		T26	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T48	15		T155	1		T126	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T10	1		T12	1		T45	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T37	1		T161	11		T38	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T11	6		T161	9		T137	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T2	16		T121	1		T147	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T11	16		T47	1		T121	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T5	13		T10	1		T223	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T37	2		T114	1		T47	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T114	1		T216	1		T129	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	364	1			T5	13		T7	8		T46	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1565	1			T1	2		T4	8		T6	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17786	1			T2	122		T3	11		T5	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T300	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T273	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T41	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T127	6		T140	7		T252	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T28	11		T140	8		T274	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T39	2		T28	6		T122	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T123	9		T130	11		T217	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T5	5		T33	9		T123	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T233	1		T128	9		T224	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T37	2		T26	11		T86	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T48	11		T151	7		T217	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T45	15		T26	15		T117	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T38	2		T127	9		T147	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T156	10		T230	10		T262	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T2	17		T147	10		T125	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T47	8		T191	9		T138	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T5	5		T223	13		T134	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T47	10		T127	2		T151	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T245	18		T274	7		T252	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T5	14		T46	1		T84	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1228	1			T6	10		T13	3		T29	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22776

1

T1

2

T2

140

T3

11

auto[1]

auto[0]

3757

1

T2

17

T5

24

T6

10