Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26533

1

T1

2

T2

157

T3

11

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23120

1

T1

2

T2

122

T3

11

auto[ADC_CTRL_FILTER_COND_OUT]

3413

1

T2

35

T5

31

T7

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20676

1

T2

155

T3

11

T5

32

auto[1]

5857

1

T1

2

T2

2

T4

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22426

1

T1

2

T2

140

T3

11

auto[1]

4107

1

T2

17

T4

7

T5

32

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	275	1			T46	3		T147	14		T191	10
values[0]	2	1			T39	2		-	-		-	-
values[1]	523	1			T5	28		T10	1		T114	1
values[2]	733	1			T10	1		T11	7		T45	24
values[3]	853	1			T9	1		T11	6		T37	4
values[4]	620	1			T11	16		T38	4		T26	24
values[5]	941	1			T2	33		T6	13		T10	1
values[6]	669	1			T5	18		T12	1		T37	2
values[7]	543	1			T7	13		T47	11		T48	26
values[8]	498	1			T37	1		T13	11		T115	12
values[9]	3090	1			T1	2		T2	2		T4	8
minimum	17786	1			T2	122		T3	11		T5	2

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	526	1			T5	27		T10	1		T114	1
values[1]	816	1			T9	1		T10	1		T45	24
values[2]	648	1			T11	13		T37	4		T114	1
values[3]	766	1			T6	13		T11	16		T38	4
values[4]	946	1			T2	33		T10	1		T38	7
values[5]	625	1			T5	18		T7	5		T12	1
values[6]	2671	1			T1	2		T4	8		T7	8
values[7]	488	1			T37	1		T13	11		T130	2
values[8]	931	1			T5	12		T46	3		T161	11
values[9]	150	1			T2	2		T147	14		T191	10
minimum	17966	1			T2	122		T3	11		T5	3

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22776

1

T1

2

T2

140

T3

11

auto[1]

3757

1

T2

17

T5

24

T6

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T5	15		T114	1		T33	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T10	1		T47	9		T48	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T9	1		T45	16		T126	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T10	1		T116	1		T147	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T11	1		T48	1		T39	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T11	1		T37	3		T114	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T6	11		T11	1		T38	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T115	1		T121	1		T151	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T10	1		T38	4		T27	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T2	21		T26	28		T125	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T7	1		T37	1		T120	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T5	6		T12	1		T114	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1426	1			T1	2		T4	1		T267	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T7	1		T47	11		T217	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T37	1		T13	7		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T159	1		T35	10		T264	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T161	1		T121	1		T122	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T5	6		T46	2		T115	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T191	10		T222	1		T264	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T2	1		T147	8		T217	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17660	1			T2	118		T3	11		T8	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T5	1		T126	1		T266	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T5	12		T33	10		T123	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T48	1		T116	13		T137	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T45	8		T137	3		T217	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T116	11		T147	11		T124	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T11	6		T48	1		T39	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T11	5		T37	1		T161	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T6	2		T11	15		T38	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T115	2		T151	13		T123	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T38	3		T27	10		T137	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T2	12		T26	35		T125	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T7	4		T37	1		T120	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T5	12		T122	1		T223	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1036	1			T4	7		T48	14		T221	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T7	7		T217	7		T225	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T13	4		T130	1		T224	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T35	8		T264	11		T18	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T161	10		T122	14		T225	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T5	6		T46	1		T115	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T222	12		T264	7		T270	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T2	1		T147	6		T217	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T2	4		T5	2		T37	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T86	11		T134	10		T275	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T191	10		T16	5		T277	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T46	2		T147	8		T217	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T39	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T5	15		T114	1		T33	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T5	1		T10	1		T47	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T11	1		T45	16		T126	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T10	1		T147	11		T124	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T9	1		T48	1		T39	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T11	1		T37	3		T114	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T11	1		T38	3		T151	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T26	12		T115	1		T121	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T6	11		T10	1		T38	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T2	21		T26	16		T123	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T37	1		T120	1		T27	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T5	6		T12	1		T114	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T7	1		T48	12		T41	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T7	1		T47	11		T217	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T37	1		T13	7		T116	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T115	1		T225	12		T245	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1438	1			T1	2		T4	1		T161	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T2	1		T5	6		T129	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17628	1			T2	118		T3	11		T8	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T16	2		T264	7		T153	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T46	1		T147	6		T217	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T39	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T5	12		T33	10		T123	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T48	1		T116	13		T137	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T11	6		T45	8		T217	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T147	11		T124	22		T138	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T48	1		T39	2		T28	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T11	5		T37	1		T161	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T11	15		T38	1		T151	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T26	12		T115	2		T151	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T6	2		T38	3		T137	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T2	12		T26	23		T123	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T37	1		T120	12		T27	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T5	12		T122	1		T223	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T7	4		T48	14		T41	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T7	7		T217	7		T88	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T13	4		T130	1		T224	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T115	11		T225	13		T175	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1132	1			T4	7		T161	10		T221	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T2	1		T5	6		T84	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T2	4		T5	2		T37	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T5	13		T114	1		T33	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T10	1		T47	1		T48	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T9	1		T45	9		T126	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T10	1		T116	12		T147	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T11	7		T48	2		T39	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T11	6		T37	2		T114	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T6	3		T11	16		T38	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T115	3		T121	1		T151	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T10	1		T38	5		T27	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T2	16		T26	37		T125	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T7	5		T37	2		T120	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T5	13		T12	1		T114	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1372	1			T1	2		T4	8		T267	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T7	8		T47	1		T217	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T37	1		T13	8		T130	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T159	1		T35	9		T264	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T161	11		T121	1		T122	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T5	7		T46	2		T115	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T191	1		T222	13		T264	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T2	2		T147	7		T217	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17844	1			T2	122		T3	11		T5	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T5	1		T126	1		T266	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T5	14		T33	9		T123	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T47	8		T127	17		T156	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T45	15		T233	1		T217	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T147	10		T124	13		T189	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T39	2		T28	11		T232	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T37	2		T224	14		T197	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T6	10		T151	7		T124	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T151	14		T123	9		T247	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T38	2		T117	1		T125	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T2	17		T26	26		T125	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T28	6		T41	6		T130	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T5	5		T223	6		T230	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1090	1			T48	11		T29	14		T228	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T47	10		T217	6		T225	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T13	3		T191	11		T224	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T35	9		T264	16		T18	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T122	17		T225	2		T16	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T5	5		T46	1		T84	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T191	9		T264	8		T270	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T147	7		T217	7		T138	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T160	13		T309	13		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T86	11		T134	9		T140	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T191	1		T16	6		T277	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T46	2		T147	7		T217	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T39	2		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T5	13		T114	1		T33	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T5	1		T10	1		T47	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T11	7		T45	9		T126	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T10	1		T147	12		T124	23
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T9	1		T48	2		T39	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T11	6		T37	2		T114	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T11	16		T38	4		T151	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T26	13		T115	3		T121	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T6	3		T10	1		T38	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T2	16		T26	24		T123	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T37	2		T120	13		T27	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T5	13		T12	1		T114	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T7	5		T48	15		T41	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T7	8		T47	1		T217	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T37	1		T13	8		T116	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T115	12		T225	14		T245	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1480	1			T1	2		T4	8		T161	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T2	2		T5	7		T129	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17786	1			T2	122		T3	11		T5	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T191	9		T16	1		T264	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T46	1		T147	7		T217	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T5	14		T33	9		T123	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T47	8		T127	17		T86	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T45	15		T233	1		T217	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T147	10		T124	13		T189	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T39	2		T28	11		T232	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T37	2		T149	13		T224	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T151	7		T125	18		T134	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T26	11		T151	14		T247	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T6	10		T38	2		T124	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T2	17		T26	15		T123	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T28	6		T117	1		T149	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T5	5		T223	6		T230	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T48	11		T41	6		T130	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T47	10		T217	6		T88	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T13	3		T191	11		T128	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T225	11		T245	17		T175	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1090	1			T29	14		T228	15		T122	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T5	5		T84	7		T138	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22776

1

T1

2

T2

140

T3

11

auto[1]

auto[0]

3757

1

T2

17

T5

24

T6

10